CN109921754B - Power amplifier - Google Patents
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- CN109921754B CN109921754B CN201910112976.0A CN201910112976A CN109921754B CN 109921754 B CN109921754 B CN 109921754B CN 201910112976 A CN201910112976 A CN 201910112976A CN 109921754 B CN109921754 B CN 109921754B
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Abstract
The embodiment of the application discloses a power amplifier. The power amplifier includes: a transistor M which is a GAN high power transistor; a first bias voltage circuit 110, a second bias voltage circuit 120, an input matching circuit 130, and an output matching circuit 140; the input matching circuit 130 comprises a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 and one end of the second capacitor C2 are respectively connected with the gate of the transistor M, the other end of the first capacitor C1 and the other end of the second capacitor C2 are respectively connected with ground, and the first capacitor C1 and the second capacitor C2 are used for adjusting the input impedance of the input matching circuit 130; the output matching circuit 140 includes a first matching circuit for adjusting an output impedance of the output matching circuit 140.
Description
Cross-referencing
The present application claims priority from chinese patent No.201811141912.5 filed on 28/9/2018. The contents of the above-mentioned application are incorporated herein by reference.
Technical Field
The present disclosure relates to electronic technologies, and in particular, to a power amplifier.
Background
With the development of power amplification technology, the power consumption problem of the input signal in the form of heat dissipation and the like is more and more obvious, and when the output is 10W output, the Power Added Efficiency (PAE) can only reach 40%, which means that a large part of power is consumed in heat dissipation, the amplification efficiency is reduced, and the use cost is also increased. The existing technology needs to invest a great deal of cost to solve the problem of heat dissipation, the size of the power amplifier is large, and a heat sink, a fan and the like are added, so that the design and the light weight are greatly challenged. Therefore, there is a need to develop a power amplifier circuit to improve the power amplification efficiency and reduce the volume of the power amplification product.
Disclosure of Invention
One embodiment of the present application provides a power amplifier. The power amplifier includes: a transistor M which is a GAN high power transistor; a first bias voltage circuit 110, a second bias voltage circuit 120, an input matching circuit 130, and an output matching circuit 140; the input matching circuit 130 comprises a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 and one end of the second capacitor C2 are respectively connected with the gate of the transistor M, the other end of the first capacitor C1 and the other end of the second capacitor C2 are respectively connected with ground, and the first capacitor C1 and the second capacitor C2 are used for adjusting the input impedance of the input matching circuit 130; the output matching circuit 140 includes a first matching circuit for adjusting an output impedance of the output matching circuit 140.
In some embodiments, the transistor M employs a CGH 55030.
In some embodiments, the input matching circuit 130 further comprises: and a third capacitor C3, wherein one end of the third capacitor C3 is connected to the input port, and the other end of the third capacitor C3 is connected to the gate of the transistor M.
In some embodiments, the first matching circuit comprises: the first inductor L1, the first transmission line TL1 and the fourth capacitor C4, first ports of the first inductor L1 and the first transmission line TL1 are connected to the drain of the transistor M, a second port of the first inductor L1 is connected to the first bias voltage circuit 110, a second port of the first transmission line TL1 is connected to a first port of the fourth capacitor C4, and a second port of the fourth capacitor C4 is grounded.
In some embodiments, the width of the first transmission line TL1 is 1.75 millimeters and the length of the first transmission line TL1 ranges from 4.6 millimeters to 8.6 millimeters.
In some embodiments, the output matching circuit 140 further comprises: and a fifth capacitor C5, wherein one end of the fifth capacitor C5 is connected to the drain of the transistor M, and the other end of the fifth capacitor C5 is grounded.
In some embodiments, the output matching circuit 140 further comprises: and a sixth capacitor C6, wherein one end of the sixth capacitor C6 is connected to the first port of the fourth capacitor C4, and the other end of the sixth capacitor C6 is connected to an output port.
In some embodiments, the first bias voltage circuit 110 is configured to provide a threshold voltage to the transistor M, and includes: the transistor M comprises a first external power supply unit and a first direct current bias unit, wherein one end of the first direct current bias unit is connected with the grid electrode of the transistor M, and the other end of the first direct current bias unit is connected with the first external power supply unit.
In some embodiments, the second bias voltage circuit 120 is used for providing an operating voltage to the transistor M, and includes: the inductor comprises a second external power supply unit and a second direct current bias unit, wherein one end of the second direct current bias unit is connected with the second port of the first inductor L1, and the other end of the second direct current bias unit is connected with the second external power supply unit.
Drawings
The present application will be further explained by way of exemplary embodiments, which will be described in detail by way of the accompanying drawings. These embodiments are not intended to be limiting, and in these embodiments like numerals are used to indicate like structures, wherein:
fig. 1 is a schematic diagram of a basic structure of a power amplifier according to some embodiments of the present application;
fig. 2 is a schematic diagram of a specific structure of a power amplifier according to some embodiments of the present application;
fig. 3 is a schematic diagram of an emulated circuit of an input matching circuit of a power amplifier according to some embodiments of the present application;
FIG. 4 is a graph illustrating the resulting conjugate values and output impedance as a function of frequency, according to some embodiments of the present application;
fig. 5 is a schematic diagram of an emulated circuit of an output matching circuit of a power amplifier according to some embodiments of the present application;
fig. 6 is a smith chart of a power amplifier according to some embodiments of the present application;
fig. 7 is a schematic diagram of a specific structure of a power amplifier according to some embodiments of the present application;
fig. 8 is a schematic diagram of a PCB layout of a power amplifier according to some embodiments of the present application;
fig. 9 is a schematic diagram of the effect of a power amplifier according to some embodiments of the present application;
fig. 10 is a schematic diagram of the effect of a power amplifier according to some embodiments of the present application.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.
It should be understood that "system", "device", "unit" and/or "module" as used herein is a method for distinguishing different components, elements, parts, portions or assemblies at different levels. However, other words may be substituted by other expressions if they accomplish the same purpose.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, the various steps may be processed in reverse order or simultaneously. Meanwhile, other operations may be added to the processes, or a certain step or several steps of operations may be removed from the processes.
Fig. 1 is a schematic diagram of a power amplifier according to some embodiments of the present application.
As shown in fig. 1, the power amplifier may include: a transistor M which is a GAN high power transistor; a first bias voltage circuit 110, a second bias voltage circuit 120, an input matching circuit 130, and an output matching circuit 140; the input matching circuit 130 comprises a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 and one end of the second capacitor C2 are respectively connected with the gate of the transistor M, the other end of the first capacitor C1 and the other end of the second capacitor C2 are respectively connected with ground, and the first capacitor C1 and the second capacitor C2 are used for adjusting the input impedance of the input matching circuit 130; the output matching circuit 140 includes a first matching circuit for adjusting an output impedance of the output matching circuit 140.
The design method of the E-type power amplifier is adopted, the design method of the E-type power amplifier is specifically composed of a single transistor and a load network, the transistor is in a switch state under excitation of a radio-frequency signal to be amplified, a circuit designed based on the E-type power amplifier can enable the transistor to be conducted only when the voltage of a transistor to be amplified is reduced to the minimum, high voltage and large current can be prevented from existing at the same time, and therefore power loss of the radio-frequency signal to be amplified in the amplification and transmission processes can be reduced.
In the present application, a design method of a class E power amplifier is adopted, so that when an effective signal is input, the transistor M is in an amplification state, the input matching circuit 130 and the output matching circuit 140 are in a working state, and when no effective signal is input, the transistor M is in a closing state, and the input matching circuit 130 and the output matching circuit 140 are not in a working state. In some embodiments, the valid signal indicates that there is a radio frequency signal to be amplified, and the operating state indicates that the input matching circuit 130 and the output matching circuit 140 can respectively acquire the radio frequency signal to be amplified and can output the radio frequency signal amplified by a transistor.
The transistor M is used for amplifying the radio frequency signal to be amplified and transmitting the amplified radio frequency signal to the output matching circuit. In some embodiments, the transistor M employs a CGH 55030.
The CGH55030 chip is a high-power GaN transistor of CREE company, and can be applied to the design of a broadband high-power amplifier.
In some embodiments, the input matching circuit 130 can perform matching according to the input impedance of a transistor M (e.g., a CGH55030 chip) by combining the frequency band characteristic and the internal resistance of the input signal to be amplified, so that the input signal to be amplified is input into the transistor M with the maximum power. According to the matching of the elements in the output matching circuit 140, the output matching circuit 140 can perform matching by combining the frequency band characteristic and the internal resistance of the input signal to be amplified according to the output impedance characteristic of the transistor M (for example, a CGH55030 chip), so that the signal subjected to power amplification processing by the transistor M is output with the maximum power.
Fig. 2 is a schematic diagram of a specific structure of a power amplifier according to some embodiments of the present application.
As shown in fig. 2, the input matching circuit 130 is configured to receive a radio frequency signal to be amplified and transmit the radio frequency signal to be amplified to the transistor M, and may further include: and a third capacitor C3, wherein one end of the third capacitor C3 is connected to the input port, and the other end of the third capacitor C3 is connected to the gate of the transistor M.
In some embodiments, the third capacitor C3 may be used for dc blocking. The reactance formed by the first capacitor C1 and the second capacitor C2 provides an impedance matched to the normal operation of the transistor M. In some embodiments, the first capacitor C1 and the second capacitor C2 may be disposed at a relatively close distance from the transistor M.
In some embodiments, in the input matching circuit 130, the maximum power of the input signal may be set not to exceed 31dbm and the frequency range of the input signal may be set to 2.4-2.5GHz according to the characteristics of the transistor M.
As an alternative example of the present application, the capacitance value of the first capacitor C1 may be 1.8pF, the capacitance value of the second capacitor C2 may be 1.8pF, and the capacitance value of the third capacitor C3 may be 6.8 pF.
As shown in fig. 2, the Pin port is an input port of the input matching circuit 130, and the Pout port is an output port of the output matching circuit 140.
Fig. 3 is a schematic diagram of an emulated circuit of an input matching circuit of a power amplifier, shown in some embodiments in accordance with the present application.
In some embodiments, circuit parameters required for circuit simulation may be set, including substrate relative dielectric constant Er, substrate thickness H, metal layer thickness T, surface roughness Rho, loss tangent Tsnd, etc., for example, Er is set to 3.55, H to 0.813 millimeters, T to 0.07 millimeters, Rho to 1, Tsnd to 0.0021. As shown in fig. 3, the port P1 is connected to one end of a transmission line TL3, the other end of the transmission line TL3 is connected to one end of a capacitor C4, the other end of the capacitor C4 is connected to one end of a transmission line TL1, the other end of the transmission line TL1 is connected to one end of an inductor S2, a capacitor C1 and one end of a transmission line TL2, the other end of the inductor S2 is connected to a capacitor C5 and the port P3, the other end of the capacitor C5 is grounded, the other end of the capacitor C1 is grounded, the other end of the transmission line TL2 is connected to the port P2, the ports P1, P2 and P3 are ports, and the equivalent impedances; the transmission line TL1 was set to be 10 mm in length and 1.75 mm in width; the transmission line TL2 was set to have a length of 1.7 mm and a width of 1.75 mm; the transmission line TL3 was set to be 5 mm in length and 1.75 mm in width; setting the capacitance value of the capacitor C1 to be 3 pF; setting the capacitance value of the capacitor C4 to be 6.8 pF; setting the capacitance value of the capacitor C5 to be 6.8 pF; the inductance value of the inductor S2 was set to 18.5 nH.
As shown in fig. 3, the capacitor C4 and the capacitor C5 may be used for dc blocking; the inductor S2 is a radio frequency choke coil, and can be used for isolating the dc path and the rf/microwave path, and eliminating the coupling between the ac signal and the dc source and ground.
Fig. 4 is a smith chart of the conjugate value and the output impedance as a function of frequency obtained from a test performed on a simulation circuit of the input matching circuit shown in fig. 3.
As shown in fig. 4, in the smith chart, the conjugate value is in the lower half circle, x is <0, and thus the reactance property is capacitive reactance, which conforms to the simulation circuit diagram shown in fig. 3. In some embodiments, the impedance is matched by selecting an appropriate matching element (e.g., capacitance, inductance, transmission line, etc.) according to a target range of matching impedances in a smith chart.
Fig. 5 is a schematic diagram of an emulated circuit of an output matching circuit of a power amplifier, shown in some embodiments in accordance with the application.
In some embodiments, circuit parameters required for circuit simulation may be set, including substrate relative dielectric constant Er, substrate thickness H, metal layer thickness T, surface roughness Rho, loss tangent Tsnd, etc., for example, Er is set to 3.55, H to 0.813 millimeters, T to 0.07 millimeters, Rho to 1, Tsnd to 0.0021. As shown in fig. 3, the port P1 is connected to one end of each of the capacitor C1, the transmission line TL2, and the inductor S1, the other end of the capacitor C1 is grounded, the other end of the transmission line TL2 is connected to one end of each of the capacitor C7 and the capacitor C4, the other end of the capacitor C7 is grounded, the other end of the capacitor C4 is connected to the port P2, the other end of the inductor S1 is connected to one end of each of the inductor S2 and the capacitor C3, the other end of the capacitor C3 is grounded, the other end of the inductor S2 is connected to the capacitor C5 and the port P3, and the other end of the capacitor C686. P1, P2 and P3 are ports, and the equivalent impedances are all 50 ohms; the transmission line TL1 was set to 6.6 mm in length and 1.75 mm in width; setting the capacitance value of the capacitor C1 to be 1.5 pF; setting the capacitance value of the capacitor C3 to be 6.8 pF; setting the capacitance value of the capacitor C4 to be 6.8 pF; setting the capacitance value of the capacitor C5 to be 6.8 pF; setting the capacitance value of the capacitor C7 to be 2 pF; setting the capacitance value of the capacitor C5 to be 6.8 pF; setting the inductance value of the inductor S1 to be 2.5 nH; the inductance value of the inductor S2 was set to 18.5 nH.
As shown in fig. 2, the output circuit 140 is configured to receive the amplified radio frequency signal and transmit the amplified radio frequency signal to an output port, and may include: a first matching circuit, a fifth capacitor C5 and a sixth capacitor C6.
In some embodiments, the first matching circuit comprises: the first inductor L1, the first transmission line TL1 and the fourth capacitor C4, first ports of the first inductor L1 and the first transmission line TL1 are connected to the drain of the transistor M, a second port of the first inductor L1 is connected to the first bias voltage circuit 110, a second port of the first transmission line TL1 is connected to a first port of the fourth capacitor C4, and a second port of the fourth capacitor C4 is grounded.
It should be noted that the "first port" and the "second port" are only used to distinguish two ports of a circuit element, so as to illustrate a connection structure of the circuit element and other circuit elements.
In some embodiments, the fourth capacitor C4 and the first inductor L1 are connected in series to form a series resonant circuit that resonates at the fundamental frequency of the input signal. The fourth capacitor C4 and the second inductor L1 are connected through the first transmission line TL1, and the amplification efficiency can be optimized by changing the length between the first transmission lines TL1, so that the phase relationship between the voltage and the current on the transmission lines is changed, and the product of the two is always kept to a minimum, thereby minimizing the heat loss.
In some embodiments, the width of the first transmission line TL1 is 1.75 millimeters and the length of the first transmission line TL1 ranges from 4.6 millimeters to 8.6 millimeters. The first transmission line TL1 may be used to adjust the overall impedance of the output matching circuit 140 so that the impedance of the output matching circuit 140 matches the impedance of the normal operation of the transistor M.
In some embodiments, the output matching circuit 140 further comprises: and a fifth capacitor C5, wherein one end of the fifth capacitor C5 is connected to the drain of the transistor M, and the other end of the fifth capacitor C5 is grounded.
In some embodiments, the fifth capacitor C5 may generate self-oscillation, which may short the second order harmonics of the input signal directly to ground, thereby filtering out the second order harmonics in the output signal.
In some embodiments, the output matching circuit 140 further comprises: and a sixth capacitor C6, wherein one end of the sixth capacitor C6 is connected to the first port of the fourth capacitor C4, and the other end of the sixth capacitor C6 is connected to an output port.
In some embodiments, the sixth capacitor C6 may be used for dc blocking.
As an alternative example of the present application, the capacitance value of the sixth capacitor C6 may be 6.8uF, the capacitance value of the fifth capacitor C5 may be 1.2pF, the capacitance value of the fourth capacitor C4 may be 2pF, the inductance value of the first inductor L1 may be 2.5nH, and the length and width of the first transmission line TL1 may be 6.6 mm and 1.75 mm, respectively.
Fig. 6 is a smith chart of a power amplifier according to some embodiments of the present application.
As shown in fig. 5, the capacitor C1 will generate self-oscillation, so that the second-order rf signal can be directly shorted to ground, and the second-order harmonic in the output signal is filtered out, the inductor L1 and the capacitor C7 are connected in series to form a series resonant circuit resonant at the fundamental frequency of the signal, and by changing the length of the transmission line TL2 between the two, the phase relationship between the voltage and the current on the transmission line TL2 can be changed, so that the product of the two is always kept to be minimum, thereby minimizing the heat loss and optimizing the efficiency; capacitors C3 and C4 may be used for dc blocking; the inductor L2 is an rf choke that can be used to isolate the dc path from the rf/microwave path and to decouple the ac signal from the dc source and ground. As shown in fig. 6, smith charts corresponding to frequency points of 2.4GHz, 2.45GHz and 2.5GHz are respectively displayed.
Fig. 7 is a schematic diagram of a specific structure of a power amplifier according to some embodiments of the present application;
as shown in fig. 7, the first bias voltage circuit 110 may include: the circuit comprises a first external power supply unit, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a second inductor L2 and a first resistor Rs, wherein one end of the second inductor L2 is connected with the gate of the transistor M, the other end of the second inductor L2 is connected with one end of a first resistor RS, the other end of the first resistor RS is respectively connected with one ends of the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11 and the twelfth capacitor C12, and the first external power supply unit, and the other ends of the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11 and the twelfth capacitor C12 are respectively grounded.
In some embodiments, the first bias voltage circuit 110 provides the transistor M with the threshold voltage required for its normal operation. The threshold voltage value may be set according to the characteristics of the transistor M. For example, the transistor M requires a threshold voltage value of-2.8V, and the first bias voltage circuit 110 provides a threshold voltage of-2.8V by controlling the first external power supply unit. It should be noted that the first bias voltage circuit 110 is not limited to the above-described circuit structure, and any circuit structure capable of providing a dc voltage can be used as the first bias voltage circuit for providing a threshold voltage to the transistor M.
In some embodiments, a circuit structure formed by the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11 and the twelfth capacitor C12 may be used to provide the dc bias. The second inductor L2 may be an rf choke, and may be used as a dc path and rf/microwave path isolation to eliminate coupling between the ac signal and the dc source and ground. The circuit structure formed by the first resistor Rs and the second inductor L2 connected in series can be used to increase the stability of impedance.
As an alternative example of the present application, the capacitance value of the seventh capacitor C7 may be 6.8pF, the capacitance value of the eighth capacitor C8 may be 1nF, the capacitance value of the ninth capacitor C9 may be 10nF, the capacitance value of the tenth capacitor C10 may be 100nF, the capacitance value of the eleventh capacitor C11 may be 1uF, the capacitance value of the twelfth capacitor C12 may be 10uF, the inductance value of the second inductor L2 may be 18.5nH, and the resistance value of the first resistor Rs may be 51 ohms.
In some embodiments, the first external power supply unit may include an external power supply or a direct current-to-direct current (DC-DC) source. The external power source may be a dc base power source (e.g., a lithium battery and/or a dc power lamp). The dc-to-dc source may be a dc conversion device that converts a dc base power supply voltage to another voltage. In some embodiments, the dc-to-dc source may convert the dc base power voltage according to a preset pulse width, or the dc-to-dc source may convert the dc base power voltage by accepting a preset control command.
As shown in fig. 7, the second bias voltage circuit 120 includes: a second external power supply unit, a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, a seventeenth capacitor C17, an eighteenth capacitor C18, a nineteenth capacitor C19, and a third inductor L3, wherein one end of each of the third inductor L3 and the thirteenth capacitor C13 is connected to the second port of the first inductor L1, the other end of the thirteenth capacitor C13 is grounded, the other end of the third inductor L3 is connected to one end of each of the second external power supply unit, the fourteenth capacitor C14, the fifteenth capacitor C15, the sixteenth capacitor C16, the seventeenth capacitor C17, the eighteenth capacitor C18, and the nineteenth capacitor C19, and the other ends of the fourteenth capacitor C14, the fifteenth capacitor C15, the sixteenth capacitor C16, the seventeenth capacitor C17, the eighteenth capacitor C18, and the nineteenth capacitor C19 are grounded, respectively.
In some embodiments, the second bias voltage circuit 120 provides the transistor M with an operating voltage required for its normal operation. The operation limit voltage value may be set according to the characteristics of the transistor M. For example, the transistor M needs an operating voltage value of 30V, and the second bias voltage circuit 120 controls the first external power supply unit to provide the operating voltage of 30V. It should be noted that the second bias voltage circuit 120 is not limited to the above-described circuit structure, and any circuit structure capable of providing a dc voltage can be used as the second bias voltage circuit for providing an operating voltage to the transistor M.
The third inductor L3 may be an rf choke, and may be used as a dc path and an rf/microwave path for isolation, eliminating coupling between the ac signal and a dc source and ground. The circuit formed by the thirteenth capacitor C13, the fourteenth capacitor C14, the fifteenth capacitor C15, the sixteenth capacitor C16, the seventeenth capacitor C17, the eighteenth capacitor C18, the nineteenth capacitor C19 and the third inductor L3 can be used for providing direct current bias.
As an alternative example of the present application, the capacitance value of the thirteenth capacitor C13 may be 6.8pF, the capacitance value of the fourteenth capacitor C14 may be 6.8pF, the capacitance value of the fifteenth capacitor C15 may be 1nF, the capacitance value of the sixteenth capacitor C16 may be 10nF, the capacitance value of the seventeenth capacitor C17 may be 100nF, the capacitance value of the eighteenth capacitor C18 may be 1uF, the capacitance value of the nineteenth capacitor C19 may be 10uF, and the inductance value of the third inductor L2 may be 18.5 nH.
In some embodiments, the second external power supply unit may include an external power supply or a direct current-to-direct current (DC-DC) source. The external power source may be a dc base power source (e.g., a lithium battery and/or a dc power lamp). The dc-to-dc source may be a dc conversion device that converts a dc base power supply voltage to another voltage. In some embodiments, the dc-to-dc source may convert the dc base power voltage according to a preset pulse width, or the dc-to-dc source may convert the dc base power voltage by accepting a preset control command.
Fig. 8 is a schematic diagram of a PCB layout of a power amplifier according to some embodiments of the present application.
As shown in fig. 8, the capacitor Cp1 and the capacitor Cp2 correspond to the fifth capacitor C5 and the fourth capacitor C4, respectively, as shown in fig. 2, in some embodiments, the distance between the capacitor Cp1 and the capacitor Cp2, as shown in fig. 8, can be fine-tuned, and the inductance and the capacitance of the transmission line can be adjusted by adjusting the distance between the capacitor Cp1 and the capacitor Cp2, so that the impedance of the CGH55030 chip in the processing circuit can be matched, and therefore the performance of the power amplifier and the strength of the final output signal can be further improved. As shown in fig. 8, the capacitor Cin1 and the capacitor Cin2 correspond to the first capacitor C1 and the second capacitor C2 shown in fig. 2, respectively, and in some embodiments, the capacitor Cin1 and the capacitor Cin2 are disposed at a relatively close distance from the transistor M.
Fig. 9 is a schematic diagram of the effect of a power amplifier according to some embodiments of the present application.
As shown in fig. 9, the abscissa represents the voltage of the operating voltage VDD of the power amplifier, the ordinate on the left side represents the power of the output signal of the power amplifier, and the ordinate on the right side represents the Power Added Efficiency (PAE) of the corresponding operating voltage of the power amplifier. Under the condition that the power of an input signal is 29dBm and the frequency of the input signal is a frequency point of 2.45 GHz), when the value of the working voltage VDD is increased from 25V to 31V, the PAE and the output power corresponding to the input signal are gradually increased.
Fig. 10 is a schematic diagram of the effect of a power amplifier according to some embodiments of the present application.
As shown in fig. 10, the abscissa represents the frequency of the input signal of the power amplifier, the ordinate on the left side represents the power of the output signal of the power amplifier, and the ordinate on the right side represents the PAE of the corresponding frequency of the power amplifier. As shown in fig. 9, when the power of the input signal is 28dBm, the PAE and the output power corresponding to the input signal gradually decrease when the frequency of the input signal increases from 2.4GHz to 2.5 GHz.
The beneficial effects that may be brought by the embodiments of the present application include, but are not limited to: (1) when the CGH55030 chips are included in the processing circuit, the power of output signals exceeds 40dbm in the frequency band range of 2.4-2.5GHz under the condition that the power of input signals is 30dbm, and the PAE reaches more than 70%, so that the heat loss is greatly reduced, the input of heat dissipation cost is reduced, and the service life and the efficiency of the power amplifier are greatly improved. (2) The first capacitor C1 and the second capacitor C2 are added in the input matching circuit, so that the matching of the whole circuit is simpler and more effective. (3) The first transmission line TL1 is added in the output matching circuit, and the length and the width of the first transmission line TL1 are adjusted, so that the matching of the whole circuit is simpler and more effective. It is to be noted that different embodiments may produce different advantages, and in different embodiments, any one or combination of the above advantages may be produced, or any other advantages may be obtained.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing detailed disclosure is to be considered merely illustrative and not restrictive of the broad application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Moreover, those skilled in the art will appreciate that aspects of the present application may be illustrated and described in terms of several patentable species or situations, including any new and useful combination of processes, machines, manufacture, or materials, or any new and useful improvement thereon. Accordingly, various aspects of the present application may be embodied entirely in hardware, entirely in software (including firmware, resident software, micro-code, etc.) or in a combination of hardware and software. The above hardware or software may be referred to as "data block," module, "" engine, "" unit, "" component, "or" system. Furthermore, aspects of the present application may be represented as a computer product, including computer readable program code, embodied in one or more computer readable media.
The computer storage medium may comprise a propagated data signal with the computer program code embodied therewith, for example, on baseband or as part of a carrier wave. The propagated signal may take any of a variety of forms, including electromagnetic, optical, etc., or any suitable combination. A computer storage medium may be any computer-readable medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code located on a computer storage medium may be propagated over any suitable medium, including radio, cable, fiber optic cable, RF, or the like, or any combination of the preceding.
Computer program code required for the operation of various portions of the present application may be written in any one or more programming languages, including an object oriented programming language such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C + +, C #, VB.NET, Python, and the like, a conventional programming language such as C, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, a dynamic programming language such as Python, Ruby, and Groovy, or other programming languages, and the like. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any network format, such as a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet), or in a cloud computing environment, or as a service, such as a software as a service (SaaS).
Additionally, the order in which elements and sequences of the processes described herein are processed, the use of alphanumeric characters, or the use of other designations, is not intended to limit the order of the processes and methods described herein, unless explicitly claimed. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
The entire contents of each patent, patent application publication, and other material cited in this application, such as articles, books, specifications, publications, documents, and the like, are hereby incorporated by reference into this application. Except where the application is filed in a manner inconsistent or contrary to the present disclosure, and except where the claim is filed in its broadest scope (whether present or later appended to the application) as well. It is noted that the descriptions, definitions and/or use of terms in this application shall control if they are inconsistent or contrary to the statements and/or uses of the present application in the material attached to this application.
Finally, it should be understood that the embodiments described herein are merely illustrative of the principles of the embodiments of the present application. Other variations are also possible within the scope of the present application. Thus, by way of example, and not limitation, alternative configurations of the embodiments of the present application can be viewed as being consistent with the teachings of the present application. Accordingly, the embodiments of the present application are not limited to only those embodiments explicitly described and depicted herein.
Claims (8)
1. A power amplifier, comprising:
a transistor M which is a GAN high power transistor;
a first bias voltage circuit 110, a second bias voltage circuit 120, an input matching circuit 130, and an output matching circuit 140; wherein the first bias voltage circuit 110 and the input matching circuit 130 are connected to the gate of the transistor M, and the second bias voltage circuit 120 and the output matching circuit 140 are connected to the drain of the transistor M;
the input matching circuit 130 comprises a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 and one end of the second capacitor C2 are respectively connected with the gate of the transistor M, the other end of the first capacitor C1 and the other end of the second capacitor C2 are respectively connected with ground, and the first capacitor C1 and the second capacitor C2 are used for adjusting the input impedance of the input matching circuit 130;
the output matching circuit 140 includes a first matching circuit for adjusting an output impedance of the output matching circuit 140; the first matching circuit comprises a first inductor L1, a first transmission line TL1 and a fourth capacitor C4, wherein first ports of the first inductor L1 and the first transmission line TL1 are connected with a drain of the transistor M, a second port of the first inductor L1 is connected with the second bias voltage circuit 120, a second port of the first transmission line TL1 is connected with a first port of the fourth capacitor C4, and a second port of the fourth capacitor C4 is grounded.
2. The amplifier of claim 1, wherein the transistor M is a CGH 55030.
3. The amplifier of claim 1, wherein the input matching circuit 130 further comprises:
and a third capacitor C3, wherein one end of the third capacitor C3 is connected to the input port, and the other end of the third capacitor C3 is connected to the gate of the transistor M.
4. The amplifier of claim 1, wherein the width of the first transmission line TL1 is 1.75 millimeters and the length of the first transmission line TL1 ranges from 4.6 millimeters to 8.6 millimeters.
5. The amplifier of claim 1, wherein the output matching circuit 140 further comprises: and a fifth capacitor C5, wherein one end of the fifth capacitor C5 is connected to the drain of the transistor M, and the other end of the fifth capacitor C5 is grounded.
6. The amplifier of claim 1, wherein the output matching circuit 140 further comprises: and a sixth capacitor C6, wherein one end of the sixth capacitor C6 is connected to the first port of the fourth capacitor C4, and the other end of the sixth capacitor C6 is connected to an output port.
7. The amplifier of claim 1, wherein the first bias voltage circuit 110 is configured to provide a threshold voltage to the transistor M, comprising:
the transistor M comprises a first external power supply unit and a first direct current bias unit, wherein one end of the first direct current bias unit is connected with the grid electrode of the transistor M, and the other end of the first direct current bias unit is connected with the first external power supply unit.
8. The amplifier of claim 1, wherein the second bias voltage circuit 120 for providing an operating voltage to the transistor M comprises:
the second external power supply unit and the second dc bias unit, the second dc bias unit is connected to the second port of the first inductor L1, and the other end of the second dc bias unit is connected to the second external power supply unit.
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| CN201910112976.0A Active CN109921754B (en) | 2018-09-28 | 2019-02-13 | Power amplifier |
| CN201910112870.0A Pending CN109921752A (en) | 2018-09-28 | 2019-02-13 | A kind of power amplifier |
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| CN112910418B (en) * | 2021-01-15 | 2022-07-29 | 电子科技大学 | Ultra-wideband chip biasing circuit structure |
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| CN107809218A (en) * | 2017-10-26 | 2018-03-16 | 天津大学 | Double frequency narrow band power amplifier intervalve matching circuit for GaN power devices |
| CN108494375A (en) * | 2018-04-18 | 2018-09-04 | 电子科技大学 | A kind of distributed power amplifier of integrated reconfigurable notch filter |
| CN108574465A (en) * | 2018-06-27 | 2018-09-25 | 成都嘉纳海威科技有限责任公司 | A kind of high efficiency F classes stacking power amplifier based on left-and-right-hand transmission line |
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| CN101662263B (en) * | 2008-08-27 | 2012-11-21 | 中国科学院微电子研究所 | Bias circuit for Ku-band matched field effect transistor |
| JP2010087934A (en) * | 2008-09-30 | 2010-04-15 | Panasonic Corp | Matching circuit, high-frequency power amplifier and cellular phone |
| KR101079015B1 (en) * | 2009-11-18 | 2011-11-01 | 순천향대학교 산학협력단 | Dual Band High Frequency Amplifier using Composite Right/Left Handed Transmission Line |
| US20110285473A1 (en) * | 2010-05-24 | 2011-11-24 | Coherent, Inc. | Impedance-matching transformers for rf driven co2 gas discharge lasers |
| CN101867349B (en) * | 2010-07-01 | 2012-11-21 | 华为技术有限公司 | Radio frequency power amplifier |
| CN102255606B (en) * | 2011-07-25 | 2014-01-01 | 中国科学院微电子研究所 | Solid-state radio frequency power supply based on E-type power amplifying circuit |
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| CN107809218A (en) * | 2017-10-26 | 2018-03-16 | 天津大学 | Double frequency narrow band power amplifier intervalve matching circuit for GaN power devices |
| CN108494375A (en) * | 2018-04-18 | 2018-09-04 | 电子科技大学 | A kind of distributed power amplifier of integrated reconfigurable notch filter |
| CN108574465A (en) * | 2018-06-27 | 2018-09-25 | 成都嘉纳海威科技有限责任公司 | A kind of high efficiency F classes stacking power amplifier based on left-and-right-hand transmission line |
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| CN109921752A (en) | 2019-06-21 |
| CN109921753A (en) | 2019-06-21 |
| CN109921753B (en) | 2020-12-22 |
| CN109921754A (en) | 2019-06-21 |
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