CN109920776A - It is used as the composition of expendable material and the method using composition in semiconductor technology - Google Patents
It is used as the composition of expendable material and the method using composition in semiconductor technology Download PDFInfo
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- CN109920776A CN109920776A CN201910179659.0A CN201910179659A CN109920776A CN 109920776 A CN109920776 A CN 109920776A CN 201910179659 A CN201910179659 A CN 201910179659A CN 109920776 A CN109920776 A CN 109920776A
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Abstract
This disclosure relates to it is used as the composition of expendable material and the method using the composition in semiconductor technology, the method and eatch-back carving method of method, manufacturing semiconductor devices including making metal interconnect.The composition includes main monomer, additive and solvent, wherein it includes the organic compound of the aromatic ring with OH unit that the main monomer, which is, and the additive is the organic compound for including OH unit and acrylic.
Description
Technical field
This disclosure relates to it is used as the composition of expendable material, the method using the composition in semiconductor processing, including
The method of making metal interconnect, the method for manufacturing semiconductor devices and eatch-back carving method.
Background technique
As the size of semiconductor devices is smaller and smaller, often occurs multi-layer stack thin film structure in the semiconductor device.
When forming multi-layer stack thin film structure, usually make photoresist keep it is thin so that pattern collapse minimize and it is patterned
The pattern is then transferred to the sacrificial material layer under patterned photoresist by thin layer, with can be by after generating
Etch into the high aspect ratio features in following semiconductor material.Expendable material to by pattern from patterned thin photoresist
Pattern transfer of the agent into substrate has increasingly important role.The key property of expendable material includes anti-swing performance, erosion
Carve controllability, resistive properties, planarization performance and gap-filling properties.For example, when expendable material is (opposite as primer
It is primer for photoresist) when being formed on the pattern of substrate, the planarization of expendable material and gap
Filling capacity is receive a lot of attention.
Therefore, the application with expendable material in semiconductor field is more and more wider, it is desirable to provide improved expendable material
And the method using this improved expendable material manufacturing semiconductor devices.
Summary of the invention
One purpose of the disclosure is to provide a kind of composition as expendable material and utilization in semiconductor processing
The method of the composition, the method and eatch-back carving method of method, manufacturing semiconductor devices including making metal interconnect.
According to the disclosure in a first aspect, providing a kind of composition for being used as expendable material in semiconductor processing.It should
Composition includes main monomer, additive and solvent, wherein the main monomer is to include organising for the aromatic ring with OH unit
Object is closed, and the additive is the organic compound for including OH unit and acrylic.
According to the second aspect of the disclosure, a kind of method for making metal interconnection is provided.This method comprises: providing
Substrate is formed with stack of dielectric layers in the substrate；First etching is carried out to the stack of dielectric layers, is prolonged with being formed
Extend through the through-hole of the stack of dielectric layers；Sacrificial material layer is coated on the surface of the stack of dielectric layers, it is described sacrificial
Domestic animal material layer is at least filled up completely the through-hole, wherein the sacrificial material layer includes according to foregoing composition；To institute
It states sacrificial material layer and carries out etch-back, the expendable material in a part to be only remained in the through-hole；To the dielectric layer
It stacks and carries out the second etching, to form the first opening, wherein the first opening being filled out by the expendable material in the through-hole
Above a part filled and there is the size for being greater than the through-hole；The expendable material in the through-hole is removed, to form second
Opening, wherein second opening and first open communication；And it forms filling first opening and described second and opens
The metal layer of mouth.
According to the third aspect of the disclosure, a kind of method being used for producing the semiconductor devices is provided.This method comprises: mentioning
For substrate, the pattern with step is formed in the substrate；Sacrificial material layer is coated on the pattern, wherein institute
Stating sacrificial material layer includes foregoing composition；Photoresist is coated in the sacrificial material layer；To described photic
Resist is patterned；And the sacrificial material layer is etched using patterned photoresist as exposure mask,
It is transferred in the sacrificial material layer with the pattern in the photoresist that will be patterned into.
According to the fourth aspect of the disclosure, a kind of method for carrying out etch-back is provided.This method comprises: providing lining
Bottom is formed with the pattern with opening in the substrate；Sacrificial material layer is coated on the pattern, wherein the sacrifice
Material layer fills the opening, and wherein the sacrificial material layer includes foregoing composition；To the expendable material
Layer carries out etch-back, so that the pattern planarization.
According to the 5th of the disclosure the aspect, use of the foregoing composition at least one of following technique is provided
On the way: multilayer photoresist technique, etch back process, dual damascene via first process, the technique for manufacturing FinFET
And 3D integrated technique.
According to the one of the embodiment of the present disclosure the advantage is that the additive in the composition is used during the solidification of composition
Make crosslinking agent, accelerate the crosslinking of main monomer so that main monomer lower than decomposition temperature at a temperature of crosslink, to prevent
The distillation of main monomer, so that the planarization performance and gap-filling properties of composition are improved.
It is according to another advantage of the embodiment of the present disclosure, by using with improved planarization performance and gap
The composition of filling capacity, the method that manufacturing semiconductor devices can be modified to, and thus to obtain having improved properties
Semiconductor devices.
By the detailed description referring to the drawings to the exemplary embodiment of the disclosure, the other feature of the disclosure and its
Advantage will become apparent.
Detailed description of the invention
The attached drawing for constituting part of specification describes the embodiment of the present disclosure, and together with the description for explaining
The principle of the disclosure.
The disclosure can be more clearly understood according to following detailed description referring to attached drawing, in which:
Fig. 1 shows mutual as expendable material production metal using the composition of at least one embodiment according to the disclosure
The flow chart of method even.
Fig. 2A-Fig. 2 L shows the partial cross section pictorial image of semiconductor device corresponding with the part steps of the method for Fig. 1.
Fig. 3 shows the method for the composition manufacturing semiconductor devices for utilizing at least one embodiment according to the disclosure
Flow chart.
Fig. 4 A- Fig. 4 G shows the partial cross section pictorial image of semiconductor device corresponding with the part steps of the method for Fig. 3.
Fig. 5 shows the process that the method for etch-back is carried out using the composition according at least one embodiment of the disclosure
Figure.
Fig. 6 A- Fig. 6 C shows the partial cross section diagram of the semiconductor device of the part steps of the method corresponding to Fig. 5
Figure.
Note that same appended drawing reference is used in conjunction between different attached drawings sometimes in embodiments described below
It indicates same section or part with the same function, and omits its repeated explanation.In the present specification, using similar mark
Number and letter indicate similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair
It is further discussed.
In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. do not indicate practical sometimes
Position, size and range etc..Therefore, disclosed invention is not limited to position, size and range disclosed in attached drawing etc. etc..
Specific embodiment
The various exemplary embodiments of the disclosure are described in detail now with reference to attached drawing.It should also be noted that unless in addition having
Body explanation, the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
Scope of disclosure.
Be to the description only actually of at least one exemplary embodiment below it is illustrative, never as to the disclosure
And its application or any restrictions used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as authorizing part of specification.
It is shown here and discuss all examples in, any occurrence should be construed as merely illustratively, without
It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
In at least one embodiment of the disclosure, a kind of combination for being used as expendable material in semiconductor processing is provided
Object.The composition master includes monomer X1, additive Y1 and solvent, wherein main monomer be include having for the aromatic ring with OH unit
Machine compound, and additive is the organic compound for including OH unit and acrylic.
In one example, main monomer X1 is, for example, the organic compound with following formula:
In one example, additive Y1 is, for example, the organic compound with following formula:
In one example, the weight percent of additive is 15%-25%, the poidometer based on main monomer X1.
In one example, it can be coated using Spun-on carbon (SOC) technique according to the composition of the embodiment of the present disclosure.With change
It learns vapor deposition (CVD) to compare, SOC technique is cheaper and more preferable to the planarization on surface.
In one example, it can utilize heat to be solidified according to the composition of the embodiment of the present disclosure.For example, at one
It, can be by baking so that solvent is removed from composition, and is cured composition in embodiment.
According to the composition of the embodiment of the present disclosure, when being baked, the solidification of additive in composition in composition
Period be used as crosslinking agent, accelerate the crosslinking of main monomer so that main monomer lower than decomposition temperature at a temperature of crosslink, from
And the distillation of main monomer is prevented, so that the planarization performance and gap-filling properties of composition are improved.
The composition of check sample and the composition according to the embodiment of the present disclosure is shown in following table.
Table 1
Consider following test: the composition of check sample and the embodiment of the present disclosure being respectively coated on to be formed on substrate
On pattern, baking conditions are 180 DEG C/min to 230 DEG C/min.According to experimental result, in the test using check sample,
Main monomer X1 distils, and in the test using the composition of the embodiment of the present disclosure, there is no distillations by main monomer X1.
Additionally, it is contemplated that following test: use respectively the embodiment of the present disclosure composition and check sample composition as
Expendable material forms the intensive contact bore region of Damascus via-first technique.According to experimental result, for using the disclosure
The test of the composition of embodiment, the flatness of acquisition are about 16nm to 18nm, and for using the test of check sample, it obtains
The planarization degree obtained is about 20nm.
It in one example, further include surfactant according to the composition of the embodiment of the present disclosure.Those skilled in the art
It is appreciated that surfactant common in this field can be used, the disclosure is without limitation.
In one example, the weight percent of surfactant is 0.1%-0.2%, the weight based on main monomer X1
Meter.
In addition, it will be understood by those skilled in the art that solvent common in this field can be used in the solvent in the disclosure,
Such as EL solvent, the disclosure are without limitation.
Fig. 1 shows mutual as expendable material production metal using the composition of at least one embodiment according to the disclosure
The flow chart of method 100 even.Fig. 2A-Fig. 2 L shows the portion of semiconductor device corresponding with the part steps of the method for Fig. 1
Partial cross-section pictorial image.It is described below in conjunction with Fig. 1 and Fig. 2A-Fig. 2 L.
In step S101, substrate 201 is provided.As shown in Figure 2 A, stack of dielectric layers 203 is formed on substrate 201.
In one example, as shown in Figure 2 A, stack of dielectric layers 203 successively includes: the first dielectric layer from top to bottom
2031, the first etching stopping layer 2033, the second dielectric layer 2035 and the second etching stopping layer 2037.
In step S103, as shown in Figure 2 D, the first etching is carried out to stack of dielectric layers 203, extends through electricity to be formed
Dielectric layer stacks 203 through-hole.
In one example, being formed and extending through the through-hole of stack of dielectric layers 203 includes: as shown in Figure 2 B, to be situated between in electricity
Photoresist 205 is coated on the surface of matter layer heap folded 203；As shown in Figure 2 C, photoresist 205 is patterned；With
And as shown in Figure 2 D, the first erosion is carried out to stack of dielectric layers 203 as exposure mask using the photoresist 205 after patterning
It carves；And photoresist 205 is removed after the first etching.
In the example shown by Fig. 2 D, first is etched in stopping at the second etching stopping layer 2037.It shows in figure 2d
First etching does not etch the second etching stopping layer 2037 completely.However, it will be understood by those skilled in the art that the first etching can
To etch away a part of the second etching stopping layer 2037, the disclosure is without limitation.
In step S105, sacrificial material layer 207 is coated on the surface of stack of dielectric layers 203.As shown in Figure 2 E, it sacrifices
Material layer 207 is at least filled up completely through-hole.Sacrificial material layer 207 includes the composition according to disclosure preceding embodiment.
In one example, sacrificial material layer 207 is coated on the surface of stack of dielectric layers 203 including the use of Spun-on carbon
(SOC) technique coats sacrificial material layer.As previously mentioned, compared with chemical vapor deposition (CVD), SOC technique it is cheaper and
It is more preferable to the planarization on surface.
In one example, method 100 further include: before carrying out etch-back to sacrificial material layer 207, to expendable material
Layer 207 carries out heat cure.
As previously mentioned, the additive in composition is used as according to the composition of the embodiment of the present disclosure when carrying out heat cure
Crosslinking agent accelerates the crosslinking of main monomer so that main monomer lower than decomposition temperature at a temperature of crosslink, to prevent
The distillation of main monomer, so that the planarization performance and gap-filling properties of composition are improved.Therefore, comprising according to this public affairs
The planarization performance and gap-filling properties for opening the sacrificial material layer of the composition of embodiment are improved.
In step S107, as shown in Figure 2 F, etch-back is carried out to sacrificial material layer 207, with only in a part of through-hole
Retain expendable material.
In step S109, as shown in figure 2i, the second etching is carried out to stack of dielectric layers 203, to form the first opening.The
One opening is above a part for being sacrificed material filling of through-hole and has the size for being greater than through-hole.
In one example, as shown in figure 2i, second it is etched in stopping at the first etching stopping layer 2033.
In one example, the second etching is carried out to stack of dielectric layers 203, includes: such as Fig. 2 G to form the first opening
It is shown, photoresist 209 is coated in stack of dielectric layers 203；As shown in 2H figure, pattern is carried out to photoresist 209
Change, so that the surface exposure of through-hole and dielectric stack 203 around through-hole；And as shown in 2I figure, utilize patterning
Photoresist 209 afterwards carries out the second etching to stack of dielectric layers 203 as exposure mask, is existed with removing dielectric stack 203
It is not sacrificed the part around the through-hole of material filling.
In step S1011, the expendable material in through-hole is removed, to form the second opening, wherein the second opening is opened with first
Mouth connection.In this step, photoresist 209 is also removed.
In one example, as shown in fig. 2j, the first opening is located in the first dielectric layer 2031, and the second opening position
In the second dielectric layer 2035.For example, the first opening will be used for the via hole of metal interconnection, and the second opening will be used for metal
The groove of interconnection.
In step S1013, as shown in 2K figure, the metal layer 2011 of filling the first opening and the second opening is formed.
In one example, the metal layer for filling the first opening and the second opening is layers of copper, and forms filling first and open
Mouth and the metal layer of the second opening include: that dielectric barrier, barrier metal are sequentially depositing in the first opening and the second opening
Layer and copper layer, then plating forms layers of copper.
In one example, this method 100 further include: as shown in figure 2l, metal layer 2011 is chemically-mechanicapolish polished,
So that the surface of metal layer is flushed with the surface of stack of dielectric layers 203.
Fig. 3 shows the method for utilizing the composition manufacturing semiconductor devices of at least one embodiment according to the disclosure
300 flow chart.Fig. 4 A- Fig. 4 G shows the partial cross section of semiconductor device corresponding with the part steps of method 300 of Fig. 3
Pictorial image.It is described below in conjunction with Fig. 3 and Fig. 4 A- Fig. 4 G.
In step S301, as shown in Figure 4 A, substrate 401 is provided.The pattern with step is formed on substrate 401.
In the example shown by Fig. 4 A, pattern is limited by single layer 403 (such as oxide skin(coating) of substrate).So
And it will be understood by those skilled in the art that pattern can be limited by multiple layers.The disclosure does not limit this.
In step S303, as shown in Figure 4 B, sacrificial material layer 405 is coated on pattern.Sacrificial material layer 405 includes root
According to composition described in the embodiment of the present disclosure.
In one example, sacrificial material layer 405 is coated on pattern to coat including the use of Spun-on carbon (SOC) technique
Sacrificial material layer.As previously mentioned, compared with chemical vapor deposition (CVD), SOC technique it is cheaper and to the planarization on surface more
It is good.
In one example, this method 300 further include: after coating sacrificial material layer 405 on pattern, to sacrifice material
The bed of material 405 carries out heat cure.
As previously mentioned, the additive in composition is used as according to the composition of the embodiment of the present disclosure when carrying out heat cure
Crosslinking agent accelerates the crosslinking of main monomer so that main monomer lower than decomposition temperature at a temperature of crosslink, to prevent
The distillation of main monomer, so that the planarization performance and gap-filling properties of composition are improved.Therefore, comprising according to this public affairs
The planarization performance and gap-filling properties for opening the sacrificial material layer of the composition of embodiment are improved.
In step S305, photoresist is coated in sacrificial material layer 405.
In one example, photoresist is coated in sacrificial material layer 405 further include: as shown in Figure 4 C, sacrificing
Anti-reflection coating 407 is formed in material layer 405, and as shown in Figure 4 D, coats photoresist on anti-reflection coating 405
409。
In step S307, photoresist 409 is patterned.
In step S309, sacrificial material layer 405 is etched using patterned photoresist as exposure mask, it will
Pattern in patterned photoresist is transferred in sacrificial material layer 405.
In one example, if yet forming anti-reflection coating 407 before coating photoresist, pattern is utilized
It includes: as illustrated in figure 4f, using patterned photic anti-that the photoresist of change, which is etched sacrificial material layer as exposure mask,
Erosion agent 409 is etched as exposure mask antagonistic reflex coating 407 and sacrificial material layer 405, with the photoresist that will be patterned into
In pattern be transferred in anti-reflection coating 407 and sacrificial material layer 405.
In one example, this method 300 further include: as shown in Figure 4 G, using patterned photoresist as
After exposure mask is etched sacrificial material layer or anti-reflection coating and sacrificial material layer, patterned photoresist is removed
Agent.
In one example, this method 300 further include: utilize the expendable material with the pattern shifted from photoresist
Layer 405 is etched the pattern on substrate 401 and/or substrate 401 as exposure mask.
In one example, if yet forming anti-reflection coating 407 before coating photoresist, and antireflection
Coating 407 also has the pattern come from photoresist transfer, then using anti-reflection coating 407 and sacrificial material layer 405 as
Exposure mask is etched the pattern on the 401 of substrate 401 and/or substrate.
Fig. 5 shows the method 500 that etch-back is carried out using composition according at least one embodiment of the disclosure
Flow chart.Fig. 6 A- Fig. 6 C shows the partial cross section pictorial image of the semiconductor device of the part steps of the method corresponding to Fig. 5.
It is described below in conjunction with Fig. 5 and Fig. 6 A- Fig. 6 C.
In step S501, substrate 601 is provided.The pattern with opening is formed on substrate 601.
As shown in Figure 6A, the pattern limited by two layers (such as layer 603 and layer 605) is formed on substrate 601.So
And it will be understood by those in the art that the pattern formed on substrate 601 can be limited by single layer or multiple layers, this public affairs
It opens without limitation.
In step S503, sacrificial material layer 605 is coated on pattern.As shown in Figure 6B, 605 blank map of sacrificial material layer
The opening of case.Sacrificial material layer 605 includes according to the foregoing composition in the embodiment of the present disclosure.
In one example, sacrificial material layer 605 is coated on pattern 603 utilize Spun-on carbon (SOC) including the use of coating
Technique coats sacrificial material layer.As previously mentioned, SOC technique is cheaper and to surface compared with chemical vapor deposition (CVD)
Planarization it is more preferable.
This method 500 further includes, and after coating sacrificial material layer 605 on pattern, carries out heat cure to sacrificial material layer.
As previously mentioned, the additive in composition is used as according to the composition of the embodiment of the present disclosure when carrying out heat cure
Crosslinking agent accelerates the crosslinking of main monomer so that main monomer lower than decomposition temperature at a temperature of crosslink, to prevent
The distillation of main monomer, so that the planarization performance and gap-filling properties of composition are improved.Therefore, comprising according to this public affairs
The planarization performance and gap-filling properties for opening the sacrificial material layer of the composition of embodiment are improved.
In step S505, etch-back is carried out to sacrificial material layer 605, so that pattern planarization.As previously described, because group
Closing object has improved planarization performance and gap-filling properties, utilizes the method according to the composition of the embodiment of the present disclosure
It can be realized planarization and the improvement of compactedness.
In at least one embodiment of the disclosure, also disclose foregoing in semiconductor processing as expendable material
Purposes of the composition at least one of following technique: multilayer photoresist technique, etch back process, dual damascene
Via-first technique, the technique and 3D integrated technique for manufacturing FinFET.
The disclosure is contemplated that following items.
Project 9, a kind of method for making metal interconnection characterized by comprising
Substrate is provided, is formed with stack of dielectric layers in the substrate；
First etching is carried out to the stack of dielectric layers, to form the through-hole for extending through the stack of dielectric layers；
Sacrificial material layer is coated on the surface of the stack of dielectric layers, the sacrificial material layer is at least filled up completely institute
Through-hole is stated, wherein the sacrificial material layer includes the composition according to any one of project 1-8；
Etch-back is carried out to the sacrificial material layer, the expendable material in a part to be only remained in the through-hole；
Second etching is carried out to the stack of dielectric layers, to form the first opening, wherein first opening is described
Above a part of through-hole filled by the expendable material and there is the size for being greater than the through-hole；
The expendable material in the through-hole is removed, to form the second opening, wherein second opening is opened with described first
Mouth connection；And
Form the metal layer of filling first opening and second opening.
Project 10, the method according to project 9, which is characterized in that the first etching is carried out to the stack of dielectric layers,
Include: with the through-hole that formation extends through the stack of dielectric layers
Photoresist is coated on the surface of the stack of dielectric layers；
The photoresist is patterned；And
The first etching is carried out to the stack of dielectric layers as exposure mask using the photoresist after patterning.
Project 11, the method according to project 9, which is characterized in that the second etching is carried out to the stack of dielectric layers,
Include: to form the first opening
Photoresist is coated on the surface of the stack of dielectric layers；
The photoresist is patterned, so that the through-hole and the dielectric stack are in the through-hole
A part exposure on the surface of surrounding；And
The second etching is carried out to the stack of dielectric layers as exposure mask using the photoresist after patterning, with removal
Part of the dielectric stack around the through-hole that do not filled by the expendable material.
Project 12, the method according to project 9, which is characterized in that the stack of dielectric layers is successively wrapped from top to bottom
It includes: the first dielectric layer, the first etching stopping layer, the second dielectric layer and the second etching stopping layer, wherein first erosion
It is engraved at second etching stopping layer and stops, and described second is etched in stopping at first etching stopping layer.
Project 13, the method according to project 9, which is characterized in that coated on the surface of the stack of dielectric layers
Sacrificial material layer coats the sacrificial material layer including the use of Spun-on carbon (SOC) technique.
Project 14, the method according to project 9, which is characterized in that further include being etched back to the expendable material
Before quarter, heat cure is carried out to the sacrificial material layer.
Project 15, a kind of method being used for producing the semiconductor devices characterized by comprising
Substrate is provided, is formed with the pattern with step in the substrate；
Sacrificial material layer is coated on the pattern, wherein the sacrificial material layer includes according to any in project 1-8
Composition described in；
Photoresist is coated in the sacrificial material layer；
The photoresist is patterned；And
The sacrificial material layer is etched using patterned photoresist as exposure mask, with the light that will be patterned into
The pattern in resist is caused to be transferred in the sacrificial material layer.
Project 16, the method according to project 15, which is characterized in that further include: utilizing has from the photoresist
The sacrificial material layer of the pattern of agent transfer is lost as pattern of the exposure mask to the substrate and/or the substrate
It carves.
Project 17, the method according to project 16, which is characterized in that coat photoresist in the sacrificial material layer
Agent includes: anti-reflection coating to be formed in the sacrificial material layer, and coat on the anti-reflection coating described photic
Resist.
Project 18, the method according to project 17, which is characterized in that using patterned photoresist as exposure mask
The sacrificial material layer is etched further include: using patterned photoresist as exposure mask to the anti-reflection coating
Be etched with the sacrificial material layer, with the pattern in the photoresist that will be patterned into be transferred to the anti-reflection coating and
In the sacrificial material layer.
Project 19, the method according to project 15, which is characterized in that sacrificial material layer packet is coated on the pattern
It includes and coats the sacrificial material layer using Spun-on carbon (SOC) technique.
Project 20, the method according to project 15, which is characterized in that further include: it is coated in the sacrificial material layer
Before photoresist, heat cure is carried out to the sacrificial material layer.
Project 21, a kind of method for carrying out etch-back characterized by comprising
Substrate is provided, is formed with the pattern with opening in the substrate；
Sacrificial material layer is coated on the pattern, wherein the sacrificial material layer fills the opening, and wherein institute
Stating sacrificial material layer includes the composition according to any one of project 1-8；
Etch-back is carried out to the sacrificial material layer, so that the pattern planarization.
Project 22, the method according to project 21, which is characterized in that coating sacrificial material layer on the pattern includes
The sacrificial material layer is coated using Spun-on carbon (SOC) technique.
Project 23, the method according to project 21, which is characterized in that further include: it is carried out to the sacrificial material layer
Before etch-back, heat cure is carried out to the sacrificial material layer.
Project 24, purposes of the composition at least one of following technique according to any one of project 1-8: more
Layer photoresist technique, etch back process, dual damascene via first process, the technique and 3D for manufacturing FinFET
Integrated technique.
In the word "front", "rear" in specification and claim, "top", "bottom", " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way
Language be in appropriate circumstances it is interchangeable so that the embodiment of the present disclosure described herein, for example, can with it is shown here
Out or operated in those of other description different other orientations of orientation.
As used in this, word " illustrative " means " be used as example, example or explanation ", not as will be by
" model " accurately replicated.It is not necessarily to be interpreted than other implementations in any implementation of this exemplary description
It is preferred or advantageous.Moreover, the disclosure is not by above-mentioned technical field, background technique, summary of the invention or specific embodiment
Given in go out theory that is any stated or being implied limited.
As used in this, word " substantially " means comprising the appearance by the defect, device or the element that design or manufacture
Any small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in actual implementation with perfect or ideal situation
Between difference.
Foregoing description can indicate to be " connected " or " coupled " element together or node or feature.As used herein
, unless explicitly stated otherwise, " connection " means an element/node/feature and another element/node/feature in electricity
Above, it is directly connected (or direct communication) mechanically, in logic or in other ways.Similarly, unless explicitly stated otherwise,
" coupling " mean an element/node/feature can with another element/node/feature in a manner of direct or be indirect in machine
On tool, electrically, in logic or in other ways link to allow to interact, even if the two features may not direct
Connection is also such.That is, " coupling " is intended to encompass the direct connection and connection, including benefit indirectly of element or other feature
With the connection of one or more intermediary elements.
In addition, middle certain term of use can also be described below, and thus not anticipate just to the purpose of reference
Figure limits.For example, unless clearly indicated by the context, be otherwise related to the word " first " of structure or element, " second " and it is other this
Class number word does not imply order or sequence.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or their combination.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering all modes for obtaining object
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembly ", and/or " order " object etc..
It should be appreciated by those skilled in the art that the boundary between aforesaid operations is merely illustrative.Multiple operations
It can be combined into single operation, single operation can be distributed in additional operation, and operating can at least portion in time
Divide and overlappingly executes.Moreover, alternative embodiment may include multiple examples of specific operation, and in other various embodiments
In can change operation order.But others are modified, variations and alternatives are equally possible.Therefore, the specification and drawings
It should be counted as illustrative and not restrictive.
Although being described in detail by some specific embodiments of the example to the disclosure, the skill of this field
Art personnel it should be understood that above example merely to be illustrated, rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out without departing from the scope and spirit of the disclosure to embodiment.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
1. a kind of composition for being used as expendable material in semiconductor processing characterized by comprising
Main monomer, additive and solvent, wherein it includes the organic compound of the aromatic ring with OH unit that the main monomer, which is, and
And the additive is the organic compound for including OH unit and acrylic.
2. composition according to claim 1, which is characterized in that the main monomer is the organic compound with following formula
Object:
3. composition according to claim 1, which is characterized in that the additive is the organic compound with following formula
Object:
4. composition according to claim 1, which is characterized in that the weight percent of the additive is 15%-25%,
Poidometer based on the main monomer.
5. composition according to claim 1, which is characterized in that further include surfactant.
6. composition according to claim 5, which is characterized in that the weight percent of the surfactant is 0.1%-
0.2%, the poidometer based on the main monomer.
7. composition according to claim 1, which is characterized in that the composition can be come using Spun-on carbon (SOC) technique
Coating.
8. composition according to claim 1, which is characterized in that the composition can utilize heat to be solidified.
9. a kind of method for making metal interconnection characterized by comprising
Substrate is provided, is formed with stack of dielectric layers in the substrate；
First etching is carried out to the stack of dielectric layers, to form the through-hole for extending through the stack of dielectric layers；
Sacrificial material layer is coated on the surface of the stack of dielectric layers, the sacrificial material layer is at least filled up completely described logical
Hole, wherein the sacrificial material layer includes composition according to claim 1 to 8；
Etch-back is carried out to the sacrificial material layer, the expendable material in a part to be only remained in the through-hole；
Second etching is carried out to the stack of dielectric layers, to form the first opening, wherein first opening is in the through-hole
Filled by the expendable material a part top and have greater than the through-hole size；
The expendable material in the through-hole is removed, to form the second opening, wherein second opening connects with first opening
It is logical；And
Form the metal layer of filling first opening and second opening.
10. according to the method described in claim 9, it is characterized in that, the first etching is carried out to the stack of dielectric layers, with shape
Include: at the through-hole for extending through the stack of dielectric layers
Photoresist is coated on the surface of the stack of dielectric layers；
The photoresist is patterned；And
The first etching is carried out to the stack of dielectric layers as exposure mask using the photoresist after patterning.
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| CN110317127A (en) * | 2019-07-09 | 2019-10-11 | 德淮半导体有限公司 | For forming the mixture of sacrificial material layer and the manufacturing method of semiconductor device in the manufacturing process of semiconductor device |
| US11916013B2 (en) | 2021-09-02 | 2024-02-27 | International Business Machines Corporation | Via interconnects including super vias |
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| US20060264033A1 (en) * | 2005-04-11 | 2006-11-23 | Olmen Jan V | Dual damascene patterning method |
| CN104752324A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
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| TW200525652A (en) * | 2004-01-30 | 2005-08-01 | Taiwan Semiconductor Mfg | Method for forming dual damascene interconnect structure |
| US20060264033A1 (en) * | 2005-04-11 | 2006-11-23 | Olmen Jan V | Dual damascene patterning method |
| CN104752324A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110317127A (en) * | 2019-07-09 | 2019-10-11 | 德淮半导体有限公司 | For forming the mixture of sacrificial material layer and the manufacturing method of semiconductor device in the manufacturing process of semiconductor device |
| US11916013B2 (en) | 2021-09-02 | 2024-02-27 | International Business Machines Corporation | Via interconnects including super vias |
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