CN109918863B - Floating geomagnetic control memristor simulator based on transconductance operational amplifier - Google Patents
Floating geomagnetic control memristor simulator based on transconductance operational amplifier Download PDFInfo
- Publication number
- CN109918863B CN109918863B CN201910370016.4A CN201910370016A CN109918863B CN 109918863 B CN109918863 B CN 109918863B CN 201910370016 A CN201910370016 A CN 201910370016A CN 109918863 B CN109918863 B CN 109918863B
- Authority
- CN
- China
- Prior art keywords
- operational amplifier
- resistance
- resistor
- pin
- transconductance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 claims description 6
- FGRBYDKOBBBPOI-UHFFFAOYSA-N 10,10-dioxo-2-[4-(N-phenylanilino)phenyl]thioxanthen-9-one Chemical compound O=C1c2ccccc2S(=O)(=O)c2ccc(cc12)-c1ccc(cc1)N(c1ccccc1)c1ccccc1 FGRBYDKOBBBPOI-UHFFFAOYSA-N 0.000 claims description 3
- 238000013461 design Methods 0.000 abstract description 3
- 238000013528 artificial neural network Methods 0.000 abstract description 2
- 230000000739 chaotic effect Effects 0.000 abstract description 2
- 230000010355 oscillation Effects 0.000 abstract description 2
- 238000012360 testing method Methods 0.000 abstract description 2
- 238000004088 simulation Methods 0.000 description 9
- 230000004907 flux Effects 0.000 description 4
- 238000011160 research Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 208000033830 Hot Flashes Diseases 0.000 description 1
- 206010060800 Hot flush Diseases 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 210000005036 nerve Anatomy 0.000 description 1
- 230000000946 synaptic effect Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
The invention discloses a floating geomagnetic memristor simulator based on a transconductance operational amplifier, which comprises a port a, a port b and a transconductance operational amplifier U 1 Transconductance operational amplifier U 2 Current feedback operational amplifier U 3 Voltage feedback operational amplifier U 4 Capacitance C 1 Resistance R 1 Resistance R 2 Resistance R 3 Resistance R 4 Resistance R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 And resistance R 11 Transconductance operational amplifier U 1 Model LM13600, said transconductance operational amplifier U 2 Model number LM13600. The electrical characteristics of the ports a and b of the floating geomagnetic memristor simulator are equivalent to those of the magnetic memristor, one end of the floating geomagnetic memristor is not required to be grounded, and the floating geomagnetic memristor simulator can be widely applied to the design and test of memristor circuits (memristor chaotic circuits, memristor oscillation circuits, memristor neural network circuits and the like).
Description
Technical Field
The invention relates to the field of novel circuit element simulator construction, in particular to a magnetic control memristor simulator based on a transconductance operational amplifier.
Background
In 1971, cai Shaotang of the university of california berkeley division taught that, starting from the theoretical completeness of the circuit, a fourth passive basic circuit element, which characterizes the relationship between charge and magnetic flux, was predicted to exist in addition to resistance, capacitance and inductance, and was named memristor. The 2008 Hewlett-packard published research results in the Nature journal, announced that physical implementation of a two-terminal device with memristor characteristics. Breakthroughs in the hewlett-packard laboratory have raised significant attention in academia and industry, raising the hot flashes of research on memristors.
Memristors are nonlinear resistors whose resistance value can change with the history of an input current or voltage, i.e., the amount of charge or magnetic flux that can flow through can be memorized by the change in resistance value. The research of memristors relates to the fields of microelectronics, condensed state physics, materialics, circuits and systems, computers, neurobiology and other multidisciplinary fields, and belongs to the research of emerging interdisciplines. The memristor has the characteristics of simple structure, easy integration, high speed, low power consumption, compatibility with a CMOS process and the like, can meet the requirements of a next generation of high-density information storage and high-performance computer on a general memory, and can realize the functions of nonvolatile state logic operation and brain-like nerve state operation.
Memristive simulators are commonly used to simulate the electrical characteristics of memristive ports and are applied to circuit designs. Common memristors are: boundary migration model, synaptic activity-dependent plasticity model, pershin model, biolek model, secondary nonlinear active magnetic control model, tertiary nonlinear magnetic control model, etc. The main disadvantages of these circuit simulation models are: one end of the other end is required to be grounded; some are not two-port models; some two-port voltages cannot exceed the power supply voltage of the active devices in the model; there are many components required and the structure is complicated.
Disclosure of Invention
The invention aims to solve the technical problem of providing a floating geomagnetic control memristor simulator based on a transconductance operational amplifier, and solves the problem that the existing magnetic control memristor simulator needs one end to be grounded.
The technical scheme for solving the technical problems is as follows: a floating geomagnetic memristor simulator based on a transconductance operational amplifier comprises a port a, a port b and a transconductance operational amplifier U 1 Transconductance operational amplifier U 2 Current feedback operational amplifier U 3 Voltage feedback operational amplifier U 4 Capacitance C 1 Resistance R 1 Resistance R 2 Resistance R 3 Resistance R 4 Resistance R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 And resistance R 11 The transconductance operational amplifier U 1 Model LM13600, said transconductance operational amplifier U 2 Model LM13600, said transconductance operational amplifier U 1 The 5 th pin and the 7 th pin are connected with the port a, and the transconductance operational amplifier U 1 8 th leg of (2) and resistor R 5 One end of (1) resistor R 6 Is connected to one end of resistor R 5 The other end of (2) is connected with a power supply VEE, a resistor R 6 And transconductance operational amplifier U 1 Is connected to the 4 th pin of the transconductance operational amplifier U 1 4 th pin of (a) and transconductance operational amplifier U 2 Is connected to the 14 th pin of the transconductance operational amplifier U 1 3 rd leg and transconductance operational amplifier U 2 Is connected to the 13 th pin of the resistor R 1 Respectively and transconductance operational amplifier U 1 4 th pin of transconductance operational amplifier U 2 Is connected to the 13 th pin of the transconductance operational amplifier U 2 13 th leg of (d) and resistor R 4 Is connected to one end of the resistor R 4 And transconductance operational amplifier U 2 Is connected to the 9 th pin of the transconductance operational amplifier U 2 9 th leg of (d) and resistor R 3 Is connected to one end of the resistor R 3 The other end of the transconductance operational amplifier U is connected with a power supply VEE 1 1 st leg of transconductance operational amplifier U 2 And the 16 th leg of (C) is connected with resistor R 2 Is connected to one end of the resistor R 2 And current feedback operational amplifier U 3 Is connected to the 6 th pin of the current feedback operational amplifier U 3 5 th leg of (C) and capacitor C 1 Is connected to one end of the capacitor C 1 Is grounded at the other end of the circuit, and a current feedback operational amplifier U 3 2 nd leg of (2) and resistor R 11 Is connected to one end of the resistor R 11 Is grounded at the other end of the circuit, and a current feedback operational amplifier U 3 3 rd leg of (d) and voltage feedback op amp U 4 Is connected to the 6 th pin of the voltage feedback operational amplifier U 4 6 th leg of (d) and resistor R 10 Is connected to one end of the resistor R 10 The other end of (a) and a voltage feedback operational amplifier U 4 Is connected to the 2 nd pin of the voltage feedback operational amplifier U 4 2 nd leg of (2) and resistor R 8 Is connected to one end of the resistor R 8 The other end of the voltage feedback operational amplifier U is connected with the port b 4 3 rd leg, resistor R 9 One end of (a) is connected with the resistor R 7 Is connected to one end of the resistor R 9 The other end of the resistor R is grounded 7 The other end of the transconductance operational amplifier U is connected with the port a 1 Is connected to the 6 th pin of the power supply VEE, the transconductance operational amplifier U 1 11 th pin of (2) is connected with a power supply VCC, the transconductance operational amplifier U 2 Is connected to the 6 th pin of the power supply VEE, the transconductance operational amplifier U 2 11 th pin of (2) is connected with a power supply VCC, and the current feedback operational amplifier U 3 Is connected to the power supply VCC at the 1 st pin, the current feedback is operatedCalculation amplifier U 3 Is connected to the power supply VEE at the 4 th pin, the voltage feedback operational amplifier U 4 Is connected with a power supply VCC at the 1 st pin of the voltage feedback operational amplifier U 4 Is connected to the power supply VEE at pin 4.
On the basis of the technical scheme, the invention can be improved as follows.
Further, the current feedback operational amplifier U 3 The model number of the integrated circuit is AD844, and the integrated circuit has the beneficial effect that the integrated drift phenomenon can be well avoided when the integrated circuit is integrated by taking the AD844 as a core.
Further, the voltage feedback operational amplifier U 4 The model number of the amplifier is OP07, and the beneficial effect of the amplifier is that the OP07 is a high-precision operational amplifier, and the amplifier has the advantages of small offset voltage, high precision and the like.
Further, the power supply VCC is a +5V end of a positive and negative 5V dual power supply.
Further, the power supply VEE is a negative 5V end of a positive and negative 5V dual power supply.
The beneficial effects of the invention are as follows: in the invention, the electrical characteristics of the ports a and b of the floating geomagnetic memristor simulator are equivalent to the port characteristics of the magnetic memristor, one end of the floating geomagnetic memristor is not required to be grounded, and the floating geomagnetic memristor simulator can be widely applied to the design and test of memristor circuits (memristor chaotic circuits, memristor oscillation circuits, memristor neural network circuits and the like).
Drawings
FIG. 1 is a schematic diagram of the present invention
FIG. 2 is a graph of a simulation of the volt-ampere relationship between the voltage value of a sinusoidal voltage source u (t) with a frequency of 2Hz and a port current i (t) in an embodiment of the present invention
FIG. 3 is a graph of a simulation of the volt-ampere relationship between the voltage value of a sinusoidal voltage source u (t) at a frequency of 10Hz and a port current i (t) in an embodiment of the present invention
FIG. 4 is a graph of a simulation of the volt-ampere relationship between the u (t) voltage value and the port current i (t) of a sinusoidal voltage source having a frequency of 50Hz in an embodiment of the present invention
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
As shown in FIG. 1, a floating geomagnetic memristor simulator based on a transconductance operational amplifier comprises a port a, a port b and a transconductance operational amplifier U 1 Transconductance operational amplifier U 2 Current feedback operational amplifier U 3 Voltage feedback operational amplifier U 4 Capacitance C 1 Resistance R 1 Resistance R 2 Resistance R 3 Resistance R 4 Resistance R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 And resistance R 11 Transconductance operational amplifier U 1 Model LM13600, transconductance operational amplifier U 2 Model LM13600, transconductance operational amplifier U 1 The 5 th pin and the 7 th pin of the circuit are connected with the port a, and the transconductance operational amplifier U 1 8 th leg of (2) and resistor R 5 One end of (1) resistor R 6 Is connected to one end of resistor R 5 The other end of (2) is connected with a power supply VEE, a resistor R 6 And transconductance operational amplifier U 1 Is connected to the 4 th pin of the transconductance operational amplifier U 1 4 th pin of (a) and transconductance operational amplifier U 2 Is connected to the 14 th pin of the transconductance operational amplifier U 1 3 rd leg and transconductance operational amplifier U 2 Is connected to the 13 th pin of the resistor R 1 Respectively and transconductance operational amplifier U 1 4 th pin of transconductance operational amplifier U 2 Is connected to the 13 th pin of the transconductance operational amplifier U 2 13 th leg of (d) and resistor R 4 Is connected to one end of resistor R 4 And transconductance operational amplifier U 2 Is connected to the 9 th pin of the transconductance operational amplifier U 2 9 th leg of (d) and resistor R 3 Is connected to one end of resistor R 3 The other end of the output signal is connected with a power supply VEE, and a transconductance operational amplifier U 1 1 st leg of transconductance operational amplifier U 2 And the 16 th leg of (C) is connected with resistor R 2 Is connected to one end of resistor R 2 And current feedback operational amplifier U 3 Is connected to the 6 th pin of the current feedback operational amplifier U 3 5 th leg of (C) and capacitor C 1 Is connected to one end of capacitor C 1 Is grounded at the other end of the circuit, and a current feedback operational amplifier U 3 2 nd leg of (2) and resistor R 11 Is connected to one end of resistor R 11 Is grounded at the other end of the circuit, and a current feedback operational amplifier U 3 3 rd leg of (d) and voltage feedback op amp U 4 Is connected to the 6 th pin of the voltage feedback operational amplifier U 4 6 th leg of (d) and resistor R 10 Is connected to one end of resistor R 10 The other end of (a) and a voltage feedback operational amplifier U 4 Is connected to the 2 nd pin of the voltage feedback operational amplifier U 4 2 nd leg of (2) and resistor R 8 Is connected to one end of resistor R 8 The other end of the voltage feedback operational amplifier U is connected with the port b 4 3 rd leg, resistor R 9 One end of (a) is connected with the resistor R 7 Is connected to one end of resistor R 9 Is grounded at the other end of the resistor R 7 The other end of (a) is connected with the port a, and the transconductance operational amplifier U 1 Is connected with the power supply VEE at the 6 th pin of the transconductance operational amplifier U 1 11 th pin of (a) is connected with a power supply VCC, and a transconductance operational amplifier U 2 Is connected with the power supply VEE at the 6 th pin of the transconductance operational amplifier U 2 11 th pin of (a) is connected with a power supply VCC, and a current feedback operational amplifier U 3 Is connected with a power supply VCC at the 1 st pin of the circuit, and a current feedback operational amplifier U 3 Is connected with the power supply VEE at the 4 th pin of the voltage feedback operational amplifier U 4 Is connected with a power supply VCC at the 1 st pin of the voltage feedback operational amplifier U 4 Is connected to the power supply VEE at pin 4.
In the embodiment of the invention, a current feedback operational amplifier U 3 Model number AD844.
In the embodiment of the invention, the voltage feedback operational amplifier U 4 Model number OP07.
In the embodiment of the invention, the power supply VCC is a +5V end of a positive and negative 5V dual power supply.
In the embodiment of the invention, the power supply VEE is a negative 5V end of a positive 5V dual power supply.
The working principle of the invention is as follows:
the components in the circuit shown in fig. 1 respectively realize floating ground control resistance, differential amplification and voltage integration. The floating ground pressure control resistor consists of a, b and U 1 、U 2 、R 1 、R 2 、R 3 、R 4 、R 5 And R is 6 Etc.; differential amplification by U 4 、R 7 、R 8 、R 9 And R is 10 Etc.; voltage integral is formed by U 3 、R 11 And C 1 And the like.
If the voltage u (t) between the memristive simulator ports a and b and the port current i (t) shown in FIG. 1 adopt the associated reference direction, the volt-ampere relationship describing the characteristics is that
u(t)＝Z X ×i(t)， (1)
Z X Is the equivalent resistance between port a and port b. From the data manual of LM13600, ports a and b
Equivalent resistance between
In the formula g m For transconductance value of transconductance operational amplifier, resistor r=r 4 ＝R 6 . Transconductance value at 25 deg.C
U in the formula D Is LM13600 internal triode (Q in data manual) 1 、Q 2 、Q 3 ) The voltage drop from stage to emitter stage during normal operation (or internal diode D 1 Tube pressure drop) of (c). As can be seen from the formulas (1) and (2), the equivalent voltage u between the circuit ports a and b shown in FIG. 1 c And (5) controlling.
Setting resistor R 7 ＝R 8 Resistance R 9 ＝R 10 The output voltage of the differential amplifying circuit is known from the principles of 'virtual short' and 'virtual break' of the operational amplifier
Time t 0 To t n Current feedback operational amplifier U 3 Output voltage of (2)
From the formulas (4) and (5), the voltage
In the method, in the process of the invention,for from time t 0 To t n The magnetic flux of the voltage u (t) between port a and port b.
The mathematical relationship between the ports a and b of the magnetic memristor simulator shown in FIG. 1 can be obtained by the formulas (1), (2), (3) and (5) as follows
Memristance valueDependent on magnetic flux->Has magnetic flux memory function.
Setting resistor R 1 The resistance value of (2) is 1000 omega, the resistance R 2 The resistance value of (2) is 15kΩ, resistance R 3 The resistance value of (2) is 10kΩ, resistance R 4 The resistance value of (2) is 100kΩ, resistance R 5 The resistance value of (2) is 10kΩ, resistance R 6 The resistance of (2) is 100kΩ. Resistor R 7 ＝R 8 ＝R 9 ＝R 10 =510 kΩ, resistor R 11 =2kΩ, capacitance C 1 The simulation of the circuit can be done in Multisim 13, =10μf. Setting the peak voltage of the sinusoidal voltage source u (t) to be 2V, obtaining the frequency f at 2HzThe simulation results of (2) are shown in FIG. 2, the simulation results of (3) are shown in FIG. 3, and the simulation results of (50) are shown in FIG. 4.
From simulation results, the volt-ampere relationship of the ports a and b of the memristor accords with three essential characteristics of the memristor: 1. the volt-ampere characteristic curve of the magnetic control memristor simulator under the excitation of a sinusoidal voltage source u (t) is a pinch loop; 2. the area of the pinching loop lobe is reduced along with the increase of the sinusoidal voltage source frequency f; 3. the pinch loop contracts to a (near) straight line when the sinusoidal voltage source frequency f tends to infinity.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (5)
1. A floating geomagnetic memristor simulator based on a transconductance operational amplifier is characterized by comprising a port a, a port b and a transconductance operational amplifier U 1 Transconductance operational amplifier U 2 Current feedback operational amplifier U 3 Voltage feedback operational amplifier U 4 Capacitance C 1 Resistance R 1 Resistance R 2 Resistance R 3 Resistance R 4 Resistance R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 And resistance R 11 The transconductance operational amplifier U 1 Model LM13600, said transconductance operational amplifier U 2 Model LM13600, said transconductance operational amplifier U 1 The 5 th pin and the 7 th pin are connected with the port a, and the transconductance operational amplifier U 1 8 th leg of (2) and resistor R 5 One end of (1) resistor R 6 Is connected to one end of resistor R 5 The other end of (2) is connected with a power supply VEE, a resistor R 6 And transconductance operational amplifier U 1 Is connected to the 4 th pin of the transconductance operational amplifier U 1 4 th pin of (a) and transconductance operational amplifier U 2 Is connected to the 14 th pin of the transconductance operational amplifier U 1 3 rd leg and transconductance operational amplifierU 2 Is connected to the 13 th pin of the resistor R 1 Respectively and transconductance operational amplifier U 1 4 th pin of transconductance operational amplifier U 2 Is connected to the 13 th pin of the transconductance operational amplifier U 2 13 th leg of (d) and resistor R 4 Is connected to one end of the resistor R 4 And transconductance operational amplifier U 2 Is connected to the 9 th pin of the transconductance operational amplifier U 2 9 th leg of (d) and resistor R 3 Is connected to one end of the resistor R 3 The other end of the transconductance operational amplifier U is connected with a power supply VEE 1 1 st leg of transconductance operational amplifier U 2 And the 16 th leg of (C) is connected with resistor R 2 Is connected to one end of the resistor R 2 And current feedback operational amplifier U 3 Is connected to the 6 th pin of the current feedback operational amplifier U 3 5 th leg of (C) and capacitor C 1 Is connected to one end of the capacitor C 1 Is grounded at the other end of the circuit, and a current feedback operational amplifier U 3 2 nd leg of (2) and resistor R 11 Is connected to one end of the resistor R 11 Is grounded at the other end of the circuit, and a current feedback operational amplifier U 3 3 rd leg of (d) and voltage feedback op amp U 4 Is connected to the 6 th pin of the voltage feedback operational amplifier U 4 6 th leg of (d) and resistor R 10 Is connected to one end of the resistor R 10 The other end of (a) and a voltage feedback operational amplifier U 4 Is connected to the 2 nd pin of the voltage feedback operational amplifier U 4 2 nd leg of (2) and resistor R 8 Is connected to one end of the resistor R 8 The other end of the voltage feedback operational amplifier U is connected with the port b 4 3 rd leg, resistor R 9 One end of (a) is connected with the resistor R 7 Is connected to one end of the resistor R 9 The other end of the resistor R is grounded 7 The other end of the transconductance operational amplifier U is connected with the port a 1 Is connected to the 6 th pin of the power supply VEE, the transconductance operational amplifier U 1 11 th pin of (2) is connected with a power supply VCC, the transconductance operational amplifier U 2 Is connected to the 6 th pin of the power supply VEE, the transconductance operational amplifier U 2 11 th pin of (2) is connected with a power supply VCC, and the current feedback operational amplifier U 3 Is connected to the power supply VCC at the 1 st pin, the current feedback operational amplifier U 3 Is connected to the power supply VEE at the 4 th pin, the voltage feedback operational amplifier U 4 Is connected with a power supply VCC at the 1 st pin of the voltage feedback operational amplifier U 4 Is connected to the power supply VEE at pin 4.
2. The floating geomagnetic memory resistance simulator of claim 1, wherein the current feedback operational amplifier U 3 Model number AD844.
3. The floating geomagnetic memory resistance simulator of claim 1, wherein the voltage feedback operational amplifier U 4 Model number OP07.
4. The floating geomagnetic memory resistance simulator of claim 1, wherein the power supply VCC is +5v terminal of a plus or minus 5V dual power supply.
5. The floating geomagnetic memory resistance simulator of claim 1, wherein the power supply VEE is a-5V terminal of a positive and negative 5V dual power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910370016.4A CN109918863B (en) | 2019-05-06 | 2019-05-06 | Floating geomagnetic control memristor simulator based on transconductance operational amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910370016.4A CN109918863B (en) | 2019-05-06 | 2019-05-06 | Floating geomagnetic control memristor simulator based on transconductance operational amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109918863A CN109918863A (en) | 2019-06-21 |
| CN109918863B true CN109918863B (en) | 2023-11-14 |
Family
ID=66979085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910370016.4A Active CN109918863B (en) | 2019-05-06 | 2019-05-06 | Floating geomagnetic control memristor simulator based on transconductance operational amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109918863B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078883B (en) * | 2021-02-25 | 2023-06-23 | 广东技术师范大学 | Magnetic flux control type memcapacitor equivalent circuit and control method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9299922B1 (en) * | 2015-06-23 | 2016-03-29 | King Fahd University Of Petroleum And Minerals | Continuous-level memristor emulator |
| CN106202796A (en) * | 2016-07-22 | 2016-12-07 | 湘潭大学 | A kind of general memory device simulator |
| CN107945829A (en) * | 2016-10-13 | 2018-04-20 | 中国矿业大学 | One kind, which is recalled, leads the controllable three ports memristor analog circuit of the adjustable gate pole of value |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103095191B (en) * | 2013-01-29 | 2014-12-10 | 中国矿业大学 | Switch reluctance motor memory sensor model modeling method |
| US9619596B2 (en) * | 2015-06-23 | 2017-04-11 | King Fahd University Of Petroleum And Minerals | Floating memristor emulator |
-
2019
- 2019-05-06 CN CN201910370016.4A patent/CN109918863B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9299922B1 (en) * | 2015-06-23 | 2016-03-29 | King Fahd University Of Petroleum And Minerals | Continuous-level memristor emulator |
| CN106202796A (en) * | 2016-07-22 | 2016-12-07 | 湘潭大学 | A kind of general memory device simulator |
| CN107945829A (en) * | 2016-10-13 | 2018-04-20 | 中国矿业大学 | One kind, which is recalled, leads the controllable three ports memristor analog circuit of the adjustable gate pole of value |
Non-Patent Citations (2)
| Title |
|---|
| 一种浮地磁控忆阻模拟器设计与特性分析;王将;钱辉;包伯成;徐权;陈墨;;电子元件与材料(09);全文 * |
| 分抗在正弦电压源中的功率与电学性质;余波;梁雪松;吴兆耀;;科学技术与工程(13);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109918863A (en) | 2019-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108804840B (en) | Extremely simple floating magnetic control memristor circuit simulation model | |
| CN101660928B (en) | Two-terminal semiconductor sensor device | |
| CN109918863B (en) | Floating geomagnetic control memristor simulator based on transconductance operational amplifier | |
| Biolek et al. | Analog emulator of genuinely floating memcapacitor with piecewise-linear constitutive relation | |
| Alharbi et al. | A novel memristor emulator based only on an exponential amplifier and ccii+ | |
| CN109194321A (en) | One kind floating ground magnetic control memristor simulator | |
| CN108846215B (en) | Extremely simple floating ground load control memristor circuit simulation model | |
| CN110046472B (en) | Secondary nonlinear magnetic control memristor simulator based on current transmitter | |
| Sprott et al. | Elegant circuits: simple chaotic oscillators | |
| CN109840365B (en) | Active memristor simulator | |
| Raj et al. | Dual mode, high frequency and power efficient grounded memristor based on OTA and DVCC | |
| Biolek et al. | Fourth fundamental circuit element: SPICE modeling and simulation | |
| CN113054947B (en) | ReLU type memristor simulator | |
| CN110032830B (en) | Three-time nonlinear magnetic control memristor simulator based on current transmitter | |
| CN110008652B (en) | Three-time nonlinear active magnetic control memristor simulator | |
| CN110765718B (en) | Binary memristor circuit simulator | |
| CN110008651B (en) | Secondary nonlinear active magnetic control memristor simulator | |
| Biolková et al. | Unified approach to synthesis of mutators employing operational transimpedance amplifiers for memristor emulation | |
| Suresha et al. | A floating memristor emulator for analog and digital applications with experimental results | |
| CN206023713U (en) | A kind of single supply op zeroing circuit and amplifying circuit | |
| CN109446647B (en) | Voltage fractional order integral control type memory order element | |
| CN109271742B (en) | Magnetic control memory order element | |
| CN209149304U (en) | A kind of cubic non-linearity magnetic control memristor circuit containing fractional order capacitor | |
| CN107194099B (en) | Memristor equivalent realization circuit based on passive filtering and bridge type rectification | |
| CN203761348U (en) | Memristor-based Schmitt trigger circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |