CN109904172A - Contact structures and display device including the contact structures - Google Patents
Contact structures and display device including the contact structures Download PDFInfo
- Publication number
- CN109904172A CN109904172A CN201810575575.4A CN201810575575A CN109904172A CN 109904172 A CN109904172 A CN 109904172A CN 201810575575 A CN201810575575 A CN 201810575575A CN 109904172 A CN109904172 A CN 109904172A
- Authority
- CN
- China
- Prior art keywords
- layer
- contact
- insulating layer
- contact hole
- lower layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 36
- 239000004020 conductor Substances 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000013461 design Methods 0.000 abstract description 24
- 229910052751 metal Inorganic materials 0.000 abstract description 14
- 239000002184 metal Substances 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 417
- 239000011229 interlayer Substances 0.000 description 42
- 239000010408 film Substances 0.000 description 41
- 239000003990 capacitor Substances 0.000 description 23
- 239000000463 material Substances 0.000 description 20
- 230000000052 comparative effect Effects 0.000 description 15
- 239000011241 protective layer Substances 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 12
- 230000005611 electricity Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 239000010409 thin film Substances 0.000 description 8
- 238000009413 insulation Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000004020 luminiscence type Methods 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 238000005070 sampling Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- -1 for example Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052779 Neodymium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 101000911390 Homo sapiens Coagulation factor VIII Proteins 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- 239000004734 Polyphenylene sulfide Substances 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000000975 dye Substances 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 102000057593 human F8 Human genes 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000012044 organic layer Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920006380 polyphenylene oxide Polymers 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229940047431 recombinate Drugs 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229920006337 unsaturated polyester resin Polymers 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/84—Passivation; Containers; Encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Optics & Photonics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
In contact structures in illustrative embodiments according to the present invention and the display device including the contact structures, by being designed to the size (or area) of contact hole to be greater than contact area and according to the characteristic of lower layer using different structures, pixel can be independently designed with the size of contact hole.Therefore, the size of contact hole increases, so that can be easy to using half-tone mask, and the quantity of mask can be advantageously reduced.In addition, the freedom degree of metal increases in pixel design, allow to design pixel with high resolution model, and increase under shed rate in the condition for not needing electrode nargin.Contact structures include: lower layer；At least the first insulating layer on lower layer, the first insulating layer have predetermined contact hole to expose a part of lower layer；With the upper layer on the first insulating layer to be contacted by contact hole with lower layer, wherein contact hole has the area more relatively large than contact area, and wherein contact area is upper layer and the contact area that lower layer is in contact with each other.
Description
Cross reference to related applications
This application claims the South Korea patent application No.10- submitted on December 11st, 2017 in Korean Intellectual Property Office
The priority of 2017-0169193 is combined the disclosure of the patent application herein by quoting.
Technical field
The present invention relates to a kind of contact structures and including the display device of contact structures, more particularly to one kind is in high-resolution
It can be conducive to the contact structures and display device of pixel design in mode.
Background technique
Currently, with the comprehensive information epoch are entered, the field that the display device of telecommunications information signal is visually presented is quick
Development, and carry out continuing performance of the research to improve various display devices, such as thin thickness, light weight and low-power consumption.
Representative display device may include that liquid crystal display device (LCD), field emission display device (FED), electrowetting are aobvious
Showing device (EWD) and organic light-emitting display device (OLED).
Wherein, the el display device including organic light-emitting display device is self-emission display apparatus, so that
Individually light source is unnecessary, this is different from liquid crystal display device.Therefore, el display device can be made it is thin and
Gently.Further, since the driving of lower voltage, field emission display device are not only advantageous in power consumption, but also realize in color,
It is also advantageous in terms of response speed, visual angle and contrast (CR), therefore is expected to apply in various fields.
El display device is by being set using organic material between two electrodes of referred to as anode and cathode
Luminescent layer configure.When the hole in anode is injected into the electron injection in luminescent layer and in cathode into luminescent layer
When, injected holes and electronics recombinate in luminescent layer and are formed exciton, to shine.
This luminescent layer includes host material and dopant material, so that interacting between two kinds of materials.Base
Matter is used to generate exciton from electrons and holes and gives the energy to dopant.Dopant is dyestuff organic material, and addition is a small amount of
Dopant, energy and convert energy into light to receive from matrix.
In order to increase the size of display device and realize high-resolution, it is necessary to ensure that high aperture.In addition, for repairing grid
The grid redundant pattern of short trouble between the horizontal line and data line/power supply line vertical line of polar curve will lead to problem.
It is only inserted into interlayer insulating film between horizontal line and the cross section of vertical line, so that leading due to shorter distance
Electrostatic breakdown is caused, and can lead to the short circuit between horizontal line and vertical line due to caused by impurity or due to above grid line
Insulation layer state caused by failure.Therefore, it is necessary to the structures within the pixel designed for reparation, to improve yield.Therefore,
In the related art, the location application grid redundant pattern intersected with each other to horizontal line and vertical line.Grid redundant pattern is formed
To occupy the presumptive area above and below grid line, so that it leads to the reduction of pixel split shed rate.Further, since in pixel
Middle increase grid redundant pattern, so being difficult to design pixel with high resolution model.
Summary of the invention
Present inventors noted that it is only inserted into interlayer insulating film between horizontal line and the cross section of vertical line,
So that easily there is short trouble, short trouble is influenced by the distance between wiring, the thickness effect capacitor of interlayer insulating film
Capacity makes it difficult to increase thickness.However, inventors noted that the thickness of gate insulating layer and buffer layer can increase, and with electricity
The capacity of container is unrelated, thus has invented a kind of structure, in this configuration, by by the setting of data line/power supply line to it is related
On the different layer of technology, gate insulating layer and buffer layer are inserted between horizontal line and vertical line, to inhibit short trouble.
That is the setting of the vertical line of data line and/or power supply line with as on the identical layer of undermost light shield layer,
And the horizontal line of grid line is arranged on layer identical with gate electrode, so that electrode or the wiring setting separated from vertical line
On layer identical with source/drain electrodes.Therefore, gate insulating layer and buffer layer may be inserted into vertical line and horizontal line it
Between.In this case, gate insulating layer/buffer layer is unrelated with the capacity of capacitor, so that not using grid redundant pattern
In the case where, by increasing the thickness of gate insulating layer and/or buffer layer, can inhibit in vertical line and horizontal cross section
Short trouble caused by locating.
Therefore, a purpose being realized of the present invention is to provide one kind and can press down without using grid redundant pattern
Make the display device of the short trouble generated between vertical line and horizontal line.
Meanwhile the contact structures of the relevant technologies have the following structure: wherein contact hole is by upper layer and lower layer, for example,
Upper electrode and lower electrode covering.In this case, the size (or area) of contact hole and upper electrode and lower electrode
Be in contact with each other (or connection) contact area it is identical.
In this case, due to the minimum dimension for patterned contact hole, there is limitation in pixel design.
In addition, the overlapping nargin between lower electrode and contact hole and between upper electrode and contact hole
(overlay margin) is necessary, thus the freedom degree of metal reduces in pixel design.That is because upper electrode needs
Contact hole is covered, so that lower electrode is not damaged by the etchant of upper electrode, so the nargin of upper electrode is necessary.
In addition, the nargin of lower electrode is also necessary in order to turn to contact hole pattern without departing from lower electrode.As described above, phase
The contact structures of pass technology need nargin for upper electrode and lower electrode so that pixel design in metal freedom degree
It reduces.
Therefore, inventors have seen that: the nargin for generating contact hole is the size (or area) because of contact hole
It can be not to the size of contact hole when the characteristic in view of lower layer applies different contact hole structures equal to contact area
Pixel is designed under conditions of being limited.Therefore, inventor has invented a kind of contact structures, wherein by by the size of contact hole
(or area) is designed to be greater than contact area and according to the characteristic of lower layer using different structures, can with the size of contact hole without
Close ground design pixel.
That is the size (or area) of contact hole is designed to be greater than contact area, and will according to the characteristic of lower layer
Two existing contact hole combinations, contact portion is formed on the side of metal or upper electrode is formed as to coat
(clad) form surrounds lower electrode.Therefore, pixel can independently be designed with the size of contact hole.As described above, when contact
When the size (or area) in hole is designed to be greater than contact area, it is unnecessary that above-mentioned top, which overlaps the overlapping nargin of nargin and lower part,
, so that pixel can independently be designed with the size of contact hole.
Therefore, another that be realized of present invention purpose is to provide and a kind of can be conducive to pixel in high resolution model and set
The contact structures of meter and display device including contact structures.
The purpose of the present invention is not limited to above-mentioned purpose, and one of ordinary skill in the art are clearly understood that by following description
Others not mentioned purpose above.
According to an aspect of the present invention, a kind of contact structures include: lower layer；At least on the lower layer
One insulating layer, first insulating layer have predetermined contact hole with a part of the exposure lower layer；Be located at described first
Upper layer on insulating layer to be contacted by the contact hole with the lower layer, wherein the contact hole has than contact area
Relatively large area, wherein the contact area is the upper layer and the contact area that the lower layer is in contact with each other.
According to another aspect of the present invention, a kind of contact structures include: at least the first insulating layer on substrate, institute
The first insulating layer is stated with predetermined contact hole；With the lower part for being located at the inside of the contact hole and being sequentially stacked and being in contact with each other
Layer and upper layer, wherein the contact hole has the area more relatively large than contact area, wherein the contact area is on described
The contact area that portion's layer and the lower layer are in contact with each other.
According to a further aspect of the invention, a kind of display device includes above-mentioned contact
According to a further aspect of the invention, a kind of display device includes: on the substrate and in a first direction
Data line；The first insulating layer on the data line；Active layer on first insulating layer；Grid line, institute
Grid line is stated to be located on first insulating layer and in the second direction intersected with the first direction, with the data line
Pixel region is divided together, wherein inserted at least one the second insulation between the grid line and first insulating layer
Layer；Gate electrode positioned at the top of the active layer, inserted with described between the gate electrode and the active layer
Two insulating layers；Third insulating layer on the gate electrode and the grid line；Source on the third insulating layer
Pole electrode and drain electrode；The 4th insulating layer on the source electrode and the drain electrode；Absolutely positioned at the described 4th
The top of edge layer and the light emitting diode in the luminescence unit of the pixel region；And contact hole, the contact hole configuration exist
In at least one insulating layer in first insulating layer to the 4th insulating layer, so that at least one described insulating layer
Above and below component be in contact with each other, wherein the contact hole has the area more relatively large than contact area, wherein described
Contact area is the contact area that the component above and below at least one described insulating layer is in contact with each other.
In one or more embodiments, between the data line and the grid line can be inserted into have described first absolutely
Edge layer and the second insulating layer.
In one or more embodiments, the display device may also include the screening on the lowest level of the substrate
Photosphere, wherein the data line bit is on layer identical with the light shield layer, and the grid line is located at and grid electricity
On extremely identical layer.
In one or more embodiments, the third insulating layer can have than first insulating layer and described by second
The smaller thickness of each of insulating layer.
According to a further aspect of the invention, a kind of display device includes: on the substrate and in a first direction
Data line and power supply line；The first insulating layer on the data line；Active layer on first insulating layer；Grid
Polar curve, the grid line are located on first insulating layer and in the second direction intersected with the first direction, with institute
It states data line and divides pixel region together, wherein inserted with the second insulation between the grid line and first insulating layer
Layer；Gate electrode positioned at the top of the active layer, inserted with described between the gate electrode and the active layer
Two insulating layers；Third insulating layer on the gate electrode and the grid line；Positioned at first insulating layer and described
Interlayer insulating film between third insulating layer；Bridging line on the interlayer insulating film；On the third insulating layer
Source electrode and drain electrode；The 4th insulating layer on the source electrode and the drain electrode；Positioned at described
The top of four insulating layers and the light emitting diode in the luminescence unit of the pixel region；And contact hole, the contact hole are matched
It sets at least one insulating layer in first insulating layer to the 4th insulating layer and the interlayer insulating film, with
So that the component above and below at least one described insulating layer is in contact with each other, wherein the contact hole has than contact area
Relatively large area, wherein what the contact area was in contact with each other for the component above and below at least one described insulating layer
Contact area.
In one or more embodiments, the bridging line be may extend on the direction parallel with the second direction
Adjacent pixel region.
In one or more embodiments, the bridging line extended in adjacent pixel regions can be connected by the contact hole
It is connected to the source electrode of adjacent pixel regions.
In one or more embodiments, the side of the bridging line can be extended vertically along the power supply line, to pass through
The contact hole is connected to the power supply line of lower section.
In one or more embodiments, between the data line and the grid line can be inserted into have described first absolutely
Edge layer and the second insulating layer.
In one or more embodiments, the display device may also include the screening on the lowest level of the substrate
Photosphere, wherein the data line and the power supply line are located on layer identical with the light shield layer, and the grid line is located at
On layer identical with the gate electrode.
In one or more embodiments, each of the third insulating layer and the interlayer insulating film can have ratio
Each smaller thickness of first insulating layer and the second insulating layer.
The other details of embodiment include in the detailed description and the accompanying drawings.
According to the present invention, the vertical line of data line and/or power supply line is arranged identical with as undermost light shield layer
On layer, and the horizontal line of grid line is arranged on layer identical with gate electrode, to can avoid in vertical line and horizontal line
Between the short trouble that generates.Therefore, it can remove the grid redundant pattern in pixel, to improve in high resolution model
Yield improves and has also additionally ensured that aperture opening ratio.
In addition, according to the present invention, being greater than contact area and under by the way that the size (or area) of contact hole to be designed to
The characteristic of portion's layer applies different structures, can independently design pixel with the size of contact hole.Therefore, the size of contact hole increases
Add, so that can be easy to using half-tone mask, and the quantity of mask can be advantageously reduced.In addition, metal in pixel design
Freedom degree increase, make it possible to carry out pixel design with high resolution model, and under conditions of not needing electrode nargin
Increase aperture opening ratio.
Effect of the invention is not limited to content illustrated above, includes more various effects in the application.
Detailed description of the invention
By from detailed description with reference to the accompanying drawing be more clearly understood that above and other of the invention in terms of, feature and
Other advantages, in which:
Fig. 1 is the block diagram of the schematic illustrations el display device of illustrative embodiments according to the present invention；
Fig. 2 is the circuit diagram for the pixel for including according to the present invention in the el display device of illustrative embodiments；
Fig. 3 is the plan view of the schematic illustrations el display device of illustrative embodiments according to the present invention；
Fig. 4 to 6 is the electroluminance display dress of illustrative embodiments according to the present invention shown in schematic illustrations Fig. 3
The diagram for the cross-section structure set；
Fig. 7 A and 7B are the plan view and sectional view as example diagram according to the contact structures of comparative example；
Fig. 8 A and 8B are to illustrate the plan view of the contact structures of illustrative embodiments according to the present invention as example and cut open
Face figure；
Fig. 9 A and 9B are the exemplary plan views of schematic illustrations contact structures of illustrative embodiments according to the present invention
And sectional view；
Figure 10 is the exemplary plan view for illustrating the contact structures according to comparative example；
Figure 11 A and 11B are the another exemplary of schematic illustrations contact structures of illustrative embodiments according to the present invention
Plan view and sectional view；
Figure 12 is another exemplary plan view for illustrating the contact structures according to comparative example；
Figure 13 A and 13B are the another exemplary of schematic illustrations contact structures of illustrative embodiments according to the present invention
Plan view and sectional view；
Figure 14 is the another exemplary plan view for illustrating the contact structures according to comparative example；And
Figure 15 A and 15B are the another exemplary of schematic illustrations contact structures of illustrative embodiments according to the present invention
Plan view and sectional view.
Specific embodiment
The advantages and features of the present invention and realize the method for these advantages and feature by reference to it is following together with attached drawing it is detailed
The illustrative embodiments carefully described will be apparent from.However, the present invention is not limited to illustrative embodiments disclosed herein, and
It is to realize in a variety of manners.These illustrative embodiments are provided, by way of example only so as to the common skill of fields
Art personnel can fully understand the disclosure and the scope of the present invention.Therefore, the present invention will be wanted only by appended right
The range of book is asked to limit.
Shape, size, ratio, the angle, number being shown in the accompanying drawings to describe exemplary embodiments of the present invention
Amount etc. is only example, and the present invention is not limited thereto.In addition, can omit in the description below the present invention to known related skill
Art explains in detail, to avoid unnecessarily making subject of the present invention smudgy.Such as " comprising " as used herein, " tool
Have " and the term of "comprising" etc be generally intended to allow to add other component, unless these terms make together with term " only "
With.
Even if not clearly stating, element is still interpreted comprising common error range.
When using such as " ... on ", " in ... top ", " in ... lower section " and " ... after " etc art
When language describes the positional relationship between two parts, one or more parts can be set between the two parts, unless these arts
Language is used together with term " immediately " or " direct ".
When an element or layer are arranged in other element or layer "upper", refer to that another layer or another element can be directly arranged
In other element, or Part III can be inserted between.
Although describing various parts using term " first ", " second " etc., these components be should not be limited by these terms.This
A little terms are only used for distinguishing a component and other component.Therefore, in the technical concept of the present invention, cited below
One component can be second component.
Similar reference marker typicallys represent similar element in entire application.
The size and thickness of each component shown in figure are depicted for ease of description, and the present invention is not limited to what is shown
The size and thickness of component.
The feature of each embodiment of the present invention partially or entirely can be combined or be combined each other, and can be with affiliated neck
The various technical approach that field technique personnel understand are interlocked and are operated, and these embodiments can independently or be relative to each other
Implement on connection ground.
Hereinafter, each illustrative embodiments of the invention be will be described in detail with reference to the accompanying drawings.
Fig. 1 is the block diagram of the schematic illustrations el display device of illustrative embodiments according to the present invention.
Referring to Fig.1, the el display device 100 of illustrative embodiments may include display panel according to the present invention
110, data-driven integrated circuit (IC) 130, grid-driving integrated circuit 150, image processing unit 170 and sequence controller
180。
Display panel 110 may include multiple sub-pixels 160.Multiple sub-pixels 160 be arranged in the matrix form line direction and
On column direction.For example, as shown in fig. 1, multiple sub-pixels 160 may be provided in m row and n column.Hereinafter, for the ease of retouching
It states, among multiple sub-pixels 160, one group of sub-pixel 160 being arranged in the row direction is defined as row sub-pixel, is arranged in column side
One group of upward sub-pixel 160 is defined as column sub-pixel.
Multiple sub-pixels 160 can realize the light of specific color respectively.For example, multiple sub-pixels 160 can be by realization red light
Red sub-pixel, realize green light green sub-pixels and realize blue light blue subpixels constitute.In this case
One group of red sub-pixel, green sub-pixels and blue subpixels can be described as a pixel.
Multiple sub-pixels 160 of display panel 110 can be connected to gate lines G L1 to GLm and data line DL1 to DLn.Example
Such as, the first row sub-pixel is connected to first grid polar curve GL1, and first row sub-pixel is connected to the first data line DL1.In addition, second
Second can be respectively connected to m gate lines G L2 to GLm to m row sub-pixel.In addition, the second to the n-th column sub-pixel can be distinguished
It is connected to the second to the n-th data line DL2 to DLn.Multiple sub-pixels 160 can be configured to based on the transmission from gate lines G L1 to GLm
Grid voltage and the data voltage transmitted from data line DL1 to DLn are operated.
The exportable data enable signal DE of image processing unit 170 and the data-signal (image data) provided from outside
DATA.Other than data enable signal DE, the also exportable vertical synchronizing signal of image processing unit 170, horizontal synchronizing signal
One or more of with clock signal.
Sequence controller 180 can be provided that from image processing unit 170 include vertical synchronizing signal, horizontal synchronization letter
Number, the various clock signals and data-signal DATA of data enable signal DE and clock signal.Sequence controller 180 is from image
Processing unit 170 receives data-signal DATA, that is, data-signal is converted to that be suitable for can be in data by input image data
Processed data signal format in drive integrated circult 130, with outputting data signals DATA, that is, output image data.This
Outside, in order to control data-driven integrated circuit 130 and grid-driving integrated circuit 150, sequence controller 180 receives such as vertical
The clock signal of synchronization signal, horizontal synchronizing signal, data enable signal (DE) and clock signal etc, to generate various controls
Signal such as data controlling signal DCS or grid control signal GCS simultaneously export control signal to data-driven integrated circuit 130
With grid-driving integrated circuit 150.
For example, in order to control grid-driving integrated circuit 150, the output of sequence controller 180 includes grid initial pulse
The various grid control signal GCS of GSP, gate shift clock GSC and grid output enable signal GOE.
Here, the control of grid initial pulse constitutes the behaviour of one or more grid circuits of grid-driving integrated circuit 150
Make starting timing.Gate shift clock is jointly to be input to one or more grid circuits and control scanning signal (grid
Pulse) displacement timing clock signal.Grid exports the timing information of the specified one or more grid circuits of enable signal.
In addition, in order to control data-driven integrated circuit 130, the output of sequence controller 180 includes source electrode initial pulse
The various data controlling signal DCS of SSP, source electrode sampling clock SSC and source output enable signal SOE.
Here, the control of source electrode initial pulse constitutes the number of one or more data circuit of data-driven integrated circuit 130
Timing is originated according to sampling.Source electrode sampling clock is the clock signal of the sampling time sequence of the data in each data circuit of control.Source
Pole exports the output timing of enable signal control data-driven integrated circuit 130.
Grid-driving integrated circuit 150 is successively provided to gate lines G L1 to GLm according to the control of sequence controller 180 and is led
It is powered and presses the scanning signal of (on-voltage) or blanking voltage (off-voltage), successively to drive gate lines G L1 to GLm.
According to driving method, grid-driving integrated circuit 150 can be only located at the side of display panel 110, or if need
The two sides of display panel 110 can be located at if wanting.
Grid-driving integrated circuit 150 can be connected by chip (COG) method on tape automated bonding (TAB) method or glass
To the landing pad of display panel 110.Grid-driving integrated circuit 150 can also be realized with panel inner grid (CIP) type, with straight
Connecing setting can be integrated in display panel 110 in display panel 110, or if necessary.
Grid-driving integrated circuit 150 may include shift register or level shifter.
When the conducting of specific grid line, data-driven integrated circuit 130 will be from the received output image of sequence controller 180
Data DATA is converted to analog data voltage, the analog data voltage after conversion is provided to data line DL1 to DLn, thus
Driving data line DL1 to DLn.
Data-driven integrated circuit 130 is connected to display panel by chip method on tape automated bonding method or glass
110 landing pad can be set up directly on display panel 110.If necessary, data-driven integrated circuit 130 can
It is integrated in display panel 110.
Data-driven integrated circuit 130 can be realized in a manner of chip on film (COF).In this case, data-driven
One end of integrated circuit 130 is bonded at least one source electrode printed circuit board, and the other end is bonded to display panel 110.
Data-driven integrated circuit 130 may include logic unit, digital analog converter (DAC) and output state, patrol
Collecting unit includes various circuits, such as level shifter or latch units.
The detailed construction of pixel 160 will be described referring to Fig. 2 and 3.
Fig. 2 is the circuit diagram for the pixel for including according to the present invention in the el display device of illustrative embodiments.
Hereinafter, for ease of description, by description ought the el display devices of illustrative embodiments according to the present invention be 2T (brilliant
Body pipe) 1C (capacitor) pixel circuit when structurally and operationally, however, the present invention is not limited thereto.
Referring to Fig. 2, in the el display device 100 of illustrative embodiments according to the present invention, a pixel can
Including switching transistor ST, driving transistor DT, compensation circuit (not shown) and light emitting diode LE.
Light emitting diode LE can be operated according to the driving current formed by driving transistor DT to shine.
Switching transistor ST may be in response to the grid signal provided by grid line 117 and execute switch operation, so that passing through
The data-signal that data line 116 provides is stored in capacitor C as data voltage.
The data voltage that driving transistor DT may be in response to be stored in capacitor C is operated, in high potential power
Flow constant driving current between line VDD and low potential power source line VSS.
Here, compensation circuit be for compensate driving transistor DT threshold voltage circuit and including one or more
Thin film transistor (TFT) and capacitor.The construction of compensation circuit can change according to compensation method.
As described above, in the el display device 100 of illustrative embodiments according to the present invention, a pixel by
2T1C structure is constituted, and 2T1C structure includes switching transistor ST, driving transistor DT, capacitor C and light emitting diode LE.So
And when adding compensation circuit, pixel can in various ways, such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C
Or 7T2C configuration.
Fig. 3 is the plan view of the schematic illustrations el display device of illustrative embodiments according to the present invention.Fig. 4
To 6 be the el display device of illustrative embodiments according to the present invention shown in schematic illustrations Fig. 3 section knot
The diagram of structure.
In this case, Fig. 3 diagrammatically illustrates the electroluminance display dress of illustrative embodiments according to the present invention
Set the planar structure of two adjacent pixels in 100.For ease of description, Fig. 3 as example illustrate a pixel configuration at
With the 2T1C structure for including switching transistor, driving transistor, capacitor and light emitting diode.However, as described above, when adding
When adding compensation circuit, a pixel can in various ways, for example 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C or 7T2C match
It sets.
Fig. 4 to 6 diagrammatically illustrates shown in Fig. 3 the electroluminance display of illustrative embodiments according to the present invention
A part of the section of line I-I ', II-II ', III-III ' and IV-IV ' interception in device 100.Wherein, Fig. 4 is as example
Illustrate a part of the circuit unit including driving transistor and capacitor, one of luminescence unit including light emitting diode
Point and grid line 116 and data line 117 cross section a part.Fig. 5 illustrates one of circuit unit as example
Point, wherein the first gate electrode 121a of driving transistor and the second drain electrode 123b of switching transistor are attached.Fig. 6
A part of circuit unit is illustrated as example, wherein data line 116 and the second source electrode 122b of switching transistor into
Row connection.
In this case, Fig. 3 illustrates the contact structures application of illustrative embodiments according to the present invention as example
In a part (see Figures 5 and 6) of the el display device 100 of illustrative embodiments according to the present invention, but the present invention is not
It is limited to this.Contact structures of the invention are described below.
Referring to Fig. 3 to 6, in the el display device 100 of illustrative embodiments according to the present invention, grid line
(or scan line) 117, data line 116 and power supply line (or power voltage line) 119 intersect on substrate 110 to divide pixel region
Domain.In addition, sensing control line or reference line can further be arranged.
Data line 116 and power supply line 119 are set in a first direction on substrate 110.In addition, the setting of grid line 117 exists
In the second direction intersected with first direction, to divide pixel region together with data line 116 and power supply line 119.In this feelings
In shape, for ease of description, a pixel region can be divided into the wherein luminescence unit of lumination of light emitting diode and by multiple
Driving circuit is constituted to provide the circuit unit of driving current to light emitting diode.
Power supply line 119, however, the present invention is not limited thereto can be set for one or more pixel regions.
Together with data line 116 and power supply line 119, reference line can be arranged in and data line 116 and electricity in a first direction
On the identical layer of source line 119.
Multiple pixel regions are by red subpixel areas, green subpixel areas, blue subpixel areas and the sub- picture of white
Plain region is constituted, to form unit pixel.In Fig. 3, the arbitrary sub-pixel of two of them, but this hair are illustrated only as example
It is bright without being limited thereto.Red subpixel areas, green subpixel areas, blue subpixel areas and white sub-pixels region it is each
A multiple pixel-driving circuits including light emitting diode and independent driving light emitting diode.Pixel-driving circuit may include switch
Transistor, driving transistor, capacitor and sensing transistor.
Power supply line 119, however, the present invention is not limited thereto can be set for one or more pixel regions.
Together with data line 116 and power supply line 119, reference line can be arranged in and data line 116 and electricity in a first direction
On the identical layer of source line 119.
When scanning pulse is provided to grid line 117, switching transistor conducting will be provided to the data of data line 116
Signal is provided to capacitor and drives the first gate electrode 121a of transistor.Switching transistor includes being connected to grid line 117
Second grid electrode 121b, be connected to by the 7th contact hole 140g data line 116 the second source electrode 122b, by the
Six contact hole 140f are connected to the second drain electrode 123b and the second active layer 124b of first gate electrode 121a.
Driving transistor according to the electric current that is provided from power supply line 119 of driving voltage control being filled in the capacitor, with to
Light emitting diode provides the electric current proportional to driving voltage, thus makes lumination of light emitting diode.Driving transistor includes passing through
6th contact hole 140f is connected to the first gate electrode 121a of the second drain electrode 123b, by the 8th contact hole 140h connection
The first drain electrode electricity of light emitting diode is connected to the first source electrode 122a of power supply line 119, by third contact hole 140c
Pole 123a and the first active layer 124a.
Power supply line 119 can be connected to the first source electrode 122a in adjacent pixel regions via bridging line 119a.Bridge joint
Line 119a may extend to adjacent pixel region on the direction parallel with second direction.As described above, in adjacent pixel regions
The bridging line 119a of middle extension can be connected to the first source electrode 122a of adjacent pixel regions by the 9th contact hole 140i.
A lateral edge power supply line 119 of bridging line 119a extends vertically, to be connected to lower section by the 8th contact hole 140h
Power supply line 119.
Thin film transistor (TFT) shown in Fig. 4 to 6 is driving transistor and switching transistor, for example, top-grate structure thin film is brilliant
Body pipe, specifically, first gate electrode 121a and second grid electrode 121b setting has in the first active layer 124a and second
Co-planar thin film transistor above active layer 124b.However, the invention is not limited thereto, can also be arranged using gate electrode in active layer
The bottom grating structure thin film transistor (TFT) of lower section.
Switching transistor and drive the first gate electrode 121a and second grid electrode 121b of transistor can be respectively with the
One active layer 124a and the second active layer 124b is overlapping, and between first gate electrode 121a and the first active layer 124a with
And between second grid electrode 121b and the second active layer 124b there is gate insulating layer 115b, gate insulating layer 115b to have
Substantially with corresponding first gate electrode 121a and the identical shape of second grid electrode 121b.
Specifically, the first active layer 124a and the second active layer 124b may be provided on substrate 110.
In this case, light shield layer 125 may be provided at the lower section of the first active layer 124a, and buffer layer 115a can be set
It sets between the first active layer 124a and light shield layer 125.
Light shield layer 125 can inhibit the first active layer 124a to be influenced by the light of external or surrounding light emitting diode, shading
Layer 125 may be provided on the lowest level of substrate 110.
Layer identical with light shield layer 125 can be arranged in data line 116 and power supply line 119 of the invention in a first direction
On.That is data line 116 and power supply line 119 of the invention is arranged in together on the lowest level of substrate with light shield layer 125.Such as
This, the vertical line of data line 116 and power supply line 119 is arranged on the layer different from the relevant technologies, so that interlayer insulating film 115c
Other insulating layers in addition, for example, buffer layer 115a and gate insulating layer 115b are inserted in data line 116 and power supply line 119
Between vertical line and the horizontal line of grid line 117, to avoid short trouble.
Buffer layer 115a may be provided on substrate 110, to cover light shield layer 125, data line 116 and power supply line 119.
First active layer 124a and the second active layer 124b be formed as respectively with the first grid on gate insulating layer 115b
Electrode 121a and second grid electrode 121b is overlapping, so that can be between the first source electrode 122a and the first drain electrode 123a
And channel is formed between the second source electrode 122b and the second drain electrode 123b.
Gate insulating layer 115b can be by the single layer of the silicon nitride SiNx or Si oxide SiOx of inorganic material or inorganic
The multilayer of the silicon nitride SiNx or Si oxide SiOx of material are formed.
Fig. 4 to 6 illustrates gate insulating layer 115b as example and is made only in first gate electrode 121a and second grid
The lower section of electrode 121b, however, the present invention is not limited thereto.Gate insulating layer 115b may be formed at is formed with the first active layer thereon
On the entire substrate 110 of 124a and the second active layer 124b.In this case, in gate insulating layer 115b, can be formed by
First source electrode 122a and the first drain electrode 123a is connected to the source region and drain region of the first active layer 124a
Contact hole.In addition, can be formed in gate insulating layer 115b by the second source electrode 122b and the second drain electrode 123b connection
To the source region of the second active layer 124b and the contact hole of drain region.
Grid line 117 may be provided on layer identical with first gate electrode 121a and second grid electrode 121b.At this
In kind situation, above-mentioned gate insulating layer 115b may be provided at the lower section of grid line 117.However, the invention is not limited thereto.
First gate electrode 121a and second grid electrode 121b and grid line 117 can by various conductive materials, for example,
Molybdenum (Mo), aluminium (Al), chromium (Cr), golden (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) one of arbitrarily or these materials
In the alloy of two or more or its multilayer constitute.
Can be used includes the oxide semiconductor structure selected from one of Zn, Cd, Ga, In, Sn, Hf and Zr or various metals
At the first active layer 124a and the second active layer 124b, or amorphous silicon (a-Si), polysilicon (poly-Si) or organic can be passed through
Semiconductor constitutes the first active layer 124a and the second active layer 124b.
First source electrode 122a and the second source electrode 122b can be respectively by passing through the first of interlayer insulating film 115c
Contact hole 140a and the 4th contact hole 140d is connected to the source region of the first active layer 124a and the second active layer 124b.First
Drain electrode 123a and the second drain electrode 123b can respectively by across interlayer insulating film 115c the second contact hole 140b and
5th contact hole 140e is connected to the drain region of the first active layer 124a and the second active layer 124b.
Interlayer insulating film 115c can be by the single layer of the silicon nitride SiNx or Si oxide SiOx of inorganic material or inorganic
The multilayer of the silicon nitride SiNx or Si oxide SiOx of material are formed.As shown in Fig. 4 to 6, interlayer insulating film 115c can shape
At on entire substrate 110 or being made only in pixel region, however, the present invention is not limited thereto.
First source electrode 122a and the second source electrode 122b and the first drain electrode 123a and the second drain electrode
123b can by various conductive materials, for example, molybdenum (Mo), aluminium (Al), chromium (Cr), golden (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and
One of any or alloy of two or more in these materials of copper (Cu) or its multilayer are constituted.
Second drain electrode 123b of switching transistor is upwardly extended, to be electrically connected to the first grid electricity of driving transistor
Pole 121a.Specifically, the second drain electrode 123b can pass through the 6th contact hole 140f connection across interlayer insulating film 115c
To first gate electrode 121a.
First drain electrode 123a can by across protective layer 115d and planarization layer 115e third contact hole 140c and
Hole H is connected to the anode 126 of light emitting diode.
As described above, in the el display device 100 of illustrative embodiments according to the present invention, data line 116
Be arranged on substrate 110 in a first direction with the vertical line of power supply line 119, and grid line 117 horizontal line setting with
In the second direction that first direction intersects, to drive pixel region together with vertical line.
In the el display device 100 of illustrative embodiments according to the present invention, data line 116 and power supply line
119 vertical line setting with as on the identical layer of undermost light shield layer 125, and the horizontal line setting of grid line 117
On layer identical with first gate electrode 121a and second grid electrode 121b.Therefore, gate insulating layer 115b and buffer layer
115a rather than the interlayer insulating film 115c of the relevant technologies, may be inserted between vertical line and horizontal line.In this case, grid
Insulating layer 115b and buffer layer 115a are unrelated with the capacity of capacitor for pole, so that gate insulating layer 115b and/or buffer layer 115a
Thickness increase, to avoid at vertical line and horizontal cross section generate short trouble.
That is in the related art, need to form grid redundant pattern repair the horizontal line of grid line and data line/
Short trouble between the vertical line of power supply line.However, it is exhausted to be only inserted into interlayer between horizontal line and the cross section of vertical line
Edge layer so that lead to electrostatic breakdown due to shorter distance, and can lead to the horizontal line due to caused by impurity with it is vertical
Short circuit between line or the failure due to caused by the insulation layer state above grid line.Therefore, it is necessary to design use within the pixel
In the structure of reparation, to improve yield.Therefore, in the related art, the location application intersected with each other to horizontal line and vertical line
Grid redundant pattern.Grid redundant pattern is formed as occupying the presumptive area above and below grid line, so as to cause in pixel
The reduction of aperture opening ratio.Further, since increasing grid redundant pattern within the pixel, so being difficult to design picture with high resolution model
Element.
According to an illustrative embodiment of the invention, it is noted that only inserted between horizontal line and the cross section of vertical line
Enter interlayer insulating film 115c, so that cross section is influenced vulnerable to short trouble, short trouble is influenced by the spacing distance between line.
Therefore, data line 116 and power supply line 119 are arranged on the layer different from the relevant technologies, so that not being interlayer in the related technology
Insulating layer 115c, but gate insulating layer 115b and buffer layer 115a may be inserted between horizontal line and vertical line.In this feelings
In shape, gate insulating layer 115b and buffer layer 115a are unrelated with the capacity of capacitor, so that gate insulating layer 115b and/or buffering
The thickness of layer 115a increases, to avoid the short trouble generated at vertical line and horizontal cross section.
Therefore, the grid redundant pattern in pixel can be omitted, so that can be easy to design pixel in high resolution model simultaneously
Yield is improved, and has additionally ensured that aperture opening ratio.
As described above, interlayer insulating film is only inserted between horizontal line and the cross section of vertical line, so that due to shorter
Distance and lead to electrostatic breakdown, and can lead to the short circuit between horizontal line and vertical line due to caused by impurity or due to
Failure caused by insulation layer state above grid line.Therefore, it is necessary to the structures within the pixel designed for reparation, to improve
Yield.Therefore, in the related art, the location application grid redundant pattern intersected with each other to horizontal line and vertical line.Grid is superfluous
Remaining pattern is formed as occupying the presumptive area above and below grid line, so that the open cells in pixel reduce.
This is because needing to be inserted into interlayer insulating film between vertical line and horizontal line and needing to increase interlayer insulating film
Thickness be difficult to increase the thickness of interlayer insulating film to remove grid redundant pattern, but in order to ensure the capacity of capacitor.
In contrast, as described above, according to an illustrative embodiment of the invention, data line 116 and power supply line 119 hang down
Straight line is arranged on layer identical with light shield layer 125, so that gate insulating layer 115b and the two insulating layers of buffer layer 115a are inserted
Enter between vertical line and horizontal line.In this case, the capacity of gate insulating layer 115b and buffer layer 115a and capacitor
It is unrelated, so that the thickness of gate insulating layer 115b and/or buffer layer 115a increase, to avoid in vertical line and horizontal intersection
The short trouble generated at part.Therefore, it can remove the grid redundant pattern in pixel, so that open cells A can expand grid
The so big size of redundant pattern can be conducive to the pixel design in high resolution model, and yield can be improved.
Next, protective layer 115d and planarization layer 115e may be provided on thin film transistor (TFT).Protective layer 115d protection is thin
Film transistor, the gate drivers being arranged in outside pixel region and other wirings.Planarization layer 115e is by making substrate
Step on 110 flatten it is slow and by the insulating layer of the upper planar of substrate 110.
Planarization layer 115e can be formed by organic insulating material.That is planarization layer 115e can be by acrylic resin, ring
Oxygen resin, phenolic resin, polyamide, polyimide resin, unsaturated polyester resin, polyphenylene oxide resin, polyphenylene sulfide resin
Rouge, the one of any of benzocyclobutene and photoresist are formed, but not limited to this.
In the presumptive area of circuit unit, planarization layer 115e is removed, to form hole H, hole H exposure protective layer 115d
Surface a part and via third contact hole 140c exposure the second drain electrode 123a below.
Referring to Fig. 4, light emitting diode be may be provided on planarization layer 115e.For example, shining as Organic Light Emitting Diode
Diode includes being formed on planarization layer 115e to be electrically connected to the anode 126 of the first drain electrode 123a of transistor, set
It sets in the organic luminous layer 127 on anode 126 and the cathode 128 being formed on organic luminous layer 127.
Anode 126 may be provided on the inside and planarization layer 115e of hole H and by be formed in protective layer 115d and
Third contact hole 140c and hole H in planarization layer 115e are electrically connected to the first drain electrode 123a.Anode 126 can be by having height
The conductive material of work function is formed, to provide hole to organic luminous layer 127.For example, anode 126 can by transparent conductive material,
Such as tin indium oxide (ITO), indium zinc oxide (IZO) or indium tin zinc oxide (ITZO) formation.
Be arranged in the inside of hole H anode 126 and protective layer 115d below the second drain electrode 123b a part (for
Convenience, referred to as storage electrode) overlapping and protective layer 115d insertion between them, to constitute first capacitor device.In addition, the
A part of two drain electrode 123b, that is, one of the first active layer 124a below storage electrode, with interlayer insulating film 115c
Divide overlapping and interlayer insulating film 115c insertion between them, to constitute the second capacitor.As described above, according to the present invention
Illustrative embodiments, first capacitor device and the second capacitor are connected in parallel, to increase the capacity of entire capacitor.Meanwhile such as
Upper described, the thickness of protective layer 115d and interlayer insulating film 115c reduce, so that can increase first capacitor compared with the relevant technologies
The capacity of device and the second capacitor.For example, the protective layer 115d and interlayer insulating film of illustrative embodiments according to the present invention
115c can have thickness more smaller than gate insulating layer 115b and buffer layer 115a.
In figures 3 and 4, for example, illustrating the first drain electrode 123a that anode 126 is electrically connected to driving transistor, but
The invention is not limited thereto.Therefore, according to the design method of the type of thin film transistor (TFT) and driving circuit, anode 126 can be electrically connected
To the first source electrode 122a of driving transistor.
Organic luminous layer 127 is the organic layer for emitting the light of specific color, and organic luminous layer 127 may include red organic hair
Photosphere, green organic luminous layer, blue organic luminous layer and white organic light emitting layer it is one of any.In addition, organic luminous layer
127 can further comprise various organic luminous layers, such as hole transmission layer, hole injection layer, electron injecting layer or electron-transport
Layer.In Fig. 4, illustrates organic luminous layer 127 and be patterned for each pixel, however, the present invention is not limited thereto, You Jifa
Photosphere 127 can be the common layer being collectively form for multiple pixels.
Cathode 128 may be provided on organic luminous layer 127.Cathode 128 can provide electronics to organic luminous layer 127.Cathode
128 can be by such as tin indium oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO) and tin oxide
(TO) etc transparent conductive oxide or ytterbium (Yb) alloy is formed.Optionally, cathode 128 can be formed by conductive material.
Then, it may be provided on anode 126 and planarization layer 115e referring to Fig. 4 to 6, dyke 115f.Dyke 115f can cover
A part of the anode 126 of lid Organic Light Emitting Diode or a part of wiring.Dyke 115f can be set in pixel region
Divide adjacent pixel.
Dyke 115f can be formed by organic insulating material.For example, dyke 115f can be by polyimides, acryl (acryl)
Or benzocyclobutene (BCB) resin is formed, however, the present invention is not limited thereto.
Dyke 115f may be provided on planarization layer 115e, and to surround luminescence unit, and dyke 115f can be set to cover
Cover the bridging line 119a of lower section.
For protecting the Organic Light Emitting Diode vulnerable to influence of moisture to make it be not exposed to the encapsulation unit of moisture (not
Show) it may be formed at the top of the Organic Light Emitting Diode configured as described above.For example, encapsulation unit can have inorganic layer and have
The structure of machine layer alternatively laminated, however, the present invention is not limited thereto.
Meanwhile it is similar with above-mentioned organic electroluminescence display device and method of manufacturing same, contact hole is formed in a insulating layer, so that being located at insulation
Component (between inserted at least one insulating layer) above and below layer is in contact with each other (or connection).Meanwhile the relevant technologies
Contact structures have contact hole by upper member and lower member, for example, the structure of upper electrode and lower electrode covering.At this
In kind situation, the size (or area) of contact hole is identical as the contact area that upper electrode and lower electrode are in contact with each other.
In this case, in the related art, due to the minimum dimension for patterned contact hole, in pixel design
There are limitations.
In addition, the overlapping nargin between lower electrode and contact hole and between upper electrode and contact hole is necessary
, thus the freedom degree of metal reduces in pixel design.That is because upper electrode needs to cover contact hole, so that lower part
Electrode is not damaged by the etchant of upper electrode, so the nargin of upper electrode is necessary.In addition, in order to by contact hole pattern
It turns to without departing from lower electrode, the nargin of lower electrode is also necessary.The contact structures of the relevant technologies as described above for
Nargin is needed for upper electrode and lower electrode, so that the freedom degree of metal reduces in pixel design.
Therefore, according to an illustrative embodiment of the invention, it is noted that the reason of generating the above-mentioned nargin of contact hole be because
It is equal to contact area for the size (or area) of contact hole, when the characteristic in view of lower layer applies different contact hole structures
When, pixel can be independently designed with the size of contact hole.Therefore, the invention discloses a kind of contact structures, wherein by that will connect
The size (or area) of contact hole is designed to be greater than contact area and according to the characteristic of lower layer using different structures, can with contact
The size in hole independently designs pixel.
That is the size (or area) of contact hole is designed to be greater than contact area, and will according to the characteristic of lower layer
Two existing contact hole combinations, contact portion is formed on the side of metal or upper electrode is formed as the shape with cladding
Formula surrounds lower electrode.Therefore, pixel can independently be designed with the size of contact hole.That is when size (or the face of contact hole
Product) when being designed to be greater than contact area, the nargin of above-mentioned upper electrode and the nargin of lower electrode are unnecessary, so that can be with
The size of contact hole independently designs pixel.Hereinafter, it will be described in detail with reference to the accompanying drawings and arrive contact structures realization of the invention
The example of above-mentioned el display device.
As described above, the contact structures of illustrative embodiments are applied to basis shown in Fig. 3,5 and 6 according to the present invention
A part of the el display device 100 of exemplary embodiment of the invention.
Fig. 7 A and 7B are the plan view and sectional view as example diagram according to the contact structures of comparative example.Fig. 8 A and 8B are
The plan view and sectional view of the contact structures of illustrative embodiments according to the present invention are illustrated as example.
Fig. 7 B diagrammatically illustrates cuing open for the line a-a ' interception in the contact structures shown in Fig. 7 A according to comparative example
The a part in face.Fig. 8 B diagrammatically illustrates the line b- in the contact structures according to illustrative embodiments shown in Fig. 8 A
A part of the section of b ' interception.
Referring to Fig. 7 A and 7B, the contact structures according to comparative example include the lower layer 24 on substrate 10；Layer insulation
Layer 15c, interlayer insulating film 15c are arranged on lower layer 24 and expose a part of lower layer 24 with contact hole 40；With
And upper layer 22, upper layer 22 are arranged on interlayer insulating film 15c, to be contacted by contact hole 40 with lower layer 24.
In this case, buffer layer 15a is further disposed at 24 lower section of lower layer.
Lower layer 24 is the active layer formed by semiconductor, and upper layer 22 is the source electrode formed by conductive material.
There is upper member and lower member according to the contact structures of comparative example, for example, upper layer 22 and lower layer 24 cover
The structure of lid contact hole 40.In this case, the size (or area) Yu upper layer 22 of contact hole 40 and lower layer 24 be each other
The contact area of contact is identical.It is understood that the length l of Fig. 7 B is the width of contact hole 40, it is equal to upper layer 22 and lower layer
The width of 24 contact portions being in contact with each other.
In this case, in the related art, it due to the minimum dimension for patterned contact hole 40, is designed in pixel
It is middle to there is limitation.
In addition, between upper layer 22 and contact hole 40 and between lower layer 24 and contact hole 40 overlap nargin m1 and
M2 is necessary, so that the freedom degree of metal reduces in pixel design.That is because upper layer 22 needs to cover contact hole
40, so that lower layer 24 is not damaged by the etchant of upper layer 22, so top overlaps nargin m1 and is necessary.In addition, in order to
Contact hole 40 is patterned without departing from lower layer 24, and overlapping nargin m2 is also necessary for lower layer 24.Institute as above
It states, in the contact structures of comparative example, overlaps nargin m1 and m2 for upper layer 22 and lower layer 24 and be necessary, so that
The freedom degree of metal reduces in pixel design.
Referring to Fig. 8 A and 8B, the contact structures of illustrative embodiments include under being located on substrate 110 according to the present invention
Portion's layer 124；Interlayer insulating film 115c, interlayer insulating film 115c are arranged on lower layer 124 and have contact hole 140 with exposure
A part of lower layer 124；And upper layer 122, upper layer 122 is arranged on interlayer insulating film 115c, to pass through contact hole
140 contact with lower layer 124.
In this case, buffer layer 115a can be further disposed at the lower section of lower layer 124.Contact hole 140 has sudden and violent
Reveal the opening of a part for the lower layer 124 not contacted with upper layer 122.Then, protective layer 115d be formed on substrate 110 with
Fill (or built-in) in the opening.
Lower layer 124 is the active layer formed by semiconductor, and upper layer 122 is the source electrode formed by conductive material,
However, the present invention is not limited thereto.
In this case, exemplary embodiments of the present invention disclose a kind of contact structures, wherein contact hole 140
Size (or area) is designed to be greater than contact area and according to the characteristic of lower layer 124 using different structures, so that can be with
The size of contact hole 140 independently designs pixel.That is such as, it is to be understood that the length L1 of Fig. 8 B is the width of contact hole 140
Degree is opposite to be longer than upper layer 122 and the width L2 of contact portion that lower layer 124 is in contact with each other.As described above, working as contact hole
Size (or area) when being designed to be greater than contact area, above-mentioned top overlap nargin and lower part overlap nargin be it is unnecessary,
So that pixel can independently be designed with the size of contact hole 140.
Contact hole 140 can expose one of a part of the upper surface of lower layer 124 and the upper surface of buffer layer 115a
Point.In addition, upper layer 122 can be with the exposed portion of the upper surface of the expose portion and buffer layer 115a of the upper surface of lower layer 124
Tap touching.
Said circumstances are applicable to when etching upper layer 122, the not impaired situation of lower layer 124.If lower layer
It is damaged, then can apply another structure.
Hereinafter, the specific contact structures of the characteristic based on lower layer be will be described in.
For ease of description, according to the type of upper layer and lower layer, contact hole can be divided into three types.Type-A refers to
Contact between source/drain electrodes and active layer, G type refer to the contact between gate electrode and source/drain electrodes, L
Type refers to the contact between vertical line and source/drain electrodes.
In addition, contact hole is divided into four kinds of situations according to the type and characteristic of lower layer.
The first situation is above-mentioned type-A, and the active layer as lower layer is to the source/drain electrodes as upper layer
Etchant is not reacted.In this case, the area of contact hole may be designed to be greater than contact area.
Next, two contact hole groups used in the relevant technologies are combined into a contact hole in second case, such as
Second case can be applied to L type.
Next, the third situation and the 4th kind of situation can be applied to above-mentioned G type, though when upper layer and lower layer by
It can also be applied when the identical material formation of such as copper etc.Therefore, the freedom degree of metal can be increased.
Wherein, in the third situation, contact portion is formed in the side of lower layer, so that can reduce the face of contact hole
Product.Lower layer is surrounded in the form coated and is suitable for protecting the structure of lower layer in addition, the 4th kind of situation is upper layer.
Fig. 9 A and 9B are the exemplary plan views of schematic illustrations contact structures of illustrative embodiments according to the present invention
And sectional view.Figure 10 is the exemplary plan view for illustrating the contact structures according to comparative example.
In this case, Fig. 9 A and 9B illustrates the first situation of type-A as example, the first situation can be applied
The 4th contact hole 140d shown in Fig. 3.Fig. 9 B is diagrammatically illustrated shown in Fig. 9 A according to illustrative embodiments
Contact structures in line A-A ' interception section a part.
Referring to Fig. 9 A and 9B, the contact structures of illustrative embodiments include under being located on substrate 110 according to the present invention
Portion's layer, such as the second active layer 124b；Interlayer insulating film 115c, interlayer insulating film 115c are arranged on the second active layer 124b simultaneously
And with the 4th contact hole 140d with a part of the second active layer 124b of exposure；And upper layer, for example, the second source electrode
122b, the second source electrode 122b are arranged on interlayer insulating film 115c, to pass through the 4th contact hole 140d and the second active layer
124b contact.
In this case, buffer layer 115a can be further disposed at the lower section of the second active layer 124b.4th contact hole
The opening of a part for the second active layer 124b that there is 140d exposure not contact with the second source electrode 122b.Then, it protects
Layer 115d is formed on substrate 110 with filling (or built-in) in the opening.
Second active layer 124b can be made of semiconductor, and the second source electrode 122b can be constructed from a material that be electrically conducting.
The 4th contact hole 140d of illustrative embodiments can have than the second source electrode 122b and according to the present invention
Two active layer 124b are in contact with each other the relatively large area of contact area of (or connection).
In this case, the 4th contact hole 140d can expose a part and the side of the upper surface of the second active layer 124b
The a part in portion and the upper surface of buffer layer 115a.In addition, the second source electrode 122b can be upper with the second active layer 124b
The contact of the expose portion of the expose portion on surface and side and the upper surface of buffer layer 115a.
The first above-mentioned situation is suitable for when etching upper layer, the not impaired situation of lower layer.
In contrast, referring to Fig.1 0, in a comparative example, it is to be understood that the size of the 4th contact hole 40d is equal to the second source electrode electricity
Pole 22b and the second active layer 24b is in contact with each other the contact area of (or connection).In this case, as described above, top is overlapping
Nargin and lower part overlap nargin and are necessary for being formed for the 4th contact hole 40d.
Figure 11 A and 11B are the another exemplary of schematic illustrations contact structures of illustrative embodiments according to the present invention
Plan view and sectional view.Figure 12 is another exemplary plan view for illustrating the contact structures according to comparative example.
In this case, Figure 11 A and 11B illustrates the second case of L type as example, and second case can answer
For the 7th contact hole 140g shown in Fig. 3.Figure 11 B is diagrammatically illustrated shown in Figure 11 A according to exemplary implementation
A part of the section of line B-B ' interception in the contact structures of mode.
1A and 11B referring to Fig.1, as another example, the contact structures of illustrative embodiments include position according to the present invention
Lower layer on substrate 110, for example, data line 116；Buffer layer 115a, buffer layer 115a be arranged on data line 116 and
A part of data line 116 is exposed with the 7th contact hole 140g；Interlayer insulating film 115c；And upper layer, for example, second
Source electrode 122b, the second source electrode 122b is arranged on interlayer insulating film 115c, to pass through the 7th contact hole 140g and number
It is contacted according to line 116.
Data line 116 is made of the first conductive material, and the second source electrode 122b can be made of the second conductive material.At this
In kind situation, the first conductive material and the second conductive material can be formed from different materials.7th contact hole 140g has exposure
Not with the opening of a part of the second source electrode 122b substrate 110 contacted.Then, protective layer 115d is formed in substrate 110
On with filling (or built-in) in the opening.
The 7th contact hole 140g of illustrative embodiments can have than the second source electrode 122b sum number according to the present invention
Be in contact with each other according to line 116 the relatively large area of contact area of (or connection).
In this case, data line 116 may make up two adjacent wirings, and each second source electrode 122b can
Every data line 116 is connected to by a 7th contact hole 140g.
7th contact hole 140g can expose a side of a part of the upper surface of every data line 116, data line 116
The upper surface of substrate between portion and two data lines 116.
In this case, each second source electrode 122b can be contacted with the expose portion of the upper surface of data line 116.
In contrast, data line 116, a side not contacted with the second source electrode 122b can be exposed, and not by buffer layer
115a and interlayer insulating film 115c covering.
Above-mentioned second case is suitable for two contact hole groups being combined into a contact hole.
In contrast, referring to Fig.1 2, it is to be understood that in a comparative example, the size of the 7th contact hole 40g is equal to the second source electrode electricity
Pole 22b and data line 16 are in contact with each other the contact area of (or connection).7th contact hole 40g is applied individually to any the second source electrode
The contact of 22b and data line 16.
Figure 13 A and 13B are the another exemplary of schematic illustrations contact structures of illustrative embodiments according to the present invention
Plan view and sectional view.Figure 14 is the another exemplary plan view for illustrating the contact structures according to comparative example.
In this case, Figure 13 A and 13B illustrates the 4th kind of situation of G type as example, and the 4th kind of situation can answer
For the 6th contact hole 140f shown in Fig. 3.Figure 13 B is diagrammatically illustrated shown in Figure 13 A according to exemplary implementation
A part of the section of line C-C interception in the contact structures of mode.
3A and 13B referring to Fig.1, as another example, the contact structures of illustrative embodiments include position according to the present invention
Lower layer on substrate 110, for example, first gate electrode 121a；Interlayer insulating film 115c, interlayer insulating film 115c setting exist
On first gate electrode 121a, and some parts of interlayer insulating film 115c are removed so that interlayer insulating film 115c has
There is the 6th contact hole 140f to expose first gate electrode 121a；And upper layer, for example, the second drain electrode 123b, second
Drain electrode 123b is contacted in the inside of the 6th contact hole 140f with first gate electrode 121a.Lower layer and upper layer can be successively
It is stacked in the inside of the 6th contact hole 140f.
First gate electrode 121a can be made of the first conductive material.Second drain electrode 123b can be by the second conductive material
It constitutes.In this case, the first conductive material and the second conductive material can be formed from the same material.However, the present invention is unlimited
In this, the first conductive material and the second conductive material can be formed by different materials.
Buffer layer 115a may be provided at the lower section of first gate electrode 121a and in buffer layer 115a and first grid electricity
Gate insulating layer 115b is inserted between the 121a of pole.There is 6th contact hole 140f exposure not contact with the second drain electrode 123b
The opening of a part of buffer layer 115a.Then, protective layer 115d is formed on substrate 110 is being open with filling (or built-in)
In.
The 6th contact hole 140f of illustrative embodiments can have than first gate electrode 121a and according to the present invention
Two drain electrode 123b are in contact with each other the relatively large area of contact area of (or connection).
In this case, for example, the 6th contact hole 140f can expose the upper surface of first gate electrode 121a, the first grid
A part of the upper surface of two sides and buffer layer 115a of pole electrode 121a and two sides of gate insulating layer 115b
Portion.
In this case, the second drain electrode 123b can exposed upper surface, the first grid with first gate electrode 121a
The expose portion of the upper surface of two sides and buffer layer 115a of pole electrode 121a and two sides of gate insulating layer 115b
Portion's contact.
In addition, the second drain electrode 123b can have covering and surround the exposed upper surface and of first gate electrode 121a
The clad structure of two sides of one gate electrode 121a.
Even if when so that increasing the freedom degree of metal, can also be applied when upper layer and lower layer are formed from the same material
Above-mentioned 4th kind of situation.In addition, the form that lower layer is coated by upper layer is surrounded, make it suitable for the protection to lower layer.
In contrast, referring to Fig.1 4, in a comparative example, it is to be understood that the size of the 6th contact hole 40f is equal to first grid electricity
Pole 21a and the second drain electrode 23b is in contact with each other the contact area of (or connection).
Figure 15 A and 15B are the another exemplary of schematic illustrations contact structures of illustrative embodiments according to the present invention
Plan view and sectional view.
In this case, Figure 15 A and 15B illustrates the third situation of G type as example, the third situation can also
Applied to the 6th contact hole shown in Fig. 3.Figure 15 B is diagrammatically illustrated shown in Figure 15 A according to exemplary embodiment party
A part of the section of line D-D ' interception in the contact structures of formula.
5A and 15B referring to Fig.1, as another example, the contact structures of illustrative embodiments include position according to the present invention
Lower layer on substrate 210, for example, first gate electrode 221a；Interlayer insulating film 215c, interlayer insulating film 215c setting exist
A part of first gate electrode 221a is exposed on first gate electrode 221a and with the 6th contact hole 240f；On and
Portion's layer, for example, the second drain electrode 223b, the second drain electrode 223b passes through the 6th contact hole 240f and first gate electrode
221a contact.
First gate electrode 221a can be made of the first conductive material.Second drain electrode 223b can be by the second conductive material
It constitutes.In this case, the first conductive material and the second conductive material can be formed from the same material.However, the present invention is unlimited
In this, the first conductive material and the second conductive material can be formed by different materials.
Buffer layer 215a may be provided at below first gate electrode 221a and in buffer layer 215a and first gate electrode
Gate insulating layer 215b is inserted between 221a.It is slow that there is 6th contact hole 240f exposure not contact with the second drain electrode 223b
Rush the opening of a part of layer 215a.Then, protective layer 215d formed over the substrate 210 with filling (or built-in) in the opening.
The 6th contact hole 240f of illustrative embodiments can have than first gate electrode 221a and according to the present invention
Two drain electrode 223b are in contact with each other the relatively large area of contact area of (or connection).
In this case, as an example, the 6th contact hole 240f can expose the upper surface of first gate electrode 221a
A part of a part and the upper surface of side, a part of the side of gate insulating layer 215b and buffer layer 215a.
In this case, the second drain electrode 223b can with the expose portion of the upper surface of first gate electrode 221a and
Side, buffer layer 215a upper surface expose portion and gate insulating layer 215b side expose portion contact.
Even if when so that increasing the freedom degree of metal, can also be applied when upper layer and lower layer are formed from the same material
The third above-mentioned situation.Therefore, area can be reduced.
Exemplary embodiments of the present invention also can be described as follows:
The contact structures of illustrative embodiments include: lower layer according to the present invention；On the lower layer at least
First insulating layer, first insulating layer have predetermined contact hole with a part of the exposure lower layer；Be located at described the
Upper layer on one insulating layer to be contacted by the contact hole with the lower layer, wherein the contact hole has than contact surface
The relatively large area of product, wherein the contact area is the upper layer and the contact area that the lower layer is in contact with each other.
According to another aspect of the present invention, the contact structures may also include that positioned at the lower section of the lower layer
Two insulating layers.
According to another aspect of the present invention, the lower layer can be made of semiconductor, and the upper layer can be by leading
Electric material is constituted.
According to another aspect of the present invention, the contact hole can expose a part and the side of the upper surface of the lower layer
The a part in portion and the upper surface of the second insulating layer.
According to another aspect of the present invention, the upper layer can expose portion with the upper surface of the lower layer and side
The contact of the expose portion of portion and the upper surface of the second insulating layer.
According to another aspect of the present invention, the lower layer can be made of the first conductive material, and the upper layer
It can be made of the second conductive material.
According to another aspect of the present invention, first conductive material and second conductive material can be by different materials
Material is made.
According to another aspect of the present invention, the lower layer may make up two adjacent wirings, and the upper layer can
Constitute two electrodes connecting respectively with the wiring by the contact hole.
According to another aspect of the present invention, the contact hole can expose a part and the side of the upper surface of every wiring
Portion and the upper surface of the substrate between two wirings.
According to another aspect of the present invention, each electrode can be contacted with the expose portion of the upper surface of every wiring.
According to another aspect of the present invention, the side of the wiring not contacted with the upper layer can be sudden and violent
Dew.
According to another aspect of the present invention, first conductive material and second conductive material can be by identical materials
Material is made.
According to another aspect of the present invention, the contact structures, which may also include that, is inserted in the lower layer and described the
Second insulating layer between one insulating layer.
The contact structures of illustrative embodiments include: at least the first insulating layer on substrate, institute according to the present invention
The first insulating layer is stated with predetermined contact hole；With the lower part for being located at the inside of the contact hole and being sequentially stacked and being in contact with each other
Layer and upper layer, wherein the contact hole has the area more relatively large than contact area, wherein the contact area is on described
The contact area that portion's layer and the lower layer are in contact with each other.
According to another aspect of the present invention, the contact hole can may also include on the substrate and be located at described
The second insulating layer of the lower section of first insulating layer, the upper surface and two sides of upper layer described in the contact holes exposing and
A part of the upper surface of the second insulating layer.
According to another aspect of the present invention, the upper layer can with the upper surface of the lower layer and two sides, with
And the part contact of the upper surface of the second insulating layer.
According to another aspect of the present invention, the upper layer can be made of clad structure, and the clad structure covering is simultaneously
Surround the upper surface of the lower layer and two sides of the lower layer.
According to another aspect of the present invention, the contact structures may also include the third positioned at the lower section of the lower layer
Insulating layer, the contact hole can expose a part of the upper surface of the lower layer and the upper table of side, the second insulating layer
A part of the side of a part in face and the third insulating layer.
According to another aspect of the present invention, the upper layer can expose portion with the upper surface of the lower layer and side
Portion, the expose portion of the second insulating layer and the third insulating layer side expose portion contact.
The display device of illustrative embodiments includes: on the substrate and in a first direction according to the present invention
Data line；The first insulating layer on the data line；Active layer on first insulating layer；Grid line, it is described
Grid line is located on first insulating layer and in the second direction intersected with the first direction, with the data line one
It rises and divides pixel region, wherein inserted at least one second insulating layer between the grid line and first insulating layer；
Gate electrode positioned at the top of the active layer, between the gate electrode and the active layer absolutely inserted with described second
Edge layer；Third insulating layer on the gate electrode and the grid line；Source electrode electricity on the third insulating layer
Pole and drain electrode；The 4th insulating layer on the source electrode and the drain electrode；Positioned at the 4th insulating layer
Top and the light emitting diode in the luminescence unit of the pixel region；And contact hole, the contact hole configuration is described
In at least one insulating layer in first insulating layer to the 4th insulating layer, so that at least one insulating layer is upper
The component of side and lower section is in contact with each other, wherein the contact hole has the area more relatively large than contact area, wherein the contact
Area is the contact area that the component above and below at least one described insulating layer is in contact with each other.
Although exemplary embodiments of the present invention are described in detail with reference to attached drawing, the present invention is not limited thereto,
In the case where without departing substantially from technical concept of the invention, it can be embodied in many different forms.Therefore it provides example of the invention
Property embodiment purpose only for the purpose of illustration, the technical concept being not intended to limit the invention.Technology structure of the invention
The range of think of is without being limited thereto.It will thus be appreciated that above-mentioned example embodiment be all in all respects it is illustrative,
It is not intended to limit the present invention.Protection scope of the present invention should be explained based on appended claims, the institute in equivalency range
There is technical concept all to should be construed as falling within the scope of the present invention.
Claims (18)
1. a kind of contact structures, comprising:
Lower layer；
At least the first insulating layer on the lower layer, first insulating layer have predetermined contact hole with exposure it is described under
A part of portion's layer；With
Upper layer on first insulating layer to be contacted by the contact hole with the lower layer,
Wherein the contact hole has the area more relatively large than contact area, wherein the contact area is the upper layer and institute
State the contact area that lower layer is in contact with each other.
2. contact structures according to claim 1, further includes:
Second insulating layer positioned at the lower section of the lower layer.
3. contact structures according to claim 2, wherein the lower layer is made of semiconductor, and the upper layer by
Conductive material is constituted.
4. contact structures according to claim 3, wherein one of the upper surface of lower layer described in the contact holes exposing
Divide a part of the upper surface with side and the second insulating layer.
5. contact structures according to claim 4, wherein the exposed portion of the upper surface of the upper layer and the lower layer
Divide the expose portion contact of the upper surface with side and the second insulating layer.
6. contact structures according to claim 1, wherein the lower layer is made of the first conductive material, and it is described on
Portion's layer is made of the second conductive material.
7. contact structures according to claim 6, wherein the lower layer constitutes two adjacent wirings, and the top
Layer constitutes two electrodes connecting respectively with the wiring by the contact hole.
8. contact structures according to claim 7, wherein a part of the upper surface of every wiring of the contact holes exposing
And side and the upper surface of the substrate between two wirings.
9. contact structures according to claim 8, wherein the exposed portion of the upper surface of each electrode and every wiring taps
Touching.
10. contact structures according to claim 9, wherein the side of the wiring not contacted with the upper layer
It is exposed.
11. according to described in any item contact structures of claim 6 to 10, further includes:
The second insulating layer being inserted between the lower layer and first insulating layer.
12. a kind of contact structures, comprising:
At least the first insulating layer on substrate, first insulating layer have predetermined contact hole；With
Inside positioned at the contact hole and the lower layer and upper layer that are sequentially stacked and are in contact with each other,
Wherein the contact hole has the area more relatively large than contact area, wherein the contact area is the upper layer and institute
State the contact area that lower layer is in contact with each other.
13. contact structures according to claim 12 further include being located on the substrate and being located at first insulating layer
Lower section second insulating layer, wherein the upper surface of upper layer described in the contact holes exposing and two sides and described
A part of the upper surface of two insulating layers.
14. contact structures according to claim 13, wherein the exposed upper surface of the upper layer and the lower layer and
The contact of the expose portion of two sides and the upper surface of the second insulating layer.
15. contact structures according to claim 13, wherein the upper layer is made of clad structure, the clad structure
Cover and surround the upper surface of the lower layer and two sides of the lower layer.
16. contact structures according to claim 13 further include the third insulating layer positioned at the lower section of the lower layer,
Described in lower layer described in contact holes exposing upper surface a part and side, one of upper surface of the second insulating layer
Point and the third insulating layer side a part.
17. contact structures according to claim 16, wherein the exposure of the upper surface of the upper layer and the lower layer
The expose portion contact of part and side, the side of the expose portion of the second insulating layer and the third insulating layer.
18. a kind of display device, including according to claim 1 to 17 described in any item contact structures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311439251.5A CN117438433A (en) | 2017-12-11 | 2018-06-06 | Contact structure and display device including the same |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2017-0169193 | 2017-12-11 | ||
| KR1020170169193A KR102052434B1 (en) | 2017-12-11 | 2017-12-11 | Structre for contact and electroluminescent display device using thereof |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311439251.5A Division CN117438433A (en) | 2017-12-11 | 2018-06-06 | Contact structure and display device including the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109904172A true CN109904172A (en) | 2019-06-18 |
| CN109904172B CN109904172B (en) | 2023-11-28 |
Family
ID=66697232
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311439251.5A Pending CN117438433A (en) | 2017-12-11 | 2018-06-06 | Contact structure and display device including the same |
| CN201810575575.4A Active CN109904172B (en) | 2017-12-11 | 2018-06-06 | Contact structure and display device including the same |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311439251.5A Pending CN117438433A (en) | 2017-12-11 | 2018-06-06 | Contact structure and display device including the same |
Country Status (3)
| Country | Link |
|---|---|
| US (4) | US10985189B2 (en) |
| KR (1) | KR102052434B1 (en) |
| CN (2) | CN117438433A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210217781A1 (en) * | 2019-01-11 | 2021-07-15 | Boe Technology Group Co., Ltd. | Array Substrate, Manufacturing Method Thereof, and Display Panel |
| KR20220021947A (en) * | 2020-08-13 | 2022-02-23 | 삼성디스플레이 주식회사 | Display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10115841A (en) * | 1996-10-08 | 1998-05-06 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| US6040589A (en) * | 1996-06-18 | 2000-03-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having larger contact hole area than an area covered by contact electrode in the hole |
| CN103424915A (en) * | 2012-05-24 | 2013-12-04 | 乐金显示有限公司 | Array substrate for liquid crystal display and method for manufacturing the same |
| CN104614906A (en) * | 2013-11-04 | 2015-05-13 | 三星显示有限公司 | Thin film transistor array panel and manufacturing method thereof |
| KR20150072118A (en) * | 2013-12-19 | 2015-06-29 | 엘지디스플레이 주식회사 | Method of forming contact hole and array substrate applying to the same |
| KR20160127459A (en) * | 2015-04-27 | 2016-11-04 | 엘지디스플레이 주식회사 | Organic light emitting diode display and manufacturing method of the same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001223365A (en) * | 2000-02-10 | 2001-08-17 | Fujitsu Ltd | Thin film transistor and its manufacturing method |
| KR100611152B1 (en) * | 2003-11-27 | 2006-08-09 | 삼성에스디아이 주식회사 | Flat Panel Display |
| KR102180067B1 (en) * | 2014-08-07 | 2020-11-17 | 엘지디스플레이 주식회사 | Thin film transistor array substrate |
| KR102296733B1 (en) * | 2014-11-06 | 2021-09-01 | 삼성디스플레이 주식회사 | Organic light emitting device |
| KR102415807B1 (en) * | 2015-09-17 | 2022-07-01 | 엘지디스플레이 주식회사 | Thin Film Transistor Substrate and Manufacturing Method Thereof |
-
2017
- 2017-12-11 KR KR1020170169193A patent/KR102052434B1/en active IP Right Grant
-
2018
- 2018-06-06 CN CN202311439251.5A patent/CN117438433A/en active Pending
- 2018-06-06 CN CN201810575575.4A patent/CN109904172B/en active Active
- 2018-10-19 US US16/165,059 patent/US10985189B2/en active Active
-
2021
- 2021-03-12 US US17/200,531 patent/US11488986B2/en active Active
-
2022
- 2022-09-26 US US17/952,419 patent/US11901371B2/en active Active
-
2023
- 2023-12-23 US US18/395,553 patent/US20240128277A1/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6040589A (en) * | 1996-06-18 | 2000-03-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having larger contact hole area than an area covered by contact electrode in the hole |
| JPH10115841A (en) * | 1996-10-08 | 1998-05-06 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| CN103424915A (en) * | 2012-05-24 | 2013-12-04 | 乐金显示有限公司 | Array substrate for liquid crystal display and method for manufacturing the same |
| CN104614906A (en) * | 2013-11-04 | 2015-05-13 | 三星显示有限公司 | Thin film transistor array panel and manufacturing method thereof |
| KR20150072118A (en) * | 2013-12-19 | 2015-06-29 | 엘지디스플레이 주식회사 | Method of forming contact hole and array substrate applying to the same |
| KR20160127459A (en) * | 2015-04-27 | 2016-11-04 | 엘지디스플레이 주식회사 | Organic light emitting diode display and manufacturing method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109904172B (en) | 2023-11-28 |
| US20240128277A1 (en) | 2024-04-18 |
| CN117438433A (en) | 2024-01-23 |
| US20190181156A1 (en) | 2019-06-13 |
| KR102052434B1 (en) | 2019-12-05 |
| US11901371B2 (en) | 2024-02-13 |
| US20230018904A1 (en) | 2023-01-19 |
| KR20190068927A (en) | 2019-06-19 |
| US20210202533A1 (en) | 2021-07-01 |
| US11488986B2 (en) | 2022-11-01 |
| US10985189B2 (en) | 2021-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11437439B2 (en) | Display device | |
| US11901371B2 (en) | Contact structure and display device including the same | |
| KR102653781B1 (en) | Display device and method of manufacturing the same | |
| CN109994513A (en) | Display device and the method for manufacturing the display device | |
| CN109727566A (en) | Display panel and display equipment | |
| CN111009552B (en) | display device | |
| KR20200036462A (en) | Display device | |
| US11837627B2 (en) | Display apparatus, display panel and method for manufacturing the same | |
| US10861927B2 (en) | Electro-luminescent display device with improved contact structure | |
| KR102513990B1 (en) | Electroluminescent Display Device ANd METHOD OF FABRICATING THE SAME | |
| KR20220078932A (en) | Display device | |
| KR102059950B1 (en) | Electroluminescent Display Device | |
| KR102512779B1 (en) | Electroluminescent display device | |
| EP4216278A2 (en) | Display panel and display device | |
| EP4207977A1 (en) | Organic light emitting display device and organic light emitting display panel | |
| KR20240107489A (en) | Display device | |
| US20230217720A1 (en) | Organic light emitting display device and organic light emitting display panel | |
| US20240221686A1 (en) | Display Device | |
| KR20240107490A (en) | Display device | |
| KR20240107989A (en) | Display device | |
| CN118284185A (en) | Display device | |
| KR20240108062A (en) | Display apparatus and driving method thereof | |
| CN118280307A (en) | Display device | |
| GB2620013A (en) | Touch display device | |
| KR20210085731A (en) | Display apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |