CN109903730A - snubber circuit - Google Patents

snubber circuit Download PDF

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Publication number
CN109903730A
CN109903730A CN201910112826.XA CN201910112826A CN109903730A CN 109903730 A CN109903730 A CN 109903730A CN 201910112826 A CN201910112826 A CN 201910112826A CN 109903730 A CN109903730 A CN 109903730A
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China
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switch
terminal
output
signal
circuit
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CN201910112826.XA
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CN109903730B (en
Inventor
刘立伟
陈彦渊
黄柏文
庄凯杰
邓至刚
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ILI Techonology Corp
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ILI Techonology Corp
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Abstract

A kind of buffer circuit comprising operational amplifier, first and second switching circuit.Operational amplifier has first and second input terminal, first and second output end.Operational amplifier includes front stage circuits, first and second output stage.Front stage circuits couple first input end to receive input signal, couple the second input terminal to receive feedback signal, and generate amplified signal.First output stage is coupled between front stage circuits and the first output end, and generates the first output signal according to amplified signal to drive the first load.Second output stage is coupled between front stage circuits and second output terminal, and generates the second output signal according to amplified signal to drive the second load.First switch circuit is coupled between the first output end and the second input terminal.Second switch circuit is coupled between second output terminal and the second input terminal.When first switch circuit is switched on, and the first output stage generates the first output signal to drive the first load, second switch circuit is disconnected, and the second output stage is disabled.

Description

Buffer circuit
Technical field
The present invention relates to a kind of buffer circuit more particularly to a kind of buffer circuits of high revolution rate.
Background technique
The panel of liquid crystal display device includes multiple liquid crystal displays (liquid crystal cell).It is currently known Same polar voltage is applied to the liquid crystal layer in liquid crystal display for a long time, charge ion is will lead to and remains in liquid crystal layer Internal electric field is generated with orientation membrane interface.This light through characteristic that may cause liquid crystal molecule therein changes, so that Non-response damage occurs for liquid crystal display panel.Therefore, the source electrode driver of liquid crystal display device would generally be by being constantly changing It is applied to the polarity of the driving voltage of liquid crystal display, avoids liquid crystal molecule because being constantly applied same polar driving electricity It presses and damages.
It specifically, generally can be in the defeated of source electrode driver in order to meet the needs of exportable opposed polarity driving voltage The output end of buffer circuit configures transmission gate to switch the driving voltage of output to data line out.It is driven though this mode can meet switching The demand of dynamic polarity of voltage only has certain resistance because being used to switch polar transmission gate of driving voltage itself, can reduce defeated The revolution rate (Slew Rate) of buffer circuit out to influence the charge/discharge speed and characteristic to pixel capacitance, and reduces liquid crystal The display quality of display device.
Summary of the invention
In view of this, the present invention provides a kind of buffer circuit of high revolution rate, asking of solving that prior art addressed is used Topic.
Buffer circuit of the invention includes operational amplifier, first switch circuit and second switch circuit.Operation amplifier Device has first input end, the second input terminal, the first output end and second output terminal.Operational amplifier include front stage circuits, First output stage and the second output stage.Front stage circuits couple first input end to receive input signal, couple the second input terminal To receive feedback signal, and amplified signal is generated accordingly.First output stage is coupled between front stage circuits and the first output end, is used To generate the first output signal according to amplified signal to drive the first load.Second output stage is coupled in front stage circuits and second defeated Between outlet, to generate the second output signal to drive the second load, wherein the pole of the second output signal according to amplified signal Property is identical as the polarity of the first output signal.First switch circuit is coupled between the first output end and the second input terminal, to Transmission first outputs signal to the second input terminal using as feedback signal when switched on.It is defeated that second switch circuit is coupled in second Between outlet and the second input terminal, to when switched on transmission second output signal to the second input terminal using as feedback letter Number.When first switch circuit is switched on, and the first output stage generates the first output signal to drive the first load, second switch Circuit is disconnected, and the second output stage is disabled；And when second switch circuit be switched on, and the second output stage generate second When output signal is to drive the second load, first switch circuit is disconnected, and the first output stage is disabled, the two at least within it One.
Based on above-mentioned, in buffer circuit proposed by the invention, the first output stage of operational amplifier is used to drive the One load, and the second output stage of operational amplifier is used to drive the second load, therefore be by same compared to existing buffer circuit One output stage alternately drives the design of different loads, the operational amplifier in buffer circuit of the present invention by switching transmission gate Setting can be omitted between load to switch the polar transmission gate of driving voltage, can not only reduce the circuit face of buffer circuit Product, can also effectively improve the revolution rate of the output signal of buffer circuit, to improve the driving capability of buffer circuit.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.
Detailed description of the invention
Figure 1A is the circuit diagram according to buffer circuit shown by one embodiment of the invention；
Figure 1B is the circuit diagram according to buffer circuit shown by another embodiment of the present invention；
Fig. 2A is the circuit diagram according to the operational amplifier of Figure 1A embodiment shown by one embodiment of the invention；
Fig. 2 B is the circuit diagram according to the operational amplifier of Figure 1B embodiment shown by one embodiment of the invention；
Fig. 3 A is the circuit diagram according to buffer circuit shown by further embodiment of this invention；
Fig. 3 B is the circuit diagram according to buffer circuit shown by further embodiment of this invention；
Fig. 4 A is the circuit diagram according to the operational amplifier of Fig. 3 A embodiment shown by one embodiment of the invention；
Fig. 4 B is the circuit diagram according to the operational amplifier of Fig. 3 B embodiment shown by one embodiment of the invention.
Drawing reference numeral explanation:
100,200,500,600: buffer circuit
110,210: first switch circuit
120,220: second switch circuit
130,230,330,430,530,630,730,830: operational amplifier
131,231,331,431,731,831: the first output stage
132,232,332,432,732,832: the second output stage
133,233,333,433,733,833: front stage circuits
143,243: third switching circuit
144,244: the four switching circuit
145: basic voltage switching circuit
211_1A: the first differential pair
211_1B: the second differential pair
211_2A: the first current source
211_2B: the second current source
213A: the first active load
213B: the second active load
331_1,431_1,731_1,831_1,332_1,432_1,732_1,832_1: switching circuit
331_2,431_2,731_2,831_2,332_2,432_2,732_2,832_2: output circuit
534,634,734,834: feedback output grade
AGND: ground voltage terminal
AVBN1H、AVBN2H、AVBN3H、AVBN4H、AVBN5H、AVBP1H、AVBP2H、AVBP3H、AVBP4H、 AVBP5H: positive bias voltage
AVBN1L、AVBN2L、AVBN3L、AVBN4L、AVBN5L、AVBP1L、AVBP2L、AVBP3L、AVBP4L、 AVBP5L: back bias voltage voltage
AVF1, AVF2: feedback signal
HPT: control voltage
HPTB: the control voltage of reverse phase
IT1, IT3: first input end
IT2, IT4: the second input terminal
M31, M32, M41, M42, M51~M58, M71, M72, M81, M82, N1A, N2A, N3A, N4A, N5~N9, N9A, N9B, N10, N11, P1A, P2A, P3A, P4A, P5~P9, P9A, P9B, P10, P11, NSW1A, PSW1A, NSW1B, PSW1B: brilliant Body pipe
MCN, MCP: miller capacitance
NAVDD: negative voltage side
OT1, OT3: the first output end
OT2, OT4: second output terminal
OUT1A, OUT2A: the first output signal
OUT1B, OUT2B: the second output signal
PAVDD: positive voltage terminal
S11~S18: switching signal
SN: the second sub- amplified signal
SP: the first sub- amplified signal
SNDA, SNDB, SPDA, SPDB: signal
SW11, SW12, SW21, SW22: earthing switch
SW1A, SW2A, SW3A, SW4A, SW5A, SW1B, SW2B, SW3B, SW4B, SW5B: switch
SWA_P, SWB_P, SWA_N, SWB_N: selection signal
SWAB_P, SWBB_P, SWAB_N, SWBB_N: the selection signal of reverse phase
TG11, TG12, TG21, TG22: transmission gate
VAP, VAN: amplified signal
VINP, VINN: input signal
VNW1, VNW2, VPW1, VPW2: basic voltage
Y1, Y2: load
Specific embodiment
Figure 1A is the circuit diagram according to buffer circuit shown by one embodiment of the invention.Please refer to Figure 1A.Buffering Circuit 100 can be used to be arranged in the source electrode driver of display device, and the voltage signal to generate positive polarity is aobvious to drive Show the pixel of panel.Buffer circuit 100 may include first switch circuit 110, second switch circuit 120 and operational amplifier 130, however, the present invention is not limited thereto.Operational amplifier 130 has first input end IT1, the second input terminal IT2, the first output end OT1 and second output terminal OT2.Operational amplifier 130 may include front stage circuits 133, the first output stage 131 and the second output Grade 132.Front stage circuits 133 couple first input end IT1 to receive input signal VINP, and couple the second input terminal IT2 to connect Feedback signal AVF1 is received, and generates amplified signal VAP accordingly, wherein input signal VINP is positive polar voltage signal.First Output stage 131 is coupled between front stage circuits 133 and the first output end OT1, to generate the first output according to amplified signal VAP Signal OUT1A is to drive load Y1, the polar voltage signal wherein the first output signal OUT1A is positive.Second output stage, 132 coupling Connect between front stage circuits 133 and second output terminal OT2, to according to amplified signal VAP generate the second output signal OUT1B with Driving load Y2, wherein the polarity of the second output signal OUT1B is identical as the polarity of the first output signal OUT1A.In this implementation In example, loads Y1 and load the two data lines (or source electrode line) that Y2 can be display panel respectively.
First switch circuit 110 is coupled between the first output end OT1 and the second input terminal IT2.First switch circuit 110 To transmit the first output signal OUT1A to the second input terminal IT2 when switched on using as feedback signal AVF1.Second switch Circuit 120 is coupled between second output terminal OT2 and the second input terminal IT2.Second switch circuit 120 when switched on to pass Defeated second output signal OUT1B to the second input terminal IT2 is using as feedback signal AVF1.
Specifically, when first switch circuit 110 be switched on, and the first output stage 131 generate positive polarity first output When signal OUT1A is to drive load Y1, second switch circuit 120 is disconnected, and the second output stage 132 is disabled, and causes second Output end OT2 stops driving load Y2 for high impedance status.At this point, load Y2 can be born as caused by another buffer circuit Polar output signal is driven.
Either, when second switch circuit 120 be switched on, and the second output stage 132 generate positive polarity second output letter When number OUT1B is to drive load Y2, first switch circuit 110 is disconnected, and the first output stage 131 is disabled, and is caused first defeated Outlet OT1 stops driving load Y1 for high impedance status.At this point, load Y1 can the cathode as caused by another buffer circuit The output signal of property is driven.
Since the first output stage 131 is only used to drive load Y1, and the second output stage 132 is only used to drive load Y2, therefore The existing buffer circuits of different loads is alternately driven by switching transmission gate compared to by same output stage, the present embodiment It can omit between buffer circuit 100 and load Y1 and load Y2 to switch the polar transmission gate of driving voltage.The present invention is not only The circuit area of buffer circuit 100 can be reduced, the revolution rate of the output signal of buffer circuit 100 can be also effectively improved, to mention The driving capability of high buffer circuit 100.
In addition, as shown in Figure 1A, buffer circuit 100 also optionally includes third switching circuit 143 and the 4th and opens Powered-down road 144.Third switching circuit 143 is coupled between the first output end OT1 and load Y1, to transmit the when switched on One output signal OUT1A is to loading Y1.4th switching circuit 144 be coupled in second output terminal OT2 and load Y2 between, to The second output signal OUT1B is transmitted when switched on to loading Y2.
More specifically, third switching circuit 143 may include earthing switch SW11 and transmission gate TG11.Earthing switch SW11 is coupled between the first output end OT1 and ground voltage terminal AGND.Transmission gate TG11 is coupled in the first output end OT1 and bears It carries between Y1, wherein earthing switch SW11 is opposite with the conducting off-state of transmission gate TG11.In addition, transmission gate TG11 includes P Transistor npn npn M31 and N-type transistor M32.The first end of P-type transistor M31 couples the first output end OT1, P-type transistor The second end coupling load Y1 of M31, and the control terminal of P-type transistor M31 couples ground voltage terminal AGND.N-type transistor M32's First end couples the first output end OT1, the second end coupling load Y1 of N-type transistor M32, and the control terminal of N-type transistor M32 Receive control voltage HPT.
Similarly, the 4th switching circuit 144 may include earthing switch SW12 and transmission gate TG12.Earthing switch SW12 coupling It connects between second output terminal OT2 and ground voltage terminal AGND.Transmission gate TG12 be coupled in second output terminal OT2 and load Y2 it Between, wherein earthing switch SW12 is opposite with the conducting off-state of transmission gate TG12.In addition, transmission gate TG12 includes P-type crystal Pipe M41 and N-type transistor M42.The first end of P-type transistor M41 couples second output terminal OT2, and the of P-type transistor M41 Two ends coupling load Y2, and the control terminal of P-type transistor M41 couples ground voltage terminal AGND.The first end of N-type transistor M42 Second output terminal OT2, the second end coupling load Y2 of N-type transistor M42 are coupled, and the control terminal of N-type transistor M42 receives instead The control voltage HPTB of phase.
When the first output stage 131 generates the first output signal OUT1A to drive load Y1, the second output stage 132 is banned Energy.At this point, transmission gate TG11 is on state, and earthing switch SW11 is off-state, causes the first output signal OUT1A can Load Y1 is transmitted to by transmission gate TG11.And transmission gate TG12 is off-state, and earthing switch SW12 is on state, is caused Be grounded second output terminal OT2 can because of the earthing switch SW12 of conducting.In this way, can avoid the electricity of second output terminal OT2 Pressure polarity is excessive with the both ends cross-pressure that the polarity of voltage for loading Y2 instead results in transmission gate TG12 and damages.
Similarly, when the second output stage 132 generates the second output signal OUT1B to drive load Y2, the first output stage 131 are disabled.At this point, transmission gate TG12 is on state, and earthing switch SW12 is off-state, causes the second output signal OUT1B can be transmitted to load Y2 by transmission gate TG12.And transmission gate TG11 is off-state, and earthing switch SW11 is conducting State causes the first output end OT1 that can be grounded because of the earthing switch SW11 of conducting.In this way, can avoid the first output end The polarity of voltage of OT1 is excessive with the both ends cross-pressure that the polarity of voltage for loading Y1 instead results in transmission gate TG11 and damages.
In addition to this, as shown in Figure 1A, buffer circuit 100 also optionally includes basic voltage switching circuit 145.Base Bottom voltage commutation circuit 145 includes P-type transistor M51, M53, M55, M57 and N-type transistor M52, M54, M56, M58.P-type Transistor M51 and N-type transistor M52 are connected in series between positive voltage terminal PAVDD and ground voltage terminal AGND, P-type transistor M51 and N-type transistor M52 can be controlled by switching signal S11, S12 to provide the P-type transistor M31 in transmission gate TG11 Basic voltage VNW1, to generate substrate bias forward when avoiding opening or closing P-type transistor M31.P-type transistor M53 and N-type transistor M54 are connected in series between ground voltage terminal AGND and negative voltage side NAVDD, P-type transistor M53 and N Transistor npn npn M54 can be controlled by switching signal S13, S14 to provide the substrate of the N-type transistor M32 in transmission gate TG11 Voltage VPW1, to generate substrate bias forward when avoiding opening or closing N-type transistor M32.P-type transistor M55 and N-type Transistor M56 is connected in series between positive voltage terminal PAVDD and ground voltage terminal AGND, P-type transistor M55 and N-type transistor M56 can be controlled by switching signal S15, S16 to provide the basic voltage VNW2 of P-type transistor M41, thus avoid open or Substrate bias forward is generated when P-type transistor M41 in closing transmission door TG12.P-type transistor M57 and N-type transistor M58 It is connected in series between ground voltage terminal AGND and negative voltage side NAVDD, P-type transistor M57 can distinguish with N-type transistor M58 It is controlled by switching signal S17, S18 to provide the basic voltage VPW2 of N-type transistor M42, to avoid opening or closing transmission Substrate bias forward is generated when N-type transistor M42 in door TG12.
Figure 1B is the circuit diagram according to buffer circuit shown by another embodiment of the present invention.Please refer to Figure 1B.It is slow Rushing circuit 200 can be used to be arranged in the source electrode driver of display device, and the voltage signal to generate negative polarity is to drive The pixel of display panel.Buffer circuit 200 may include first switch circuit 210, second switch circuit 220 and operational amplifier 230, however, the present invention is not limited thereto.Operational amplifier 230 has first input end IT3, the second input terminal IT4, the first output end OT3 and second output terminal OT4.Operational amplifier 230 may include front stage circuits 233, the first output stage 231 and the second output Grade 232.Front stage circuits 233 couple first input end IT3 to receive input signal VINN, and couple the second input terminal IT4 to connect Feedback signal AVF2 is received, and generates amplified signal VAN accordingly, wherein input signal VINN is negative polar voltage signal.First Output stage 231 is coupled between front stage circuits 233 and the first output end OT3, to generate the first output according to amplified signal VAN Signal OUT2A is to drive load Y2, the polar voltage signal wherein the first output signal OUT2A is negative.Second output stage, 232 coupling Connect between front stage circuits 233 and second output terminal OT4, to according to amplified signal VAN generate the second output signal OUT2B with Driving load Y1, wherein the polarity of the second output signal OUT2B is identical as the polarity of the first output signal OUT2A.In this implementation In example, loads Y1 and load the two data lines (or source electrode line) that Y2 can be display panel respectively.
First switch circuit 210 is coupled between the first output end OT3 and the second input terminal IT4.First switch circuit 210 To transmit the first output signal OUT2A to the second input terminal IT4 when switched on using as feedback signal AVF2.Second switch Circuit 220 is coupled between second output terminal OT4 and the second input terminal IT4.Second switch circuit 220 when switched on to pass Defeated second output signal OUT2B to the second input terminal IT4 is using as feedback signal AVF2.
Please merge A referring to Fig.1 and Figure 1B, in the first embodiment of the present invention, when first switch circuit 210 be switched on, And first output stage 231 generate negative polarity the first output signal OUT2A with drive load Y2 when, 220 quilt of second switch circuit It disconnects, and the second output stage 232 is disabled, causes second output terminal OT4 to be high impedance status and stop driving load Y1.This When, Y1 first output signal OUT1A as caused by the first output stage 131 of the buffer circuit 100 of Figure 1A is loaded (for anode Property) driven.
In the second embodiment of the present invention, when second switch circuit 220 is switched on, and the second output stage 232 generate it is negative When polar second output signal OUT2B is to drive load Y1, first switch circuit 210 is disconnected, and 231 quilt of the first output stage Forbidden energy causes the first output end OT3 to be high impedance status and stops driving load Y2.At this point, load Y2 can be by the buffering of Figure 1A Second output signal OUT1B (by positive polarity) caused by second output stage 132 of circuit 100 drives.Certainly, above-mentioned One embodiment can also be realized all with second embodiment.
Since the first output stage 231 is only used to drive load Y2, and the second output stage 232 is only used to drive load Y1, because This is the design for alternately driving different loads by switching transmission gate by same output stage compared to existing buffer circuit, It can omit and be arranged to switch the polar transmission of driving voltage between the buffer circuit 200 and load Y1 and load Y2 of the present embodiment Door, can not only reduce the circuit area of buffer circuit 200, can also effectively improve the revolution rate of the output signal of buffer circuit 200, To improve the driving capability of buffer circuit 200.
In addition, as shown in Figure 1B, buffer circuit 200 also optionally includes third switching circuit 243 and the 4th and opens Powered-down road 244.Third switching circuit 243 is coupled between the first output end OT3 and load Y2, to transmit the when switched on One output signal OUT2A is to loading Y2.4th switching circuit 244 be coupled in second output terminal OT4 and load Y1 between, to The second output signal OUT2B is transmitted when switched on to loading Y1.
More specifically, third switching circuit 243 may include earthing switch SW21 and transmission gate TG21.Earthing switch SW21 is coupled between the first output end OT3 and ground voltage terminal AGND.Transmission gate TG21 is coupled in the first output end OT3 and bears It carries between Y2, wherein earthing switch SW21 is opposite with the conducting off-state of transmission gate TG21.In addition, transmission gate TG21 includes P Transistor npn npn M71 and N-type transistor M72.The first end of P-type transistor M71 couples the first output end OT3, P-type transistor The second end coupling load Y2 of M71, and the control terminal of P-type transistor M71 receives the control voltage HPTB of reverse phase.N-type transistor The first end of M72 couples the first output end OT3, the second end coupling load Y2 of N-type transistor M72, and N-type transistor M72's Control terminal couples ground voltage terminal AGND.The running of earthing switch SW21 and transmission gate TG21 is similar to the earthing switch of Figure 1A The running of SW12 and transmission gate TG12, therefore above-mentioned related description can be considered in light of actual conditions and analogize and learn, details are not described herein.
Similarly, the 4th switching circuit 244 may include earthing switch SW22 and transmission gate TG22.Earthing switch SW22 coupling It connects between second output terminal OT4 and ground voltage terminal AGND.Transmission gate TG22 be coupled in second output terminal OT4 and load Y1 it Between, wherein earthing switch SW22 is opposite with the conducting off-state of transmission gate TG22.In addition, transmission gate TG22 includes P-type crystal Pipe M81 and N-type transistor M82.The first end of P-type transistor M81 couples second output terminal OT4, and the of P-type transistor M81 Two ends coupling load Y1, and the control terminal of P-type transistor M81 receives control voltage HPT.The first end of N-type transistor M82 couples The second end coupling load Y1 of second output terminal OT4, N-type transistor M82, and the control terminal coupling ground connection electricity of N-type transistor M82 Pressure side AGND.The running of earthing switch SW22 and transmission gate TG22 is similar to the earthing switch SW11 and transmission gate TG11 of Figure 1A Running, therefore above-mentioned related description can be considered in light of actual conditions, details are not described herein.
In addition to this, buffer circuit 200 also optionally includes basic voltage switching circuit (not shown).This substrate electricity It presses the framework of switching circuit and is functionally similar to the basic voltage switching circuit 145 of Figure 1A, therefore above-mentioned related description can be considered in light of actual conditions, Details are not described herein.
Please referring to merging below, A and Fig. 2A, Fig. 2A are according to Figure 1A embodiment shown by one embodiment of the invention referring to Fig.1 Operational amplifier circuit diagram.Operational amplifier 330 is defeated including front stage circuits 333, the first output stage 331 and second Grade 332 out.Front stage circuits 333 include the first differential pair 211_1A, the second differential pair 211_1B, the first current source 211_2A, the Two current source 211_2B, the first active load 213A, the second active load 213B, the first resistance being made of transistor N10, P10 Anti- provider, the second impedance provider being made of transistor N11, P11 and miller capacitance MCP, MCN.
First differential pair 211_1A and the second differential pair 211_1B forms the input stage of front stage circuits 333.First is differential It include the first differential pair formed by transistor N2A, N1A to 211_1A, wherein transistor N2A receives input signal VINP, and Transistor N1A receives feedback signal AVF1.Second differential pair 211_1B include formed by transistor P2A, P1A it is second differential Right, wherein transistor P2A receives input signal VINP, and transistor P1A receives feedback signal AVF1.First differential pair 211_1A And second the form of differential pair 211_1B be complementary.
First current source 211_2A includes transistor N3A and N4A.Transistor N4A receives positive bias voltage AVBN2H, brilliant Body pipe N3A receives positive bias voltage AVBN1H.First current source 211_2A is coupled in the first differential pair 211_1A and ground voltage It holds between AGND.Second current source 211_2B then includes transistor P4A and P3A.Transistor P4A receives positive bias voltage AVBP2H, transistor P3A receive positive bias voltage AVBP1H.Second current source 211_2B be coupled in the second differential pair 211_1B with Between positive voltage terminal PAVDD.In the present embodiment, the first current source 211_2A is complementary with the form of the second current source 211_2B.
First active load 213A is made of transistor P5-P8, and the second active load 213B is then by transistor N5-N8 institute It constitutes.First active load 213A is coupled between positive voltage terminal PAVDD and the first differential pair 211_1A.Second active load 213B is then coupled between ground voltage terminal AGND and the second differential pair 211_1B.First active load 213A and second is actively The form for loading 213B is complementary.Wherein, the first end of transistor P5, P6 is connected to positive voltage terminal PAVDD, the control of transistor P5, P6 End processed is mutually coupled and is coupled to the second end of transistor P7, and the second end of transistor P5, P6 are respectively coupled to transistor P7, P8 First end.In addition, the control terminal of transistor P7, P8 receive positive bias voltage AVBP4H jointly.The first end of transistor N5, N6 It is coupled to ground voltage terminal AGND, the control terminal of transistor N5, N6 are mutually coupled and are coupled to the first end of transistor N7, crystal The second end of pipe N5, N6 are respectively coupled to the second end of transistor N7, N8.In addition, the control terminal of transistor N7, N8 receive jointly Positive bias voltage AVBN4H.
It is actively negative that the first impedance provider being made of transistor N10, P10 is coupled in the first active load 213A and second It carries between 213B, it is main that the second impedance provider being made of transistor N11, P11 is coupled in the first active load 213A and second Between dynamic load 213B.Wherein, the second impedance provider that transistor N11, P11 is constituted is arranged in pairs or groups the first active load 213A and the Two active load 213B form the gain stage circuit of front stage circuits 333, and generating includes the first sub- amplified signal SP and second The amplified signal VAP (being shown in Figure 1A) of sub- amplified signal SN.
More specifically, transistor N10, P10 coupled in parallel transistor P7 second end and transistor N7 Between one end.The control terminal of transistor N10, P10 receive positive bias voltage AVBN3H and AVBP3H respectively.Transistor N11, P11 then coupled in parallel between the second end of transistor P8 and the first end of transistor N8.The control terminal of transistor N11, P11 Positive bias voltage AVBN5H and AVBP5H is received respectively.
First output stage 331 includes switching circuit 331_1 and output circuit 331_2.Switching circuit 331_1 couples prime Circuit 333, and according to selection signal SWA_P with first signal transmission channel that is turned on or off.Output circuit 331_2 coupling switch Circuit 331_1 receives the first sub- sub- amplified signal SN of amplified signal SP and second by above-mentioned first signal transmission channel, and The first output signal OUT1A is generated according to the first sub- sub- amplified signal SN of amplified signal SP and second.
Switching circuit 331_1 includes switch SW1A-SW5A.Wherein, switch SW1A, SW2A, SW3A is opened by transmission gate construction SW4A, SW5A are closed then respectively by transistor PSW1A and the construction of transistor NSW1A institute.Switch SW1A, SW2A are controlled by selection letter Number SWA_P and selection signal SWAB_P of reverse phase and be switched on or disconnect, and provide the first signal transmission passage to be respectively transmitted The first sub- sub- amplified signal SN to output circuit 331_2 of amplified signal SP and second.Switch SW3A is coupled in output circuit Between the output end of 331_2 and miller capacitance MCP, MCN of front stage circuits 333.Switch SW3A be controlled by selection signal SWA_P with The selection signal SWAB_P of reverse phase and be switched on or disconnect.Switch SW4A be coupled in the first input end of output circuit 331_2 with Between positive voltage terminal PAVDD, and according to selection signal SWA_P to be turned on or off.Switch SW5A is coupled in output circuit 331_2 The second input terminal and ground voltage terminal AGND between, and the selection signal SWAB_P according to reverse phase is to be turned on or off.
Switch SW4A, SW5A as drawing high switch and dragging down switch, are led respectively when switch SW1A, SW2A are disconnected It is logical, to provide the voltage of positive voltage terminal PAVDD and the voltage of ground voltage terminal AGND respectively to the first of output circuit 331_2 Input terminal and the second input terminal.Wherein, the conducting off-state of switch SW1A, SW2A, SW3A is identical, switch SW4A, SW5A's Conducting off-state is identical, and the conducting off-state of switch SW1A, SW4A are complementary (opposite), the conducting of switch SW2A, SW5A Off-state complementation (opposite).
Output circuit 331_2 includes transistor P9A and transistor N9A.Transistor P9A and transistor N9A connect respectively The collection of letters SPDA and SNDA.When switch SW1A, SW2A are switched on, signal SPDA and SNDA are respectively equal to the first son amplification The sub- amplified signal SN of signal SP and second, at this point, output circuit 331_2 generates the first output signal OUT1A to drive pixel. On the other hand, when switch SW1A, SW2A are disconnected, signal SPDA and SNDA are respectively equal to the electricity of positive voltage terminal PAVDD The voltage of pressure and ground voltage terminal AGND at this point, output circuit 331_2 stops generating the first output signal OUT1A, and makes the One output signal OUT1A is the state of high impedance.
Second output stage 332 includes switching circuit 332_1 and output circuit 332_2.Switching circuit 332_1 couples prime Circuit 333, and according to selection signal SWB_P with the second signal Transfer pipe that is turned on or off.Output circuit 332_2 coupling switch Circuit 332_1 receives the first sub- sub- amplified signal SN of amplified signal SP and second by above-mentioned second signal Transfer pipe, and The second output signal OUT1B is generated according to the first sub- sub- amplified signal SN of amplified signal SP and second.
Switching circuit 332_1 includes switch SW1B-SW5B.Wherein, switch SW1B, SW2B, SW3B is opened by transmission gate construction SW4B, SW5B are closed then respectively by transistor PSW1B and the construction of transistor NSW1B institute.Switch SW1B, SW2B are controlled by selection letter Number SWB_P and selection signal SWBB_P of reverse phase and be switched on or disconnect, and provide second signal transmission channel to be respectively transmitted The first sub- sub- amplified signal SN to output circuit 332_2 of amplified signal SP and second.Switch SW3B is coupled in output circuit Between the output end of 332_2 and miller capacitance MCP, MCN of front stage circuits 333.Switch SW3B be controlled by selection signal SWB_P with The selection signal SWBB_P of reverse phase and be switched on or disconnect.Switch SW4B be coupled in the first input end of output circuit 332_2 with Between positive voltage terminal PAVDD, and according to selection signal SWB_P to be turned on or off.Switch SW5B is coupled in output circuit 332_2 The second input terminal and ground voltage terminal AGND between, and the selection signal SWBB_P according to reverse phase is to be turned on or off.
Switch SW4B, SW5B as drawing high switch and dragging down switch, are led respectively when switch SW1B, SW2B are disconnected Logical, the first of the voltage of the voltage of offer positive voltage terminal PAVDD and ground voltage terminal AGND to output circuit 332_2 is defeated respectively Enter end and the second input terminal.Wherein, the conducting off-state of switch SW1B, SW2B, SW3B is identical, and switch SW4B, SW5B's leads On-off open state is identical, and the conducting off-state of switch SW1B, SW4B are complementary (opposite), and the conducting of switch SW2B, SW5B are disconnected Open state complementation (opposite).
Output circuit 332_2 includes transistor P9B and transistor N9B.Transistor P9B and transistor N9B connect respectively The collection of letters SPDB and SNDB.When switch SW1B, SW2B are switched on, signal SPDB and SNDB are respectively equal to the first son amplification The sub- amplified signal SN of signal SP and second, at this point, output circuit 332_2 generates the second output signal OUT1B to drive pixel. On the other hand, when switch SW1B, SW2B are disconnected, signal SPDB and SNDB are respectively equal to the electricity of positive voltage terminal PAVDD The voltage of pressure and ground voltage terminal AGND at this point, output circuit 332_2 stops generating the second output signal OUT1B, and makes the Two output signal OUT1B are the state of high impedance.
It is noted that the conducting off-state of switch SW1B, SW2B, SW3B and leading for switch SW1A, SW2A, SW3A On-off open state is complementary (opposite).In other words, when output circuit 332_2 generates the second output signal OUT1B to drive pixel When, output circuit 332_1 stops generating the first output signal OUT1A, and makes the shape of the first output signal OUT1A high impedance State, vice versa.
B, Fig. 2 B are the operational amplifiers according to Figure 1B embodiment shown by one embodiment of the invention referring to figure 2. below Circuit diagram.Operational amplifier 430 includes front stage circuits 433, the first output stage 431 and the second output stage 432.First is defeated Grade 431 includes switching circuit 431_1 and output circuit 431_2 out.Second output stage 432 include switching circuit 432_1 and Output circuit 432_2.
The operational amplifier 430 of Fig. 2 B is similar to the operational amplifier 330 of Fig. 2A, and the difference of the two is only that operation is put Big device 330 is coupled between positive voltage terminal PAVDD and ground voltage terminal AGND, that is, operational amplifier 330 is to be embodied in positive electricity Source domain (positive power domain), and operational amplifier 430 is then coupled in negative voltage side NAVDD and ground voltage It holds between AGND, that is, operational amplifier 430 is to be embodied in negative electricity source domain (negative power domain).Therefore preceding In grade circuit 433, transistor N4A receives back bias voltage voltage AVBN2L, and transistor N3A receives back bias voltage voltage AVBN1L, crystal Pipe P4A receives back bias voltage voltage AVBP2H, and transistor P3A receives back bias voltage voltage AVBP1H, and the control terminal of transistor P7, P8 are total With reception back bias voltage voltage AVBP4H, and the control terminal of transistor N7, N8 receive back bias voltage voltage AVBN4H jointly.Except this it Outside, compared to selection signal SWA_P, SWB_P and reverse phase in switching circuit 331_1 and 332_1 selection signal SWAB_P, SWBB_P is positive signal, the selection letter of selection signal SWA_N, SWB_N and reverse phase in switching circuit 431_1 and 432_1 Number SWAB_N, SWBB_N are minus polarity signal.The implementation detail and running of operational amplifier 430 about Fig. 2 B, can consider in light of actual conditions on It states the related description of Fig. 2A and analogizes and learn, details are not described herein.
Fig. 3 A is the circuit diagram according to buffer circuit shown by further embodiment of this invention.A referring to figure 3..It is slow Rush circuit 500 may include first switch circuit 110, second switch circuit 120, operational amplifier 530, third switching circuit 143, 4th switching circuit 144 and basic voltage switching circuit 145, however, the present invention is not limited thereto.The first switch circuit of Fig. 3 A 110, second switch circuit 120, third switching circuit 143, the 4th switching circuit 144 and basic voltage switching circuit 145 are divided Not Lei Siyu Figure 1A first switch circuit 110, second switch circuit 120, third switching circuit 143, the 4th switching circuit 144 And basic voltage switching circuit 145, therefore the related description of above-mentioned Figure 1A can be considered in light of actual conditions, details are not described herein.
The operational amplifier 530 of Fig. 3 A is similar to the operational amplifier 130 of Figure 1A, and the difference of the two is, operation amplifier Device 530 further includes feedback output grade 534.Feedback output grade 534 is coupled between front stage circuits 133 and the second input terminal IT2, is used To generate third output signal using as feedback signal AVF1 according to amplified signal VAP.In the embodiment as shown in fig. 3 a, due to Feedback signal AVF1 can be provided to the second input terminal IT2 by feedback output grade 534, therefore first switch circuit 110 and second switch Circuit 120 can be all disconnected, and the first output stage 131 and the second output stage 132 can be all disabled, and cause the first output end OT1 It is all high impedance status with second output terminal OT2, to can realize that buffer circuit 500 provides the application of high impedance output.As for Other implementation details and running of the operational amplifier 530 of Fig. 3 A, can consider mutually speaking on somebody's behalf for the operational amplifier 130 of above-mentioned Figure 1A in light of actual conditions Bright, details are not described herein.
Fig. 3 B is the circuit diagram according to buffer circuit shown by further embodiment of this invention.B referring to figure 3..It is slow Rushing circuit 600 may include first switch circuit 210, second switch circuit 220, operational amplifier 630, third switching circuit 243 And the 4th switching circuit 244, however, the present invention is not limited thereto.First switch circuit 210, the second switch circuit 220, of Fig. 3 B Three switching circuits 243 and the 4th switching circuit 244 are analogous respectively to the first switch circuit 210 of Figure 1B, second switch circuit 220, third switching circuit 243 and the 4th switching circuit 244, therefore the related description of above-mentioned Figure 1B can be considered in light of actual conditions, it is no longer superfluous herein It states.
The operational amplifier 630 of Fig. 3 B is similar to the operational amplifier 230 of Figure 1B, and the difference of the two is, operation amplifier Device 630 further includes feedback output grade 634.Feedback output grade 634 is coupled between front stage circuits 233 and the second input terminal IT4, is used To generate third output signal using as feedback signal AVF2 according to amplified signal VAN.In the embodiment shown in figure 3b, due to Feedback signal AVF2 can be provided to the second input terminal IT4 by feedback output grade 634, therefore first switch circuit 210 and second switch Circuit 220 can be all disconnected, and the first output stage 231 and the second output stage 232 can be all disabled, and cause the first output end OT3 It is all high impedance status with second output terminal OT4, to can realize that buffer circuit 600 provides the application of high impedance output.As for Other implementation details and running of the operational amplifier 630 of Fig. 3 B, can consider mutually speaking on somebody's behalf for the operational amplifier 230 of above-mentioned Figure 1B in light of actual conditions Bright, details are not described herein.
A, Fig. 4 A are the operational amplifiers according to Fig. 3 A embodiment shown by one embodiment of the invention referring to figure 4. below Circuit diagram.Operational amplifier 730 includes that front stage circuits 733, the first output stage 731, the second output stage 732 and feedback are defeated Grade 734 out.Front stage circuits 733 are similar to the front stage circuits 333 of Fig. 2A, therefore can consider the related description of above-mentioned Fig. 2A in light of actual conditions, herein not It repeats again.
First output stage 731 includes switching circuit 731_1 and output circuit 731_2.Output circuit 731_2 is similar to figure The output circuit 331_2 of 2A, therefore the related description of above-mentioned Fig. 2A can be considered in light of actual conditions, details are not described herein.In addition, opening compared to Fig. 2A Powered-down road 331_1 includes switch SW1A-SW5A, and switching circuit 731_1 only includes switch SW1A, SW2A, SW4A and SW5A, The coupling mode of switch SW1A, SW2A, SW4A and SW5A of middle Fig. 4 A and running are analogous respectively to the switching circuit of Fig. 2A Switch SW1A, SW2A, SW4A and SW5A of 331_1, therefore the related description of above-mentioned Fig. 2A can be considered in light of actual conditions, details are not described herein.
Second output stage 732 includes switching circuit 732_1 and output circuit 732_2.Output circuit 732_2 is similar to figure The output circuit 332_2 of 2A, therefore the related description of above-mentioned Fig. 2A can be considered in light of actual conditions, details are not described herein.In addition, opening compared to Fig. 2A Powered-down road 332_1 includes switch SW1B-SW5B, and switching circuit 732_1 only includes switch SW1B, SW2B, SW4B and SW5B, The coupling mode of switch SW1B, SW2B, SW4B and SW5B of middle Fig. 4 A and running are analogous respectively to the switching circuit of Fig. 2A Switch SW1B, SW2B, SW4B and SW5B of 332_1, therefore the related description of above-mentioned Fig. 2A can be considered in light of actual conditions, details are not described herein.
Feedback output grade 734 includes transistor P9 and N9.The first end of transistor P9 is coupled to positive voltage terminal PAVDD.It is brilliant The second end coupling miller capacitance MCP and MCN of body pipe P9 simultaneously generates third output signal as feedback signal AVF1.Transistor The control terminal of P9 receives the first sub- amplified signal SP.The first end coupling miller capacitance MCP and MCN of transistor N9 simultaneously generates third Output signal is as feedback signal AVF1.The second end of transistor N9 is coupled to ground voltage terminal AGND.The control of transistor N9 End processed receives the second sub- amplified signal SN.
The feedback signal AVF1 as caused by the feedback output grade 734 of Fig. 4 A is provided to the first differential pair 211_1A's The control terminal of the transistor P1A of the control terminal of transistor N1A and the second differential pair 211_1B and form negative feedback loop, so In the case where the first output stage 731 and the second output stage 732 are all disabled, operational amplifier 730 still can normal operation.So One, the first output stage 731 and the second output stage 732 can be all disabled, and caused the first output signal OUT1A and second to export and believed Number OUT1B is all high impedance status, provides the application of high impedance output to can realize.
B, Fig. 4 B are the operational amplifiers according to Fig. 3 B embodiment shown by one embodiment of the invention referring to figure 4. below Circuit diagram.Operational amplifier 830 includes that front stage circuits 833, the first output stage 831, the second output stage 832 and feedback are defeated Grade 834 out.Front stage circuits 833 are similar to the front stage circuits 433 of Fig. 2 B, therefore can consider the related description of above-mentioned Fig. 2 B in light of actual conditions, herein not It repeats again.
First output stage 831 includes switching circuit 831_1 and output circuit 831_2.Output circuit 831_2 is similar to figure The output circuit 431_2 of 2B, therefore the related description of above-mentioned Fig. 2 B can be considered in light of actual conditions, details are not described herein.In addition, opening compared to Fig. 2 B Powered-down road 431_1 includes switch SW1A-SW5A, and switching circuit 831_1 only includes switch SW1A, SW2A, SW4A and SW5A, The coupling mode of switch SW1A, SW2A, SW4A and SW5A of middle Fig. 4 B and running are analogous respectively to the switching circuit of Fig. 2 B Switch SW1A, SW2A, SW4A and SW5A of 431_1, therefore the related description of above-mentioned Fig. 2 B can be considered in light of actual conditions, details are not described herein.
Second output stage 832 includes switching circuit 832_1 and output circuit 832_2.Output circuit 832_2 is similar to figure The output circuit 432_2 of 2B, therefore the related description of above-mentioned Fig. 2 B can be considered in light of actual conditions, details are not described herein.In addition, opening compared to Fig. 2 B Powered-down road 432_1 includes switch SW1B-SW5B, and switching circuit 832_1 only includes switch SW1B, SW2B, SW4B and SW5B, The coupling mode of switch SW1B, SW2B, SW4B and SW5B of middle Fig. 4 B and running are analogous respectively to the switching circuit of Fig. 2 B Switch SW1B, SW2B, SW4B and SW5B of 432_1, therefore the related description of above-mentioned Fig. 2 B can be considered in light of actual conditions, details are not described herein.
Feedback output grade 834 includes transistor P9 and N9.The first end of transistor P9 is coupled to ground voltage terminal AGND.It is brilliant The second end coupling miller capacitance MCP and MCN of body pipe P9 simultaneously generates third output signal as feedback signal AVF2.Transistor The control terminal of P9 receives the first sub- amplified signal SP.The first end coupling miller capacitance MCP and MCN of transistor N9 simultaneously generates third Output signal is as feedback signal AVF2.The second end of transistor N9 is coupled to negative voltage side NAVDD.The control of transistor N9 End receives the second sub- amplified signal SN.
The feedback signal AVF2 as caused by the feedback output grade 834 of Fig. 4 B is provided to the first differential pair 211_1A's The control terminal of the transistor P1A of the control terminal of transistor N1A and the second differential pair 211_1B and form negative feedback loop, so In the case where the first output stage 831 and the second output stage 832 are all disabled, operational amplifier 830 still can normal operation.So One, the first output stage 831 and the second output stage 832 can be all disabled, and caused the first output signal OUT2A and second to export and believed Number OUT2B is all high impedance status, provides the application of high impedance output to can realize.
In conclusion the first output stage of operational amplifier is only used in the buffer circuit that the embodiment of the present invention is proposed Drive a load, and the second output stage of operational amplifier is only used to drive another load, therefore compared to existing buffering electricity Road is the design for alternately driving different loads by switching transmission gate by same output stage, the operational amplifier of the present embodiment Setting can be omitted between load to switch the polar transmission gate of driving voltage, can not only reduce the circuit face of buffer circuit Product, can also effectively improve the revolution rate of the output signal of buffer circuit, to improve the driving capability of buffer circuit.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection of the invention Subject to range ought be defined depending on claim.

Claims (16)

1.一种缓冲电路，其特征在于，包括：1. A buffer circuit, characterized in that, comprising: 运算放大器，具有第一输入端、第二输入端、第一输出端以及第二输出端，其中所述运算放大器包括：An operational amplifier having a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the operational amplifier includes: 前级电路，耦接所述第一输入端以接收输入信号，耦接所述第二输入端以接收反馈信号，并据以产生放大信号；a pre-stage circuit, coupled to the first input terminal to receive an input signal, coupled to the second input terminal to receive a feedback signal, and to generate an amplified signal accordingly; 第一输出级，耦接在所述前级电路与所述第一输出端之间，用以依据所述放大信号产生第一输出信号以驱动第一负载；以及a first output stage, coupled between the pre-stage circuit and the first output terminal, for generating a first output signal according to the amplified signal to drive a first load; and 第二输出级，耦接在所述前级电路与所述第二输出端之间，用以依据所述放大信号产生第二输出信号以驱动第二负载，其中所述第二输出信号的极性与所述第一输出信号的极性相同；A second output stage, coupled between the pre-stage circuit and the second output terminal, is used for generating a second output signal according to the amplified signal to drive a second load, wherein the pole of the second output signal The polarity is the same as the polarity of the first output signal; 第一开关电路，耦接在所述第一输出端与所述第二输入端之间，用以在被导通时传输所述第一输出信号至所述第二输入端以作为所述反馈信号；以及a first switch circuit, coupled between the first output terminal and the second input terminal, for transmitting the first output signal to the second input terminal as the feedback when turned on signal; and 第二开关电路，耦接在所述第二输出端与所述第二输入端之间，用以在被导通时传输所述第二输出信号至所述第二输入端以作为所述反馈信号；A second switch circuit, coupled between the second output terminal and the second input terminal, is used for transmitting the second output signal to the second input terminal as the feedback when turned on Signal; 其中当所述第一开关电路被导通，且所述第一输出级产生所述第一输出信号以驱动所述第一负载时，所述第二开关电路被断开，且所述第二输出级被禁能；以及，当所述第二开关电路被导通，且所述第二输出级产生所述第二输出信号以驱动所述第二负载时，所述第一开关电路被断开，且所述第一输出级被禁能，两者至少其中之一。When the first switch circuit is turned on and the first output stage generates the first output signal to drive the first load, the second switch circuit is turned off, and the second the output stage is disabled; and when the second switch circuit is turned on and the second output stage generates the second output signal to drive the second load, the first switch circuit is turned off on, and the first output stage is disabled, at least one of the two. 2.根据权利要求1所述的缓冲电路，其特征在于，2. The buffer circuit according to claim 1, characterized in that, 所述第一输出级包括：The first output stage includes: 第三开关电路，耦接所述前级电路，且依据第一选择信号以导通或断开第一信号传送通道；以及a third switch circuit, coupled to the previous stage circuit, and turns on or off the first signal transmission channel according to the first selection signal; and 第一输出电路，耦接所述第三开关电路，通过所述第一信号传送通道接收所述放大信号，并依据所述放大信号产生所述第一输出信号，a first output circuit, coupled to the third switch circuit, receives the amplified signal through the first signal transmission channel, and generates the first output signal according to the amplified signal, 所述第二输出级包括：The second output stage includes: 第四开关电路，耦接所述前级电路，且依据第二选择信号以导通或断开第二信号传送通道；以及a fourth switch circuit, coupled to the previous stage circuit, and turns on or off the second signal transmission channel according to the second selection signal; and 第二输出电路，耦接所述第四开关电路，通过所述第二信号传送通道接收所述放大信号，并依据所述放大信号产生所述第二输出信号。The second output circuit is coupled to the fourth switch circuit, receives the amplified signal through the second signal transmission channel, and generates the second output signal according to the amplified signal. 3.根据权利要求2所述的缓冲电路，其特征在于，所述第三开关电路包括：3. The buffer circuit according to claim 2, wherein the third switch circuit comprises: 第一开关，接收所述放大信号中的第一子放大信号，受控于所述第一选择信号，并在所述第一开关导通时传送所述第一子放大信号至所述第一输出电路；a first switch, receiving a first sub-amplified signal in the amplified signal, controlled by the first selection signal, and transmitting the first sub-amplified signal to the first switch when the first switch is turned on output circuit; 第二开关，接收所述放大信号中的第二子放大信号，受控于所述第一选择信号，并在所述第二开关导通时传送所述第二子放大信号至所述第一输出电路；以及The second switch receives the second sub-amplified signal in the amplified signal, is controlled by the first selection signal, and transmits the second sub-amplified signal to the first when the second switch is turned on output circuit; and 第三开关，耦接在所述第一输出电路的输出端与所述前级电路的米勒电容之间，且依据所述第一选择信号以导通或断开，The third switch is coupled between the output end of the first output circuit and the Miller capacitor of the preceding circuit, and is turned on or off according to the first selection signal, 其中所述第一开关、所述第二开关与所述第三开关的导通断开状态相同。The on-off states of the first switch, the second switch and the third switch are the same. 4.根据权利要求3所述的缓冲电路，其特征在于，所述第三开关电路还包括：4. The buffer circuit according to claim 3, wherein the third switch circuit further comprises: 第四开关，耦接在所述第一输出电路的第一输入端与第一电压端之间，且依据所述第一选择信号以导通或断开；以及a fourth switch, coupled between the first input terminal of the first output circuit and the first voltage terminal, and turned on or off according to the first selection signal; and 第五开关，耦接在所述第一输出电路的第二输入端与第二电压端之间，且依据所述第一选择信号以导通或断开，a fifth switch, coupled between the second input terminal of the first output circuit and the second voltage terminal, and turned on or off according to the first selection signal, 其中所述第四开关与所述第五开关的导通断开状态相同，所述第四开关与所述第一开关的导通断开状态相反，所述第五开关与所述第二开关的导通断开状态相反，The on-off states of the fourth switch and the fifth switch are the same, the on-off states of the fourth switch and the first switch are opposite, and the fifth switch and the second switch The on-off state is opposite, 其中所述第一电压端为正电压端，且所述第二电压端为接地电压端；或者是，所述第一电压端为接地电压端，且所述第二电压端为负电压端。The first voltage terminal is a positive voltage terminal, and the second voltage terminal is a ground voltage terminal; or, the first voltage terminal is a ground voltage terminal, and the second voltage terminal is a negative voltage terminal. 5.根据权利要求2所述的缓冲电路，其特征在于，所述第四开关电路包括：5. The buffer circuit according to claim 2, wherein the fourth switch circuit comprises: 第一开关，接收所述放大信号中的第一子放大信号，受控于所述第二选择信号，并在所述第一开关导通时传送所述第一子放大信号至所述第二输出电路；The first switch receives the first sub-amplified signal in the amplified signal, is controlled by the second selection signal, and transmits the first sub-amplified signal to the second when the first switch is turned on output circuit; 第二开关，接收所述放大信号中的第二子放大信号，受控于所述第二选择信号，并在所述第二开关导通时传送所述第二子放大信号至所述第二输出电路；以及The second switch receives the second sub-amplified signal in the amplified signal, is controlled by the second selection signal, and transmits the second sub-amplified signal to the second switch when the second switch is turned on output circuit; and 第三开关，耦接在所述第二输出电路的输出端与所述前级电路的米勒电容之间，且依据所述第二选择信号以导通或断开，The third switch is coupled between the output end of the second output circuit and the Miller capacitor of the preceding circuit, and is turned on or off according to the second selection signal, 其中，所述第一开关、所述第二开关与所述第三开关的导通断开状态相同。Wherein, the on-off states of the first switch, the second switch and the third switch are the same. 6.根据权利要求5所述的缓冲电路，其特征在于，所述第四开关电路还包括：6. The buffer circuit according to claim 5, wherein the fourth switch circuit further comprises: 第四开关，耦接在所述第二输出电路的第一输入端与第一电压端之间，且依据所述第二选择信号以导通或断开；以及a fourth switch, coupled between the first input terminal of the second output circuit and the first voltage terminal, and turned on or off according to the second selection signal; and 第五开关，耦接在所述第二输出电路的第二输入端与第二电压端之间，且依据所述第二选择信号以导通或断开，a fifth switch, coupled between the second input terminal of the second output circuit and the second voltage terminal, and turned on or off according to the second selection signal, 其中所述第四开关与所述第五开关的导通断开状态相同，所述第四开关与所述第一开关的导通断开状态相反，所述第五开关与所述第二开关的导通断开状态相反，The on-off states of the fourth switch and the fifth switch are the same, the on-off states of the fourth switch and the first switch are opposite, and the fifth switch and the second switch The on-off state is opposite, 其中所述第一电压端为正电压端，且所述第二电压端为接地电压端；或者是，所述第一电压端为接地电压端，且所述第二电压端为负电压端。The first voltage terminal is a positive voltage terminal, and the second voltage terminal is a ground voltage terminal; or, the first voltage terminal is a ground voltage terminal, and the second voltage terminal is a negative voltage terminal. 7.根据权利要求2所述的缓冲电路，其特征在于，所述运算放大器还包括：7. The buffer circuit of claim 2, wherein the operational amplifier further comprises: 反馈输出级，耦接在所述前级电路与所述第二输入端之间，用以依据所述放大信号产生第三输出信号以作为所述反馈信号。The feedback output stage is coupled between the pre-stage circuit and the second input terminal, and is used for generating a third output signal as the feedback signal according to the amplified signal. 8.根据权利要求7所述的缓冲电路，其特征在于，所述反馈输出级包括：8. The buffer circuit of claim 7, wherein the feedback output stage comprises: 第一晶体管，所述第一晶体管的第一端耦接至第一电压端，所述第一晶体管的第二端耦接所述前级电路的米勒电容并产生所述第三输出信号，且所述第一晶体管的控制端接收所述放大信号中的第一子放大信号；以及a first transistor, a first end of the first transistor is coupled to a first voltage end, a second end of the first transistor is coupled to the Miller capacitor of the pre-stage circuit and generates the third output signal, and the control terminal of the first transistor receives the first sub-amplified signal in the amplified signal; and 第二晶体管，所述第二晶体管的第一端耦接所述米勒电容并产生所述第三输出信号，所述第二晶体管的第二端耦接至第二电压端，且所述第二晶体管的控制端接收所述放大信号中的第二子放大信号，a second transistor, a first end of the second transistor is coupled to the Miller capacitor and generates the third output signal, a second end of the second transistor is coupled to a second voltage end, and the first The control terminal of the two transistors receives the second sub-amplified signal in the amplified signal, 其中所述第一电压端为正电压端，且所述第二电压端为接地电压端；或者是，所述第一电压端为接地电压端，且所述第二电压端为负电压端。The first voltage terminal is a positive voltage terminal, and the second voltage terminal is a ground voltage terminal; or, the first voltage terminal is a ground voltage terminal, and the second voltage terminal is a negative voltage terminal. 9.根据权利要求8所述的缓冲电路，其特征在于，所述第三开关电路包括：9. The buffer circuit according to claim 8, wherein the third switch circuit comprises: 第一开关，接收所述第一子放大信号，受控于所述第一选择信号，并在所述第一开关导通时传送所述第一子放大信号至所述第一输出电路；以及a first switch, receiving the first sub-amplification signal, controlled by the first selection signal, and transmitting the first sub-amplification signal to the first output circuit when the first switch is turned on; and 第二开关，接收所述放大信号中的第二子放大信号，受控于所述第一选择信号，并在所述第二开关导通时传送所述第二子放大信号至所述第一输出电路；The second switch receives the second sub-amplified signal in the amplified signal, is controlled by the first selection signal, and transmits the second sub-amplified signal to the first when the second switch is turned on output circuit; 其中所述第一开关与所述第二开关的导通断开状态相同。The on-off states of the first switch and the second switch are the same. 10.根据权利要求9所述的缓冲电路，其特征在于，所述第三开关电路还包括：10. The buffer circuit according to claim 9, wherein the third switch circuit further comprises: 第三开关，耦接在所述第一输出电路的第一输入端与所述第一电压端之间，且依据所述第一选择信号以导通或断开；以及a third switch, coupled between the first input terminal of the first output circuit and the first voltage terminal, and turned on or off according to the first selection signal; and 第四开关，耦接在所述第一输出电路的第二输入端与所述第二电压端之间，且依据所述第一选择信号以导通或断开，a fourth switch, coupled between the second input terminal of the first output circuit and the second voltage terminal, and turned on or off according to the first selection signal, 其中所述第三开关与所述第四开关的导通断开状态相同，所述第三开关与所述第一开关的导通断开状态相反，所述第四开关与所述第二开关的导通断开状态相反。The on-off states of the third switch and the fourth switch are the same, the on-off states of the third switch and the first switch are opposite, and the fourth switch and the second switch The on-off state is opposite. 11.根据权利要求8所述的缓冲电路，其特征在于，所述第四开关电路包括：11. The buffer circuit of claim 8, wherein the fourth switch circuit comprises: 第一开关，接收所述第一子放大信号，受控于所述第二选择信号，并在所述第一开关导通时传送所述第一子放大信号至所述第二输出电路；以及a first switch, receiving the first sub-amplification signal, controlled by the second selection signal, and transmitting the first sub-amplification signal to the second output circuit when the first switch is turned on; and 第二开关，接收所述第二子放大信号，受控于所述第二选择信号，并在所述第二开关导通时传送所述第二子放大信号至所述第二输出电路，The second switch receives the second sub-amplification signal, is controlled by the second selection signal, and transmits the second sub-amplification signal to the second output circuit when the second switch is turned on, 其中，所述第一开关与所述第二开关的导通断开状态相同。Wherein, the on-off states of the first switch and the second switch are the same. 12.根据权利要求11所述的缓冲电路，其特征在于，所述第四开关电路还包括：12. The buffer circuit according to claim 11, wherein the fourth switch circuit further comprises: 第三开关，耦接在所述第二输出电路的第一输入端与所述第一电压端之间，且依据所述第二选择信号以导通或断开；以及a third switch, coupled between the first input terminal of the second output circuit and the first voltage terminal, and turned on or off according to the second selection signal; and 第四开关，耦接在所述第二输出电路的第二输入端与所述第二电压端之间，且依据所述第二选择信号以导通或断开，a fourth switch, coupled between the second input terminal of the second output circuit and the second voltage terminal, and turned on or off according to the second selection signal, 其中所述第三开关与所述第四开关的导通断开状态相同，所述第三开关与所述第一开关的导通断开状态相反，所述第四开关与所述第二开关的导通断开状态相反。The on-off states of the third switch and the fourth switch are the same, the on-off states of the third switch and the first switch are opposite, and the fourth switch and the second switch The on-off state is opposite. 13.根据权利要求1所述的缓冲电路，其特征在于，还包括：13. The buffer circuit of claim 1, further comprising: 第三开关电路，耦接在所述第一输出端与所述第一负载之间，用以在被导通时传输所述第一输出信号至所述第一负载；以及a third switch circuit, coupled between the first output terminal and the first load, for transmitting the first output signal to the first load when turned on; and 第四开关电路，耦接在所述第二输出端与所述第二负载之间，用以在被导通时传输所述第二输出信号至所述第二负载。A fourth switch circuit, coupled between the second output terminal and the second load, is used for transmitting the second output signal to the second load when turned on. 14.根据权利要求13所述的缓冲电路，其特征在于，14. The buffer circuit according to claim 13, wherein, 所述第三开关电路包括：The third switch circuit includes: 第一接地开关，耦接在所述第一输出端与接地电压端之间；以及a first ground switch, coupled between the first output terminal and the ground voltage terminal; and 第一传输门，耦接在所述第一输出端与所述第一负载之间，其中所述第一接地开关与所述第一传输门的导通断开状态相反，a first transmission gate, coupled between the first output terminal and the first load, wherein the on-off states of the first ground switch and the first transmission gate are opposite, 所述第四开关电路包括：The fourth switch circuit includes: 第二接地开关，耦接在所述第二输出端与所述接地电压端之间；以及a second ground switch, coupled between the second output terminal and the ground voltage terminal; and 第二传输门，耦接在所述第二输出端与所述第二负载之间，其中所述第二接地开关与所述第二传输门的导通断开状态相反。A second transmission gate is coupled between the second output terminal and the second load, wherein the on-off state of the second ground switch is opposite to that of the second transmission gate. 15.根据权利要求14所述的缓冲电路，其特征在于：15. The buffer circuit of claim 14, wherein: 所述第一传输门包括：The first transmission gate includes: 第一P型晶体管，所述第一P型晶体管的第一端耦接所述第一输出端，所述第一P型晶体管的第二端耦接所述第一负载，且所述第一P型晶体管的控制端耦接所述接地电压端；以及a first P-type transistor, a first end of the first P-type transistor is coupled to the first output end, a second end of the first P-type transistor is coupled to the first load, and the first The control terminal of the P-type transistor is coupled to the ground voltage terminal; and 第一N型晶体管，所述第一N型晶体管的第一端耦接所述第一输出端，所述第一N型晶体管的第二端耦接所述第一负载，且所述第一N型晶体管的控制端接收控制电压，a first N-type transistor, a first end of the first N-type transistor is coupled to the first output end, a second end of the first N-type transistor is coupled to the first load, and the first The control terminal of the N-type transistor receives the control voltage, 所述第二传输门包括：The second transmission gate includes: 第二P型晶体管，所述第二P型晶体管的第一端耦接所述第二输出端，所述第二P型晶体管的第二端耦接所述第二负载，且所述第二P型晶体管的控制端耦接所述接地电压端；以及A second P-type transistor, the first end of the second P-type transistor is coupled to the second output end, the second end of the second P-type transistor is coupled to the second load, and the second The control terminal of the P-type transistor is coupled to the ground voltage terminal; and 第二N型晶体管，所述第二N型晶体管的第一端耦接所述第二输出端，所述第二N型晶体管的第二端耦接所述第二负载，且所述第二N型晶体管的控制端接收反相的所述控制电压。A second N-type transistor, the first end of the second N-type transistor is coupled to the second output end, the second end of the second N-type transistor is coupled to the second load, and the second The control terminal of the N-type transistor receives the inverted control voltage. 16.根据权利要求15所述的缓冲电路，其特征在于，还包括：16. The buffer circuit of claim 15, further comprising: 基底电压切换电路，包括：Base voltage switching circuit, including: 第三P型晶体管，所述第三P型晶体管的第一端耦接正电压端，所述第三P型晶体管的控制端接收第一切换信号，且第三P型晶体管的第二端提供所述第一P型晶体管的基底电压；The third P-type transistor, the first terminal of the third P-type transistor is coupled to the positive voltage terminal, the control terminal of the third P-type transistor receives the first switching signal, and the second terminal of the third P-type transistor provides the substrate voltage of the first P-type transistor; 第三N型晶体管，所述第三N型晶体管的第一端耦接所述接地电压端，所述第三N型晶体管的控制端接收第二切换信号，且第三N型晶体管的第二端提供所述第一P型晶体管的所述基底电压；A third N-type transistor, the first terminal of the third N-type transistor is coupled to the ground voltage terminal, the control terminal of the third N-type transistor receives the second switching signal, and the second switching signal of the third N-type transistor is A terminal provides the substrate voltage of the first P-type transistor; 第四P型晶体管，所述第四P型晶体管的第一端耦接所述接地电压端，所述第四P型晶体管的控制端接收第三切换信号，且第四P型晶体管的第二端提供所述第一N型晶体管的基底电压；a fourth P-type transistor, the first terminal of the fourth P-type transistor is coupled to the ground voltage terminal, the control terminal of the fourth P-type transistor receives the third switching signal, and the second The terminal provides the substrate voltage of the first N-type transistor; 第四N型晶体管，所述第四N型晶体管的第一端耦接负电压端，所述第四N型晶体管的控制端接收第四切换信号，且第四N型晶体管的第二端提供所述第一N型晶体管的所述基底电压；a fourth N-type transistor, the first terminal of the fourth N-type transistor is coupled to the negative voltage terminal, the control terminal of the fourth N-type transistor receives the fourth switching signal, and the second terminal of the fourth N-type transistor provides the substrate voltage of the first N-type transistor; 第五P型晶体管，所述第五P型晶体管的第一端耦接所述正电压端，所述第五P型晶体管的控制端接收第五切换信号，且第五P型晶体管的第二端提供所述第二P型晶体管的基底电压；a fifth P-type transistor, the first terminal of the fifth P-type transistor is coupled to the positive voltage terminal, the control terminal of the fifth P-type transistor receives a fifth switching signal, and the second terminal of the fifth P-type transistor The terminal provides the substrate voltage of the second P-type transistor; 第五N型晶体管，所述第五N型晶体管的第一端耦接所述接地电压端，所述第五N型晶体管的控制端接收第六切换信号，且第五N型晶体管的第二端提供所述第二P型晶体管的所述基底电压；a fifth N-type transistor, the first terminal of the fifth N-type transistor is coupled to the ground voltage terminal, the control terminal of the fifth N-type transistor receives the sixth switching signal, and the second terminal of the fifth N-type transistor A terminal provides the substrate voltage of the second P-type transistor; 第六P型晶体管，所述第六P型晶体管的第一端耦接所述接地电压端，所述第六P型晶体管的控制端接收第七切换信号，且第六P型晶体管的第二端提供所述第二N型晶体管的基底电压；以及a sixth P-type transistor, the first terminal of the sixth P-type transistor is coupled to the ground voltage terminal, the control terminal of the sixth P-type transistor receives the seventh switching signal, and the second terminal provides the substrate voltage of the second N-type transistor; and 第六N型晶体管，所述第六N型晶体管的第一端耦接所述负电压端，所述第六N型晶体管的控制端接收第八切换信号，且第六N型晶体管的第二端提供所述第二N型晶体管的所述基底电压。a sixth N-type transistor, the first terminal of the sixth N-type transistor is coupled to the negative voltage terminal, the control terminal of the sixth N-type transistor receives the eighth switching signal, and the second A terminal provides the substrate voltage of the second N-type transistor.
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