CN210927601U - Driving device and amplifier circuit with voltage interpolation function - Google Patents
Driving device and amplifier circuit with voltage interpolation function Download PDFInfo
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- CN210927601U CN210927601U CN202020127986.XU CN202020127986U CN210927601U CN 210927601 U CN210927601 U CN 210927601U CN 202020127986 U CN202020127986 U CN 202020127986U CN 210927601 U CN210927601 U CN 210927601U
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Abstract
The utility model discloses a drive arrangement and amplifier circuit of utensil voltage interpolation function, this amplifier circuit include that plural number input is right for receive a first voltage and a second voltage, the plural number input is coupled in a voltage output end through an output stage in addition, the plural number input includes to at least: a first input pair coupled between a ground and a pair of nodes, comprising at least a first pair of transistors sized to correspond to a first ratio; and a second input pair coupled between the ground point and the pair of nodes, including at least a second pair of transistors having a size corresponding to a second ratio, wherein the second ratio is not equal to the first ratio, the second ratio is a multiple of the first ratio, and a voltage output by the voltage output terminal is an interpolation result of the first voltage and the second voltage weighted by the first ratio and the second ratio. The driving device comprises the amplifier circuit.
Description
Technical Field
The utility model relates to an amplifier circuit of utensil voltage interpolation function to and contain a drive arrangement of this amplifier circuit.
Background
With the increase of the size and resolution of the liquid crystal panel, the area occupied by the display driving chip during layout is also increasing. Among them, the 6-bit digital-to-analog converter is a design with better chip area utilization rate generally recognized at present. However, the 6-bit image resolution has not been able to meet the image resolution requirement of the larger-sized liquid crystal panel. For example, the image resolution requirement of the large-sized liquid crystal panel has reached 10 bits nowadays. If the 6-bit digital-to-analog converter is upgraded to a 10-bit digital-to-analog converter to meet the requirement of at least 10-bit image resolution, the digital-to-analog converter occupies a significant circuit area, so that the chip area utilization rate is greatly reduced.
Therefore, it is an important issue in the industry to reduce the chip area and the production cost while increasing the image resolution.
SUMMERY OF THE UTILITY MODEL
An object of the present invention is to provide an amplifier circuit with voltage interpolation function for effectively reducing chip area and simultaneously improving image resolution.
Another object of the present invention is to provide a driving device for a liquid crystal display, which is used to effectively reduce the chip area and simultaneously improve the image resolution.
An embodiment of the utility model provides an amplifier circuit of utensil voltage interpolation function, including the plural number input to, be used for receiving a first voltage and a second voltage, the plural number input is coupled in a voltage output end to another through an output stage, the plural number input is to including at least: a first input pair coupled between a ground and a pair of nodes, comprising at least a first pair of transistors sized to correspond to a first ratio; and a second input pair coupled between the ground point and the pair of nodes, comprising at least a second pair of transistors having a size corresponding to a second ratio, wherein the second ratio is not equal to the first ratio, the second ratio is a multiple of the first ratio, and a voltage output by the voltage output terminal is an interpolation of the first voltage and the second voltage weighted by the first ratio and the second ratio.
Another embodiment of the present invention provides an amplifier circuit with voltage interpolation function, including a plurality of input pairs for receiving a first voltage and a second voltage, the plurality of input pairs are coupled to a voltage output end through an output stage, and the plurality of input pairs at least include: a first input pair coupled between a ground and a pair of nodes, comprising at least a first pair of transistors sized to correspond to a first ratio; a second input pair, coupled between the ground point and the pair of nodes, comprising at least a second pair of transistors sized to correspond to a second ratio; and a third input pair coupled between the ground point and the pair of nodes, comprising at least a third pair of transistors having a size corresponding to a third ratio, wherein the first ratio, the second ratio and the third ratio are different from each other, and the voltage output by the voltage output terminal is an interpolation result of the first voltage and the second voltage weighted by the first ratio, the second ratio and the third ratio.
Another embodiment of the present invention provides a driving device for a liquid crystal display, the driving device comprising the aforementioned amplifier circuit, wherein the amplifier circuit is integrated into the driving device.
Drawings
Fig. 1 is a schematic circuit diagram illustrating an amplifier circuit with voltage interpolation function according to a first embodiment of the present invention;
fig. 2 is an exemplary circuit diagram of an amplifier circuit with voltage interpolation function according to a second embodiment of the present invention;
fig. 3 is a schematic diagram of a driving apparatus for a liquid crystal display according to an embodiment of the present invention.
Description of reference numerals:
100,200,320 Amplifier circuit
110,210 input stage
111-0,111-1,111-2,111-3,111-4,211-0,211-1,211-2,211-3,211-4, input pair
120,220 output stage
300 driving device
310 digital-to-analog converter (DAC)
330 reference voltage trace
A. B, C, D node
E <0>, E <1>, E <2>, E <3>, E <4> select bits
I、I111-0、I111-1、I111-2、I111-3、I111-4Electric current
S _ DATA digital image signal
V1, V2, VIH, VIL, Vo voltages
Vout voltage output terminal
Detailed Description
The invention will be further described with reference to the accompanying drawings and preferred embodiments.
Fig. 1 is a schematic circuit diagram of an amplifier circuit with voltage interpolation function according to a first embodiment of the present invention. The amplifier circuit 100 is used for generating an output voltage Vo according to interpolation of two input voltages VIH and VIL, and includes an input stage 110 and an output stage 120. The input stage 110 includes a plurality of input pairs, such as input pairs 111-0 to 111-4, for receiving input voltages VIH and VIL. The input pairs 111-0-111-4 are commonly coupled between ground and a pair of nodes A, B, are coupled to the output stage 120 through a node A, B, and are coupled to the voltage output terminal Vout of the amplifier circuit 100 through the output stage 120. The output stage 120 is coupled to the node A, B and the voltage output terminal Vout, and is used for converting the differential current output by the input stage 110 into a single-ended voltage, outputting the single-ended voltage to the voltage output terminal Vout, and providing sufficient driving current for the following stage.
The input pairs 111-0 ~ 111-4, each input pair includes two input ends respectively, and the two input ends of each input pair are marked as respective first input end and second input end. The first input terminal of each input pair is coupled to a pair of switching devices respectively for selectively receiving the input voltage VIH or VIL according to a corresponding selection bit, e.g., selection bits E <0> to E <4>, and the second input terminal of each input pair is coupled to the voltage output terminal Vout for receiving the feedback output voltage Vo.
According to the first embodiment of the present invention, the input pairs 111-0 to 111-4 may respectively include a pair of transistors, and the output current of each transistor pair is equal to the product of the transconductance (gm) and the voltage VIH or VIL received by the first input terminal, as shown in the following equations (2) to (6). The square of the transconductance gm is proportional to the product of the input terminal size (W/L, the aspect ratio of a pair of transistors) of each pair of transistors and the amount of current I supplied, as shown in the following equation (1). The output voltage Vo of the output stage 120 is equal to the product of the sum of the output currents of all the input pairs 111-0 to 111-4 and the equivalent output impedance Ro (not shown), as shown in the following equation (7). That is, the output voltage Vo may be determined by a ratio of the size of the input terminal (W/L) of each pair of transistors to the amount of current supplied.
I111-0＝gm0*Vin (2)
I111-1＝gm1*Vin (3)
I111-2＝gm2*Vin (4)
I111-3＝gm3*Vin (5)
I111-4＝gm4*Vin (6)
Vo＝(I111-0+I111-1+I111-2+I111-3+I111-4)*Ro (7)
Wherein, I111-0～I111-4Respectively represent the output currents of the input pairs 111-0 to 111-4, and gm0 to gm4 respectively representThe table inputs the transductions of pairs 111-0 to 111-4, Vin represents the voltage received by each input to the first input, i.e., VIH or VIL.
According to the first embodiment of the present invention, the input pair 111-0 to 111-4 may respectively include a pair of transistors, each pair of transistors having a multiple relationship in size (or a substantially multiple relationship when considering a small manufacturing error), the pair of transistors being configured to generate corresponding currents according to different ratios such that the transistors have a multiple relationship (or a substantially multiple relationship) in the generated currents. For example, the aspect ratio (W/Lratio) of a pair of transistors included in the pair 111-0 can be input as a basic size unit, i.e., the aspect ratio of the pair of transistors can be set to 1 unit, and the current I generated by the input pair 111-0 can also be set to a basic current unit. The sizes of the other input pairs 111-1-111-4 can be flexibly selected or designed according to the basic size unit.
As illustrated in FIG. 1, input pair 111-1 may be sized the same as input pair 111-0. That is, the pair of transistors included in input pair 111-1 may likewise have an aspect ratio of 1 unit. Therefore, the size of the transistor pair included in the input pair 111-1 may correspond to a first ratio, where the first ratio is 1 and the magnitude of the current generated by the transistor pair is 1 ×.i. In an embodiment of the present invention, the ratio represents a ratio of a size of the transistor pair to the basic size unit. Similarly, the size of the transistor pairs included in input pair 111-0 also corresponds to the first ratio.
The size of input pair 111-2 may be designed to be twice that of input pair 111-0. That is, the pair of transistors included in input pair 111-2 may have an aspect ratio of 2 units. Therefore, the size of the transistor pair included in the input pair 111-2 may correspond to a second ratio, where the second ratio is 2 and the magnitude of the current generated by the transistor pair is 2 ×.i.
The size of input pair 111-3 may be designed to be four times that of input pair 111-0. That is, the pair of transistors included in input pair 111-3 may have an aspect ratio of 4 units. Thus, the size of the transistor pairs included in the input pair 111-3 may correspond to a third ratio, where the third ratio is 4 and the magnitude of the current generated by the transistor pairs is 4 x I.
The size of input pair 111-4 may be designed to be eight times that of input pair 111-0. That is, the pair of transistors included in input pair 111-4 may have an aspect ratio of 8 units. Thus, the size of the transistor pairs included in the input pair 111-4 may correspond to a fourth ratio, where the fourth ratio is 8 and the magnitude of the current generated by the transistor pairs is 8 x I.
In the embodiment of the present invention, the input pairs 111-0 to 111-4 in the input stage 110 can weight the input voltages VIH and VIL according to unequal ratios and output the voltage Vo at the voltage output terminal Vout, i.e., the interpolated result of the input voltages VIH and VIL weighted by unequal ratios is used as the output voltage Vo. In this embodiment, the fourth ratio is greater than the third ratio, the third ratio is greater than the second ratio, the second ratio is greater than the first ratio, and the fourth ratio is a multiple of the third ratio, the third ratio is a multiple of the second ratio, and the fourth ratio, the third ratio and the second ratio are all multiples of the first ratio.
As illustrated in FIG. 1, the input stage 110 can use the input pairs 111-0 to 111-4 to weight the input voltages VIH and VIL according to the ratios of 1,2, 4, 8, etc. to generate the interpolation result, so as to realize the 4-bit voltage interpolation, wherein the sum of the ratio values is the number of the interpolation voltages. More specifically, the input stage 110 can generate 16 voltages with different levels by weighting the input voltage VIH or VIL with the input pairs 111-0-111-4 according to the unequal ratio, wherein 16 is 1+1+2+4+8, i.e. 4 times of 2, so as to perform 4-bit voltage interpolation. And the relationship between the output voltage Vo and the input voltage VIH or VIL, and the unequal ratio can be expressed by the following equivalent equation (8):
in the formula (8), the reaction mixture is,
corresponding to the inverted signals representing E <0> -E <4 >. In which the embodiment shown in fig. 1 and 2In the embodiment, if it is used to receive the selection bit E<0>～E<4>The receiving end of (a) draws a circle "○", indicating that the signal actually input to the circuit will be the inverse of the selected bit (e.g.,
one of (a); if it is used to receive the selection bit E<0>～E<4>The receiving end of (1) does not draw a circle "○" representing that the signal actually inputted into the circuit is a selection bit (e.g., E)<0>～E<4>One of (1) of (a). In the embodiment of the present invention, the operation of inverting the selection bit can be implemented by providing an inverter or other circuits with similar functions at the receiving end of the selection bit.
It is noted that the above ratios are only used as examples and are not used to limit the scope of the present invention. According to embodiments of the present invention, the ratio is selected according to the number of interpolation voltages required, and can be flexibly combined and varied. For example, if 5-bit voltage interpolation is to be implemented, one input pair may be added, which may include transistor pairs sized 16 times the base size unit (i.e., corresponding to a ratio of 16), or two input pairs, which may include transistor pairs sized 8 times the base size unit (i.e., corresponding to a ratio of 8).
Compared with the prior art, the utility model discloses an amplifier circuit 100 usable less transistor is to realizing the same voltage interpolation function to can reduce the required control signal of amplifier circuit by a wide margin and walk line and switching device's quantity, effectively reduce circuit layout's area.
Fig. 2 is a schematic circuit diagram of an amplifier circuit with voltage interpolation according to a second embodiment of the present invention. The amplifier circuit 200 is used for generating an output voltage Vo according to the interpolation of two input voltages VIH and VIL, and includes an input stage 210 and an output stage 220. The input stage 210 includes a plurality of input pairs, such as input pairs 211-0 to 211-4, for receiving input voltages VIH and VIL. The input pairs 211-0-211-4 are commonly coupled between ground and a pair of nodes C, D, are coupled to the output stage 220 through a node C, D, and are coupled to the voltage output terminal Vout of the amplifier circuit 200 through the output stage 220. The output stage 220 is coupled to the node C, D and the voltage output terminal Vout, and is used for converting the differential current output by the input stage 210 into a single-ended voltage, outputting the single-ended voltage to the voltage output terminal Vout, and providing sufficient driving current for the following stage.
Five input pairs 211-0 ~ 211-4, each input pair comprising two pairs of transistors, and each transistor pair may comprise two input pairs, the two input terminals of each transistor pair being identified as respective first and second input terminals. More specifically, a first input terminal of one of the transistors in each input pair receives the voltage VIH, a first input terminal of the other transistor in each input pair receives the voltage VIL, and a second input terminal of each transistor in each input pair is coupled to the voltage output terminal Vout for receiving the fed back output voltage Vo. In addition, each of the input pairs 211-0 to 211-4 is coupled to a pair of switching devices, respectively, for selectively generating a corresponding current based on a desired input voltage VIH or VIL according to a corresponding selection bit, e.g., selection bits E <0> to E <4 >.
According to the second embodiment of the present invention, the input pairs 211-0 to 211-4 may respectively include two pairs of transistors, and the output current of each pair of transistors is equal to the product of the transconductance (gm) and the voltage received by the first input terminal (one skilled in the art can make adaptive adjustments according to the above equations (2) to (6) to derive the corresponding equations). The first input terminal of one of the transistors in each input pair is used for receiving an input voltage VIH, and the first input terminal of the other transistor in each input pair is used for receiving an input voltage VIL. The square of the transconductance gm is in turn proportional to the product of the input size (W/L) of each pair of transistors and the amount of current I supplied, as shown in equation (1) above. The output voltage Vo of the output stage 220 is equal to the product of the sum of the output currents of all the input pairs 211-0 to 211-4 and the equivalent output impedance Ro (not shown) (those skilled in the art can derive the corresponding formula by adaptively adjusting the above formula (7)). That is, the output voltage Vo may be determined by a ratio of the size of the input terminal (W/L) of each pair of transistors to the amount of current supplied.
According to a second embodiment of the present invention, the input pair 211-0 to 211-4 may comprise transistor pairs having a multiple relationship (or, when considering a few manufacturing errors, a substantially multiple relationship) in their dimensions, said transistor pairs being configured to generate corresponding currents according to different ratios, such that the transistor pairs have a multiple relationship (or, substantially, a multiple relationship) in their generated currents. For example, the two pairs of transistors included in the input pair 211-0 may have the same aspect ratio, and the aspect ratios of the two pairs of transistors may be set to the basic size unit, i.e., the aspect ratios of the two pairs of transistors may be set to 1 unit, and the current I generated by the input pair 211-0 may also be set to the basic current unit. The sizes of the other input pairs 211-1-211-4 can be flexibly selected or designed according to the basic size unit.
As illustrated in FIG. 2, input pair 211-1 may be sized the same as input pair 211-0. That is, the two pairs of transistors included in input pair 211-1 may likewise have an aspect ratio of 1 unit. Therefore, the size of the two transistor pairs included in the input pair 211-1 may correspond to a first ratio, where the first ratio is 1 and the magnitude of the current generated by the transistor pairs is 1 ×.i. In an embodiment of the present invention, the ratio represents a ratio of a size of the transistor pair to the basic size unit. Similarly, the size of the transistor pairs included in input pair 211-0 also corresponds to the first ratio.
The size of input pair 211-2 may be designed to be twice that of input pair 211-0. That is, the two pairs of transistors included in input pair 211-2 may have an aspect ratio of 2 units. Thus, the size of the transistor pair included in the input pair 211-2 may correspond to a second ratio, where the second ratio is 2 and the magnitude of the current generated by the transistor pair is 2 ×.i.
The size of the input pair 211-3 may be designed to be four times that of the input pair 211-0. That is, the two pairs of transistors included in input pair 211-3 may have an aspect ratio of 4 units. Thus, the size of the transistor pair included in the input pair 211-3 may correspond to a third ratio, where the third ratio is 4 and the magnitude of the current generated by the transistor pair is 4 x I.
The size of input pair 211-4 may be designed to be eight times that of input pair 211-0. That is, the two pairs of transistors included in input pair 211-4 may have an aspect ratio of 8 units. Thus, the size of the transistor pair included in the input pair 211-4 may correspond to a fourth ratio, where the fourth ratio is 8 and the magnitude of the current generated by the transistor pair is 8 x I.
In the embodiment of the present invention, the input pairs 211-0 to 211-4 in the input stage 210 can weight the input voltages VIH and VIL according to unequal ratios and output the voltage Vo at the voltage output terminal Vout, i.e., the input voltages VIH and VIL are used as the output voltage Vo through an interpolation result weighted by unequal ratios. In this embodiment, the fourth ratio is greater than the third ratio, the third ratio is greater than the second ratio, the second ratio is greater than the first ratio, and the fourth ratio is a multiple of the third ratio, the third ratio is a multiple of the second ratio, and the fourth ratio, the third ratio and the second ratio are all multiples of the first ratio.
As shown in FIG. 2, the input stage 210 can use the input pairs 211-0 to 211-4 to weight the input voltages VIH and VIL according to the ratios of 1,2, 4, 8, etc. to generate the interpolation result, so as to realize the 4-bit voltage interpolation, wherein the sum of the ratio values is the number of the interpolation voltages. More specifically, the input stage 210 can generate 16 voltages with different levels by weighting the input voltage VIH or VIL with the input pairs 211-0-211-4 according to the unequal ratio, wherein 16 is 1+1+2+4+8, i.e. 4 times of 2, so as to perform 4-bit voltage interpolation. The relationship between the output voltage Vo and the input voltage VIH or VIL, and the unequal ratio may be the same as the above-listed equivalent equation (8).
It should be noted that the above ratio is only used for illustration and not for limiting the protection scope of the present invention. According to embodiments of the present invention, the ratio is selected according to the number of interpolation voltages required, and can be flexibly combined and varied. For example, if 5-bit voltage interpolation is to be implemented, one input pair may be added, which may include transistor pairs sized 16 times the base size unit (i.e., corresponding to a ratio of 16), or two input pairs, which may include transistor pairs sized 8 times the base size unit (i.e., corresponding to a ratio of 8).
Compared with the prior art, the utility model discloses an amplifier circuit 200 usable less transistor is to realizing the same voltage interpolation function to can reduce the required control signal of amplifier circuit by a wide margin and walk line and switching device's quantity, effectively reduce circuit layout's area.
Fig. 3 is a schematic diagram of a driving apparatus 300 for an lcd according to an embodiment of the present invention. The amplifier circuit 100/200 of the present invention can be integrated into the driving device of the liquid crystal display. The driving device 300 may comprise a digital-to-analog converter 310, an amplifier circuit 320 and 2NThe strip reference voltage trace 330. The reference voltage trace 330 is used to provide a reference voltage 2 generated by a reference voltage generating circuit (not shown)NGamma reference voltage. The DAC 310 is coupled to the reference voltage trace 330 for generating a digital video signal S _ DATA from 2NTwo adjacent reference voltages V1 and V2 are switched from the gamma reference voltage, wherein V1 and V2 are provided to the amplifier circuit 320 as the input voltages VIH and VIL. The amplifier circuit 320 can be implemented by the amplifier circuit 100/200 of fig. 1 or fig. 2, and is used for generating an output voltage Vo corresponding to the interpolation result according to the reference voltages V1 and V2 output by the digital-to-analog converter 310.
Therefore, 2 is generated by the voltage interpolation of the amplifier circuit 320 having the interpolation function according to the input voltage thereofKAn interpolated voltage, the driving device 300 will eventually be equivalent to generate 2(N+K)A gamma reference voltage, wherein 2KIs the sum of the dimensional ratio values of the transistor pairs of the input stage of the amplifier circuit. Compared with the prior art, the utility model discloses an usable less transistor of amplifier circuit 320 is to realizing the same voltage interpolation function to can reduce the required control signal of amplifier circuit by a wide margin and walk line and switching device's quantity, effectively reduce circuit layout's area. Furthermore, the transistors in the input stage of the amplifier circuit of the present invention can be operated in the same operation region (e.g., saturation region), and thus compared to the prior art, the present invention also has the advantage of easy design. In addition, the voltage value interpolated by the present invention has better linearity, for example, the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) performances are better than the conventional techniques. In addition, because the present invention adopts the transistor dimension design with unequal ratio, the amplifier circuit has larger-sized elements, so that the influence of the error (random mismatch) between the elements on the whole circuit can be relatively weakened.
The foregoing is a more detailed description of the present invention, taken in conjunction with the specific preferred embodiments thereof, and it is not intended that the invention be limited to the specific embodiments shown and described. To the technical field of the utility model belongs to the prerequisite of not deviating from the utility model discloses, can also make a plurality of equal substitution or obvious variants, performance or usage are the same moreover, all should regard as belonging to the utility model's scope of protection.
Claims (12)
1. An amplifier circuit with voltage interpolation, comprising: the circuit comprises a plurality of input pairs for receiving a first voltage and a second voltage, the plurality of input pairs are coupled to a voltage output end through an output stage, and the plurality of input pairs at least comprise:
a first input pair coupled between a ground and a pair of nodes, comprising at least a first pair of transistors sized to correspond to a first ratio; and
a second input pair coupled between the ground point and the pair of nodes, comprising at least a second pair of transistors having a size corresponding to a second ratio, wherein the second ratio is not equal to the first ratio, the second ratio is a multiple of the first ratio, and a voltage output by the voltage output terminal is an interpolation of the first voltage and the second voltage weighted by the first ratio and the second ratio.
2. The amplifier circuit of claim 1, further comprising:
a third input pair comprising at least a third pair of transistors sized to correspond to a third ratio, wherein the third ratio is not equal to the second ratio, the third ratio is a multiple of the first ratio and the second ratio, and the voltage output by the voltage output is an interpolation of the first voltage and the second voltage weighted by the first ratio, the second ratio, and the third ratio.
3. The amplifier circuit of claim 1,
the first input pair further comprises two inputs: one input end is used for selectively receiving the first voltage or the second voltage according to a first selection bit, and the other input end is coupled with the voltage output end;
the second input pair further comprises two inputs: one input end is used for selectively receiving the first voltage or the second voltage according to a second selection bit, and the other input end is coupled with the voltage output end.
4. The amplifier circuit of claim 1,
the first pair of transistors includes two input terminals: one input end is used for receiving the first voltage, and the other input end is coupled with the voltage output end;
said first input pair further comprises a third pair of transistors sized to correspond to said first ratio; and, the third pair of transistors comprises two input terminals: one input end is used for receiving the second voltage, and the other input end is coupled to the voltage output end.
5. The amplifier circuit of claim 1,
the second pair of transistors comprises two input terminals: one input end is used for receiving the first voltage, and the other input end is coupled with the voltage output end;
said second input pair further comprising a fourth pair of transistors sized to correspond to said second ratio; and, the fourth pair of transistors includes two input terminals: one input end is used for receiving the second voltage, and the other input end is coupled to the voltage output end.
6. An amplifier circuit with voltage interpolation, comprising: the circuit comprises a plurality of input pairs for receiving a first voltage and a second voltage, the plurality of input pairs are further coupled to a voltage output end through an output stage, and the plurality of input pairs at least comprise:
a first input pair coupled between a ground and a pair of nodes, comprising at least a first pair of transistors sized to correspond to a first ratio;
a second input pair, coupled between the ground point and the pair of nodes, comprising at least a second pair of transistors sized to correspond to a second ratio; and
a third input pair coupled between the ground point and the pair of nodes, comprising at least a third pair of transistors having a size corresponding to a third ratio, wherein the first ratio, the second ratio and the third ratio are different from each other, and the voltage output by the voltage output terminal is an interpolation result of the first voltage and the second voltage weighted by the first ratio, the second ratio and the third ratio.
7. The amplifier circuit of claim 6, wherein the third ratio is greater than the second ratio, the second ratio is greater than the first ratio, and the third ratio and the second ratio are each multiples of the first ratio.
8. The amplifier circuit of claim 6,
the first input pair further comprises two inputs: one input end is used for selectively receiving the first voltage or the second voltage according to a first selection bit, and the other input end is coupled with the voltage output end;
the second input pair further comprises two inputs: one input end is used for selectively receiving the first voltage or the second voltage according to a second selection bit, and the other input end is coupled with the voltage output end;
the third input pair further comprises two inputs: one input end is used for selectively receiving the first voltage or the second voltage according to a third selection bit, and the other input end is coupled to the voltage output end.
9. The amplifier circuit of claim 6,
the first pair of transistors includes two input terminals: one input end is used for receiving the first voltage, and the other input end is coupled with the voltage output end;
said first input pair further comprises a fourth pair of transistors having a size corresponding to said first ratio, and said fourth pair of transistors comprises two input terminals: one input end is used for receiving the second voltage, and the other input end is coupled to the voltage output end.
10. The amplifier circuit of claim 6,
the second pair of transistors comprises two input terminals: one input end is used for receiving the first voltage, and the other input end is coupled with the voltage output end;
said second input pair further comprises a fifth pair of transistors having a size corresponding to said second ratio, and said fifth pair of transistors comprises two input terminals: one input end is used for receiving the second voltage, and the other input end is coupled to the voltage output end.
11. The amplifier circuit of claim 6,
the third pair of transistors comprises two input terminals: one input end is used for receiving the first voltage, and the other input end is coupled with the voltage output end;
said third input pair further comprises a sixth pair of transistors sized to correspond to said third ratio, and said sixth pair of transistors comprises two input terminals: one input end is used for receiving the second voltage, and the other input end is coupled to the voltage output end.
12. A driving apparatus for a liquid crystal display, characterized in that: the driving device comprising the amplifier circuit of claim 1 or 6, wherein the amplifier circuit is integrated into the driving device.
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| CN109903730A (en) * | 2019-02-13 | 2019-06-18 | 奕力科技股份有限公司 | Buffer circuit |
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| CN109903730A (en) * | 2019-02-13 | 2019-06-18 | 奕力科技股份有限公司 | Buffer circuit |
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