CN210927601U - Drive and Amplifier Circuit with Voltage Interpolation - Google Patents

Abstract

The utility model discloses a drive arrangement and amplifier circuit of utensil voltage interpolation function, this amplifier circuit include that plural number input is right for receive a first voltage and a second voltage, the plural number input is coupled in a voltage output end through an output stage in addition, the plural number input includes to at least: a first input pair coupled between a ground and a pair of nodes, comprising at least a first pair of transistors sized to correspond to a first ratio; and a second input pair coupled between the ground point and the pair of nodes, including at least a second pair of transistors having a size corresponding to a second ratio, wherein the second ratio is not equal to the first ratio, the second ratio is a multiple of the first ratio, and a voltage output by the voltage output terminal is an interpolation result of the first voltage and the second voltage weighted by the first ratio and the second ratio. The driving device comprises the amplifier circuit.

Description

Drive and Amplifier Circuit with Voltage Interpolation

technical field

The utility model relates to an amplifier circuit with a voltage interpolation function, and a driving device including the amplifier circuit.

Background technique

With the increase in the size and resolution of the liquid crystal panel, the area occupied by the display driver chip layout is also increasing. Among them, the 6-bit digital-to-analog converter is currently generally recognized as a design with better chip area utilization. However, the 6-bit image resolution can no longer meet the image resolution requirements of larger-sized LCD panels. For example, the image resolution requirement of today's large-sized liquid crystal panels has reached 10 bits. If the 6-bit digital-to-analog converter is upgraded to a 10-bit digital-to-analog converter to meet the image resolution requirement of at least 10 bits, the digital-to-analog converter will occupy a large circuit area, making the utilization rate of the chip area large. decline.

Therefore, while improving the image resolution, how to reduce the chip area and production cost has become a very important issue in the industry.

Utility model content

One of the objectives of the present invention is to provide an amplifier circuit with a voltage interpolation function, which can effectively reduce the chip area and improve the image resolution.

Another object of the present invention is to provide a driving device for a liquid crystal display, which can effectively reduce the chip area and improve the image resolution.

An embodiment of the present invention provides an amplifier circuit with a voltage interpolation function, comprising a complex input pair for receiving a first voltage and a second voltage, the complex input pair being coupled to the other through an output stage A voltage output terminal, the plurality of input pairs at least include: a first input pair coupled between a ground point and a pair of nodes, including at least a first pair of transistors, the size of the first pair of transistors corresponds to a a first ratio; and a second input pair coupled between the ground point and the pair of nodes, comprising at least a second pair of transistors sized to correspond to a second ratio, wherein The second ratio is not equal to the first ratio, the second ratio is a multiple of the first ratio, and a voltage output by the voltage output terminal is the first voltage and the second ratio The voltage is an interpolated result weighted by the first ratio and the second ratio.

Another embodiment of the present invention provides an amplifier circuit with a voltage interpolation function, comprising a plurality of input pairs for receiving a first voltage and a second voltage, the plurality of input pairs being coupled to the other through an output stage at a voltage output end, and the complex input pair at least includes: a first input pair, coupled between a ground point and a pair of nodes, including at least a first pair of transistors, the size of the first pair of transistors corresponds to in a first ratio; a second input pair, coupled between the ground point and the pair of nodes, including at least a second pair of transistors, the size of the second pair of transistors corresponding to a second ratio; and a third input pair coupled between the ground point and the pair of nodes, including at least a third pair of transistors sized to correspond to a third ratio, wherein the first pair of transistors The ratio, the second ratio and the third ratio are not equal to each other, and the voltage output by the voltage output terminal is the first voltage and the second voltage through the first ratio, the second voltage The ratio is weighted with the third ratio of the interpolation result.

Yet another embodiment of the present invention provides a driving device for a liquid crystal display. The driving device includes the aforementioned amplifier circuit, wherein the amplifier circuit is integrated into the driving device.

Description of drawings

1 is an exemplary circuit schematic diagram of an amplifier circuit with a voltage interpolation function provided by a first embodiment of the present invention;

2 is an exemplary circuit schematic diagram of an amplifier circuit with a voltage interpolation function provided by a second embodiment of the present invention;

FIG. 3 is a schematic diagram of a driving device for a liquid crystal display provided by a specific embodiment of the present invention.

Description of reference numbers:

100, 200, 320: Amplifier Circuits

110, 210: Input stage

111-0, 111-1, 111-2, 111-3, 111-4, 211-0, 211-1, 211-2, 211-3, 211-4: Input pairs

120,220: output stage

300: Drive

310: Digital to Analog Converter (DAC)

330: Reference voltage trace

A, B, C, D: Nodes

E<0>, E<1>, E<2>, E<3>, E<4>: select bits

I, I _111-0 , I _111-1 , I _111-2 , I _111-3 , I _111-4 : Current

S_DATA: digital video signal

V1, V2, VIH, VIL, Vo: Voltage

Vout: voltage output terminal

Detailed ways

The present utility model will be further described below with reference to the accompanying drawings and in conjunction with the preferred embodiments.

FIG. 1 is an exemplary circuit schematic diagram of an amplifier circuit with a voltage interpolation function provided by the first embodiment of the present invention. The amplifier circuit 100 is used for generating an output voltage Vo by interpolation according to the two input voltages VIH and VIL, and includes an input stage 110 and an output stage 120 . The input stage 110 includes a plurality of input pairs, such as input pairs 111-0 to 111-4, for receiving the input voltages VIH and VIL. The input pairs 111 - 0 to 111 - 4 are commonly coupled between the ground point and a pair of nodes A and B, are coupled to the output stage 120 through the nodes A and B, and are coupled to the voltage output of the amplifier circuit 100 through the output stage 120 terminal Vout. The output stage 120 is coupled to the nodes A, B and the voltage output terminal Vout, which is used to convert the differential current output by the input stage 110 into a single-ended voltage form and output it to the voltage output terminal Vout, and provide sufficient power for the subsequent circuit drive current.

The input pairs 111-0 to 111-4, each of which includes two input ends respectively, and the two input ends of each input pair are denoted as respective first input ends and second input ends. The first input terminals of each input pair are respectively coupled to a pair of switching devices for selectively receiving the input voltage VIH according to a corresponding selection bit, for example, selection bits E<0>-E<4> or VIL, the second input terminal of each input pair is coupled to the voltage output terminal Vout for receiving the feedback output voltage Vo.

According to the first embodiment of the present invention, the input pairs 111-0 to 111-4 may respectively include a pair of transistors, and the respective output current of each pair of transistors is equal to the respective transconductance (gm) and the first input terminal. The product of the received voltages VIH or VIL is shown in the following equations (2) to (6). Among them, the square of the transduction gm is proportional to the product of the input terminal size of each pair of transistors (W/L, the aspect ratio of a pair of transistors) and the supplied current I, as shown in the following formula (1) . The output voltage Vo of the output stage 120 is equal to the product of the sum of the output currents of all the input pairs 111-0 to 111-4 and the equivalent output impedance Ro (not shown), as shown in the following formula (7). That is, the output voltage Vo can be determined by the ratio of the input terminal size (W/L) of each pair of transistors to the amount of current supplied.

I _111-0 = gm0*Vin (2)

I _111-1 =gm1*Vin (3)

I _111-2 =gm2*Vin (4)

I _111-3 =gm3*Vin (5)

I _111-4 = gm4*Vin (6)

Vo=(I _111-0 +I _111-1 +I _111-2 +I _111-3 +I _111-4 )*Ro (7)

Among them, I _111-0 to I _111-4 represent the output currents of the input pairs 111-0 to 111-4, respectively, gm0 to gm4 represent the transduction of the input pairs 111-0 to 111-4, respectively, and Vin represents the input to the first The voltage received by an input terminal is VIH or VIL.

According to the first embodiment of the present invention, the input pairs 111-0 to 111-4 may respectively include a pair of transistors, and the sizes of the transistors of each pair have a multiple relationship (or, when a slight manufacturing error is considered, generally a multiple relationship) , the transistor pairs are used to generate corresponding currents according to different ratios, so that the currents generated by the transistor pairs have a multiple relationship (or generally a multiple relationship). For example, the aspect ratio (W/Lratio) of a pair of transistors included in the pair 111-0 can be input as the base size unit, that is, the aspect ratio of the pair of transistors can be set to 1 unit, and the input pair 111 The current I produced by -0 is also set as the base current unit. The sizes of the other input pairs 111-1 to 111-4 can be flexibly selected or designed according to the basic dimension unit.

As illustrated in FIG. 1, the input pair 111-1 may be designed to be the same size as the input pair 111-0. That is, a pair of transistors included in the input pair 111-1 may also have an aspect ratio of 1 unit. Therefore, the size of the transistor pair included in the input pair 111-1 may correspond to a first ratio, in which case the first ratio is 1, and the magnitude of the current generated by the transistor pair is 1*I. In an embodiment of the present invention, the ratio represents the ratio of the size of the transistor pair to the above-mentioned basic size unit. Likewise, the size of the transistor pair included in the input pair 111-0 also corresponds to the first ratio.

Input pair 111-2 can be designed to be twice the size of input pair 111-0. That is, a pair of transistors included in the input pair 111-2 may have an aspect ratio of 2 units. Therefore, the size of the transistor pair included in the input pair 111-2 may correspond to a second ratio, in which case the second ratio is 2, and the magnitude of the current generated by the transistor pair is 2*I.

Input pair 111-3 can be designed to be four times the size of input pair 111-0. That is, a pair of transistors included in the input pair 111-3 may have an aspect ratio of 4 units. Therefore, the size of the transistor pair included in the input pair 111-3 may correspond to a third ratio, where the third ratio is 4, and the magnitude of the current generated by the transistor pair is 4*I.

Input pair 111-4 can be designed to be eight times the size of input pair 111-0. That is, a pair of transistors included in the input pair 111-4 may have an aspect ratio of 8 units. Therefore, the size of the transistor pair included in the input pair 111-4 may correspond to a fourth ratio, where the fourth ratio is 8, and the magnitude of the current generated by the transistor pair is 8*I.

In the embodiment of the present invention, the input pairs 111-0 to 111-4 in the input stage 110 can weight the input voltages VIH and VIL according to unequal ratios, and output the voltage Vo at the voltage output terminal Vout, that is, , the interpolation result of the input voltage VIH and VIL weighted by unequal ratio is used as the output voltage Vo. Wherein, in this embodiment, the fourth ratio is greater than the third ratio, the third ratio is greater than the second ratio, the second ratio is greater than the first ratio, and the fourth ratio is a multiple of the third ratio, and the third ratio is the second ratio The fourth ratio, the third ratio and the second ratio are all multiples of the first ratio.

As shown in FIG. 1 , the input stage 110 can use the input pairs 111-0 to 111-4 to respectively weight the input voltage VIH or VIL according to the ratio of 1, 1, 2, 4, 8, etc. to generate an interpolation result, so as to achieve 4-bit voltage interpolation, where the sum of the ratio values is the number of interpolated voltages. More specifically, the input stage 110 can use the input pairs 111-0 to 111-4 to weight the input voltage VIH or VIL according to the unequal ratio to generate 16 voltages of different levels, wherein 16=1+1+ 2+4+8, which is 2 to the 4th power, to achieve 4-bit voltage interpolation. The relationship between the output voltage Vo and the input voltage VIH or VIL, and the unequal ratio can be expressed by the following equivalent formula (8):

对应表示E＜0＞～E＜4＞的反相信号。其中于图1、图2所示实施例中，若用以接收选择位元E<0>～E<4>的接收端绘制了圆圈“○”，代表实际输入该电路的信号将会是选择位元的反相信号(例如，

的其中一者)；若用以接收选择位元E<0>～E<4>的接收端并未绘制圆圈“○”，代表实际输入该电路的信号为选择位元(例如，E<0>～E<4>的其中一者)。于本实用新型的实施例中，可通过于选择位元接收端设置一反相器或其他类似功能的电路实施将选择位元反相的操作。In formula (8),

Corresponds to the inverted signals representing E<0> to E<4>. In the embodiment shown in FIG. 1 and FIG. 2 , if the receiving end used to receive the selection bits E<0>~E<4> is drawn with a circle "○", it means that the signal actually input to the circuit will be the selection bit-bit inverted signal (for example,

If the receiving end used to receive the selection bits E<0>~E<4> does not draw a circle "○", it means that the signal actually input to the circuit is the selection bit (for example, E<0 >～E<4> one of). In the embodiment of the present invention, the operation of inverting the selected bits can be implemented by arranging an inverter or other circuits with similar functions at the receiving end of the selected bits.

It is worth noting that the above ratios are only used as examples, and are not used to limit the scope of the present invention. According to an embodiment of the present invention, the ratio is selected according to the required number of interpolated voltages, and can be combined and changed flexibly. For example, to achieve 5-bit voltage interpolation, an input pair can be added, and the size of the transistor pair included in this input pair can be designed to be 16 times the base size unit (that is, the corresponding ratio is 16) Alternatively, two input pairs may be added, and the size of the transistor pairs included in the two input pairs may be designed to be 8 times the base size unit (ie, the corresponding ratio is 8).

Compared with the prior art, the amplifier circuit 100 of the present invention can use fewer transistor pairs to achieve the same voltage interpolation function, thereby greatly reducing the number of control signal traces and switching devices required by the amplifier circuit, effectively Reduce the area of the circuit layout.

FIG. 2 is an exemplary circuit diagram of an amplifier circuit with a voltage interpolation function provided by a second embodiment of the present invention. The amplifier circuit 200 is used for generating an output voltage Vo by interpolation according to the two input voltages VIH and VIL, and includes an input stage 210 and an output stage 220 . The input stage 210 includes a plurality of input pairs, such as input pairs 211-0 to 211-4, for receiving the input voltages VIH and VIL. The input pairs 211 - 0 to 211 - 4 are commonly coupled between the ground point and a pair of nodes C and D, are coupled to the output stage 220 through the nodes C and D, and are coupled to the voltage output of the amplifier circuit 200 through the output stage 220 terminal Vout. The output stage 220 is coupled to the nodes C, D and the voltage output terminal Vout, which is used to convert the differential current output by the input stage 210 into a single-ended voltage form and output it to the voltage output terminal Vout, and provide sufficient power for the subsequent circuit drive current.

There are five input pairs 211-0 to 211-4, each input pair includes two pairs of transistors, and each pair of transistors can include two input pairs respectively, and the two input ends of each pair of transistors are recorded as respective the first input terminal and the second input terminal. More specifically, the first input terminal of one pair of transistors of each input pair is used for receiving the voltage VIH, the first input terminal of the other pair of transistors is used for receiving the voltage VIL, and the second input terminal of each pair of transistors is coupled to Connected to the voltage output terminal Vout for receiving the feedback output voltage Vo. In addition, each of the input pairs 211-0 to 211-4 is respectively coupled to a pair of switch devices for selectively selecting based on a corresponding selection bit, for example, the selection bits E<0> to E<4>. The desired input voltage VIH or VIL produces the corresponding current.

According to the second embodiment of the present invention, the input pairs 211-0 to 211-4 may respectively include two pairs of transistors, and the respective output current of each pair of transistors is equal to the respective transconductance (gm) and the first input terminal The product of the received voltages (persons skilled in the art can make adaptive adjustments according to the above formulas (2) to (6) to deduce the corresponding formulas). The first input end of one pair of transistors of each input pair is used for receiving the input voltage VIH, and the first input end of the other pair of transistors is used for receiving the input voltage VIL. Among them, the square of the transduction gm is proportional to the product of the input terminal size (W/L) of each pair of transistors and the supplied current I, as shown in the above formula (1). The output voltage Vo of the output stage 220 is equal to the product of the sum of the output currents of all the input pairs 211-0 to 211-4 and the equivalent output impedance Ro (not shown) (those skilled in the art can make The corresponding formula is derived by adapting the adjustment). That is, the output voltage Vo can be determined by the ratio of the input terminal size (W/L) of each pair of transistors to the amount of current supplied.

According to the second embodiment of the present invention, the sizes of the transistor pairs included in the input pairs 211-0 to 211-4 may have a multiple relationship (or, when a slight manufacturing error is considered, generally a multiple relationship), the transistors The pairs are used to generate corresponding currents according to different ratios, so that the transistor pairs have a multiple relationship (or, generally, a multiple relationship) of the generated currents. For example, the two pairs of transistors included in the input pair 211-0 may have the same aspect ratio, and the aspect ratio of the two pairs of transistors may be set as the basic size unit, that is, the width and height of the two pairs of transistors All can be set to 1 unit, and the current I produced by the input pair 211-0 is also set to the base current unit. The sizes of the other input pairs 211-1 to 211-4 can be flexibly selected or designed according to the basic dimension unit.

As illustrated in FIG. 2, the input pair 211-1 may be designed to be the same size as the input pair 211-0. That is, the two pairs of transistors included in the input pair 211-1 may also have an aspect ratio of 1 unit. Therefore, the size of the two transistor pairs included in the input pair 211-1 may correspond to a first ratio, and the first ratio is 1, and the magnitude of the current generated by the transistor pair is 1*I. In an embodiment of the present invention, the ratio represents the ratio of the size of the transistor pair to the above-mentioned basic size unit. Likewise, the size of the transistor pairs included in the input pair 211-0 also corresponds to the first ratio.

Input pair 211-2 can be designed to be twice the size of input pair 211-0. That is, the two pairs of transistors included in the input pair 211-2 may have an aspect ratio of 2 units. Therefore, the size of the transistor pair included in the input pair 211-2 may correspond to a second ratio, where the second ratio is 2, and the magnitude of the current generated by the transistor pair is 2*I.

Input pair 211-3 can be designed to be four times the size of input pair 211-0. That is, the two pairs of transistors included in the input pair 211-3 may have an aspect ratio of 4 units. Therefore, the size of the transistor pair included in the input pair 211-3 may correspond to a third ratio, where the third ratio is 4, and the magnitude of the current generated by the transistor pair is 4*I.

Input pair 211-4 can be designed to be eight times the size of input pair 211-0. That is, the two pairs of transistors included in the input pair 211-4 may have an aspect ratio of 8 units. Therefore, the size of the transistor pair included in the input pair 211-4 may correspond to a fourth ratio, where the fourth ratio is 8, and the magnitude of the current generated by the transistor pair is 8*I.

In the embodiment of the present invention, the input pairs 211-0 to 211-4 in the input stage 210 can weight the input voltages VIH and VIL according to unequal ratios, and output the voltage Vo at the voltage output terminal Vout, that is, , an interpolation result of the input voltage VIH and VIL weighted by an unequal ratio is used as the output voltage Vo. Wherein, in this embodiment, the fourth ratio is greater than the third ratio, the third ratio is greater than the second ratio, the second ratio is greater than the first ratio, and the fourth ratio is a multiple of the third ratio, and the third ratio is the second ratio The fourth ratio, the third ratio and the second ratio are all multiples of the first ratio.

In the embodiment shown in FIG. 2 , the input stage 210 can use the input pairs 211-0 to 211-4 to respectively weight the input voltage VIH or VIL according to the ratio of 1, 1, 2, 4, 8, etc., to generate an interpolation result, To achieve 4-bit voltage interpolation, where the sum of the ratio values is the number of interpolated voltages. More specifically, the input stage 210 can use the input pairs 211-0 to 211-4 to weight the input voltage VIH or VIL according to the unequal ratio to generate 16 voltages of different levels, wherein 16=1+1+ 2+4+8, which is 2 to the 4th power, to achieve 4-bit voltage interpolation. And the relationship between the output voltage Vo and the input voltage VIH or VIL, and the unequal ratio can be the same as the equivalent formula (8) listed above.

It should be noted that the above ratios are only used for illustration, not for limiting the protection scope of the present invention. According to an embodiment of the present invention, the ratio is selected according to the required number of interpolated voltages, and can be combined and changed flexibly. For example, to achieve 5-bit voltage interpolation, an input pair can be added, and the size of the transistor pair included in this input pair can be designed to be 16 times the base size unit (that is, the corresponding ratio is 16) Alternatively, two input pairs may be added, and the size of the transistor pairs included in the two input pairs may be designed to be 8 times the base size unit (ie, the corresponding ratio is 8).

Compared with the prior art, the amplifier circuit 200 of the present invention can use fewer transistor pairs to achieve the same voltage interpolation function, thereby greatly reducing the number of control signal wirings and switching devices required by the amplifier circuit, effectively Reduce the area of the circuit layout.

FIG. 3 is a schematic diagram of a driving device 300 for a liquid crystal display according to an embodiment of the present invention. The amplifier circuit 100/200 of the present invention can be integrated into the driving device of the liquid crystal display. The driving device 300 may include a digital-to-analog converter 310 , an amplifier circuit 320 and 2 ^N reference voltage traces 330 . The reference voltage trace 330 is used for providing ^2N gamma reference voltages generated by a reference voltage generating circuit (not shown). The digital-to-analog converter 310 is coupled to the reference voltage trace 330, and is used for switching and outputting two adjacent reference voltages V1 and V2 from among ^2N gamma reference voltages according to a digital image signal S_DATA, wherein V1 and V2 can be provided to The amplifier circuit 320 serves as the above-mentioned input voltages VIH and VIL. The amplifier circuit 320 can be implemented by the amplifier circuit 100 / 200 of FIG. 1 or FIG. 2 for generating an output voltage Vo corresponding to the interpolation result according to the reference voltages V1 and V2 output by the digital-to-analog converter 310 .

Therefore, the amplifier circuit 320 with the interpolation function performs voltage interpolation according to its input voltage to generate 2 ^K interpolation voltages, the driving device 300 will eventually be equivalent to generating 2 ^(N+K) gamma reference voltages, wherein 2 ^K is the sum of the size ratio values of the transistor pairs of the input stage of the amplifier circuit. Compared with the prior art, the amplifier circuit 320 of the present invention can use fewer transistor pairs to achieve the same voltage interpolation function, thereby greatly reducing the number of control signal traces and switching devices required by the amplifier circuit, effectively Reduce the area of the circuit layout. In addition, the transistors in the input stage of the amplifier circuit of the present invention can all operate in the same operating region (eg, saturation region), so the present invention also has the advantage of being easy to design compared to the prior art. In addition, the voltage value interpolated by the method of the present invention can have better linearity, for example, the performance of integral nonlinearity (INL) and differential nonlinearity (DNL) can be excellent. on traditional technology. In addition, since the present invention adopts unequal ratio transistor size design, the amplifier circuit has larger size components, which can relatively weaken the influence of random mismatch between components on the whole circuit.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art to which the present invention belongs, under the premise of not departing from the concept of the present invention, several equivalent substitutions or obvious modifications can be made, and the performance or use is the same, which should be regarded as belonging to the present invention. protected range.

Claims (12)

1. An amplifier circuit with a voltage interpolation function, characterized in that it comprises a plurality of input pairs for receiving a first voltage and a second voltage, the plurality of input pairs being coupled to a voltage through an output stage. At the output end, the complex input pair includes at least: a first input pair, coupled between a ground point and a pair of nodes, including at least a first pair of transistors, the size of the first pair of transistors corresponding to a first ratio; and A second input pair, coupled between the ground point and the pair of nodes, includes at least a second pair of transistors, the size of the second pair of transistors corresponding to a second ratio, wherein the second ratio Not equal to the first ratio, the second ratio is a multiple of the first ratio, and a voltage output by the voltage output terminal is the first voltage and the second voltage passing through the first voltage. An interpolation result weighted by a ratio and the second ratio. 2. The amplifier circuit of claim 1, further comprising: A third input pair including at least a third pair of transistors, the size of the third pair of transistors corresponding to a third ratio, wherein the third ratio is not equal to the second ratio, and the third ratio is is a multiple of the first ratio and the second ratio, and the voltage output by the voltage output terminal is the first voltage and the second voltage through the first ratio, the second ratio and the the third ratio-weighted interpolation result. 3. The amplifier circuit of claim 1, wherein The first input pair further includes two input terminals: one input terminal is used to selectively receive the first voltage or the second voltage according to a first selection bit, and the other input terminal is coupled to the the voltage output terminal; The second input pair further includes two input terminals: one input terminal is used to selectively receive the first voltage or the second voltage according to a second selection bit, and the other input terminal is coupled to the the voltage output terminal. 4. The amplifier circuit of claim 1, wherein The first pair of transistors includes two input terminals: one input terminal is used to receive the first voltage, and the other input terminal is coupled to the voltage output terminal; The first input pair further includes a third pair of transistors, the size of the third pair of transistors corresponding to the first ratio; and the third pair of transistors includes two input terminals: one of the input terminals is used to receive For the second voltage, the other input terminal is coupled to the voltage output terminal. 5. The amplifier circuit of claim 1, wherein The second pair of transistors includes two input terminals: one input terminal is used to receive the first voltage, and the other input terminal is coupled to the voltage output terminal; The second input pair also includes a fourth pair of transistors, the size of the fourth pair of transistors corresponding to the second ratio; and the fourth pair of transistors includes two input terminals: one of the input terminals is used to receive For the second voltage, the other input terminal is coupled to the voltage output terminal. 6. An amplifier circuit with a voltage interpolation function, characterized in that it comprises a plurality of input pairs for receiving a first voltage and a second voltage, the plurality of input pairs being coupled to a voltage through an output stage. output, and the complex input pair includes at least: a first input pair, coupled between a ground point and a pair of nodes, including at least a first pair of transistors, the size of the first pair of transistors corresponding to a first ratio; a second input pair, coupled between the ground point and the pair of nodes, including at least a second pair of transistors, the size of the second pair of transistors corresponding to a second ratio; and A third input pair, coupled between the ground point and the pair of nodes, includes at least a third pair of transistors, the size of the third pair of transistors corresponding to a third ratio, wherein the first ratio , the second ratio and the third ratio are not equal to each other, and the voltage output by the voltage output terminal is the first voltage and the second voltage through the first ratio, the second ratio the result of the interpolation weighted with the third ratio. 7. The amplifier circuit of claim 6, wherein the third ratio is greater than the second ratio, the second ratio is greater than the first ratio, and the third ratio is the same as the first ratio Both ratios are multiples of the first ratio. 8. The amplifier circuit of claim 6, wherein The first input pair further includes two input terminals: one input terminal is used to selectively receive the first voltage or the second voltage according to a first selection bit, and the other input terminal is coupled to the the voltage output terminal; The second input pair further includes two input terminals: one input terminal is used to selectively receive the first voltage or the second voltage according to a second selection bit, and the other input terminal is coupled to the the voltage output terminal; The third input pair further includes two input terminals: one input terminal is used to selectively receive the first voltage or the second voltage according to a third selection bit, and the other input terminal is coupled to the the voltage output terminal. 9. The amplifier circuit of claim 6, wherein The first pair of transistors includes two input terminals: one input terminal is used to receive the first voltage, and the other input terminal is coupled to the voltage output terminal; The first input pair also includes a fourth pair of transistors, the size of the fourth pair of transistors corresponding to the first ratio, and the fourth pair of transistors includes two input terminals: one input terminal for receiving For the second voltage, the other input terminal is coupled to the voltage output terminal. 10. The amplifier circuit of claim 6, wherein The second pair of transistors includes two input terminals: one input terminal is used to receive the first voltage, and the other input terminal is coupled to the voltage output terminal; The second input pair also includes a fifth pair of transistors, the size of the fifth pair of transistors corresponding to the second ratio, and the fifth pair of transistors includes two inputs: one input for receiving For the second voltage, the other input terminal is coupled to the voltage output terminal. 11. The amplifier circuit of claim 6, wherein The third pair of transistors includes two input terminals: one input terminal is used to receive the first voltage, and the other input terminal is coupled to the voltage output terminal; The third input pair also includes a sixth pair of transistors, the size of the sixth pair of transistors corresponding to the third ratio, and the sixth pair of transistors includes two input terminals: one input terminal for receiving For the second voltage, the other input terminal is coupled to the voltage output terminal. 12. A driving device for a liquid crystal display, wherein the driving device comprises the amplifier circuit of claim 1 or 6, wherein the amplifier circuit is integrated into the driving device.

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