CN109889026B

CN109889026B - Power device and electric appliance

Info

Publication number: CN109889026B
Application number: CN201910211275.2A
Authority: CN
Inventors: 冯宇翔
Original assignee: Midea Group Co Ltd; GD Midea Air Conditioning Equipment Co Ltd
Current assignee: Midea Group Co Ltd; GD Midea Air Conditioning Equipment Co Ltd
Priority date: 2019-03-20
Filing date: 2019-03-20
Publication date: 2020-10-30
Anticipated expiration: 2039-03-20
Also published as: WO2020186733A1; CN109889026A

Abstract

The application discloses power device and electrical apparatus. The power device comprises a control input end, an upper bridge arm switch tube, a lower bridge arm switch tube, an upper resistor group, a lower resistor group, a first drive circuit which is connected with the control input end and is connected with the upper bridge arm switch tube through the upper resistor group, and a second drive circuit which is connected with the control input end and is connected with the lower bridge arm switch tube through the lower resistor group. The control input can be switched in a first level, a second level or a third level. When the control input end is connected with a first level, the first driving circuit and the second driving circuit output high and low levels of a first voltage range. When the control input end is connected with a second level, the first driving circuit and the second driving circuit output high and low levels of a second voltage range. When the control input end is connected to a third level, the first driving circuit and the second driving circuit output high and low levels of a third voltage range. The first voltage range, the second voltage range, and the third voltage range are different. This can improve the suitability of silicon, gallium nitride and silicon carbide power devices.

Description

Power device and electric appliance

Technical Field

The application relates to the technical field of electric appliances, in particular to a power device and an electric appliance.

Background

In the prior art, with the continuous improvement of the requirement on the energy consumption of the system, the power consumption of an Intelligent Power Module (IPM) becomes a main source of the variable frequency electric control power consumption of the inverter air conditioner, and how to reduce the power consumption of the intelligent power Module becomes an important subject influencing the further popularization and application of the intelligent power Module and even the inverter air conditioner. The replacement of Si devices by GaN devices or SiC devices is an effective way to reduce the power consumption of smart power modules, but also brings new problems therewith.

The threshold voltage (3V) of the GaN device, the threshold voltage (20V) of the SiC device, and the threshold voltage (15V) of the Si device are different. The threshold voltage of the GaN device is lower than that of the Si device, and if the same High Voltage Integrated Circuit (HVIC) transistor is used for driving, the gate of the GaN device is easily broken down; the threshold voltage of the SiC device is higher than that of the Si device, and if the same high-voltage integrated circuit tube is adopted for driving, the opening process of the SiC device is not thorough easily, and the low power consumption advantage of the SiC device cannot be exerted. However, if different high-voltage integrated circuit tubes are used for driving, difficulty in material organization in the production process is caused, material mixing risks exist, and the cost of the intelligent power module is also increased. Moreover, if the high-voltage integrated circuit tube driving the Si device is powered by a lower voltage to ensure that the GaN device is not broken down, the power consumption of the entire Si device intelligent power module is also easily increased, and even the Si device cannot work normally.

Disclosure of Invention

The embodiment of the application provides a power device and an electric appliance.

The power device comprises a control input end, an upper bridge arm switching tube, a lower bridge arm switching tube, an upper resistor group, a lower resistor group, a first driving circuit and a second driving circuit, wherein the first driving circuit is connected with the control input end and is connected with the upper bridge arm switching tube through the upper resistor group; the control input can be switched in a first level, a second level or a third level. When the control input end is connected with a first level, the first driving circuit and the second driving circuit output high and low levels of a first voltage range. When the control input end is connected to the second level, the first driving circuit and the second driving circuit output the high-low level of the second voltage range. When the control input end is connected to a third level, the first driving circuit and the second driving circuit output high and low levels of a third voltage range. The first voltage range, the second voltage range, and the third voltage range are different.

The electric appliance of the embodiment of the application comprises the power device and the processor, wherein the processor is connected with the power device.

In certain embodiments, the appliance is an air conditioner.

The power device and the electric appliance can output high-low level signals in different voltage ranges to adapt to the use requirements of different types of devices (such as GaN devices, SiC devices and Si devices) on the premise of not changing external input voltage, the conduction processes of the different types of devices are in a complete conduction state and cannot cause breakdown, and the performance of the different types of devices is fully exerted. And because the same first drive circuit and second drive circuit just can realize exporting the high-low level signal of different voltage ranges, do not have the compounding risk in the production process of power device, the material organization of being convenient for reduces material cost. In addition, the upper resistor group and the lower resistor group can respectively control the first driving circuit and the second driving circuit to be switched on and off, so that reliable switching on and switching off of different types of devices are guaranteed.

Additional aspects and advantages of embodiments of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of embodiments of the present application.

Drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a circuit block diagram of a power device according to some embodiments of the present application;

FIG. 2 is a schematic diagram of a power device according to some embodiments of the present application with a control input connected to a power supply or ground via a bonding line;

fig. 3 is a block schematic diagram of a power device according to an embodiment of the present application;

fig. 4 to 11 are schematic structural diagrams of upper and lower bridge arm switching tubes according to some embodiments of the present disclosure;

FIG. 12 is a schematic diagram of a UH driver circuit in accordance with certain embodiments of the present application;

FIG. 13 is a schematic diagram of a VH drive circuit according to some embodiments of the present application;

figure 14 is a schematic diagram of a WH driver circuit according to certain embodiments of the present application;

FIG. 15 is a schematic diagram of a UL/VL/WL driver circuit according to some embodiments of the present application;

FIG. 16 is a block diagram of an appliance according to certain embodiments of the present application.

Detailed Description

Embodiments of the present application will be further described below with reference to the accompanying drawings. The same or similar reference numbers in the drawings identify the same or similar elements or elements having the same or similar functionality throughout.

In addition, the embodiments of the present application described below in conjunction with the accompanying drawings are exemplary and are only for the purpose of explaining the embodiments of the present application, and are not to be construed as limiting the present application.

Referring to fig. 1, the power device 100 according to the present embodiment includes a control input terminal SS, an upper bridge arm switch tube 127, a lower bridge arm switch tube 128, an upper resistor group 134, a lower resistor group 135, a first driving circuit 129 connected to the control input terminal SS and connected to the upper bridge arm switch tube 127 through the upper resistor group 134, and a second driving circuit 120 connected to the control input terminal SS and connected to the lower bridge arm switch tube 128 through the lower resistor group 135. The control input SS can be switched to a first level, a second level or a third level. When the control input SS is connected to the first level, the first driving circuit 129 and the second driving circuit 120 output high-low level signals of the first voltage range. When the control input SS is switched to the second level, the first driving circuit 129 and the second driving circuit 120 output high-low level signals of the second voltage range. When the control input SS is connected to the third level, the first driving circuit 129 and the second driving circuit 120 output high-low level signals of the third voltage range. The first voltage range, the second voltage range, and the third voltage range are different.

The power device 100 of the present application can output high and low level signals with different voltage ranges to meet the use requirements of different types of devices (such as GaN devices, SiC devices, and Si devices) without changing the external input voltage, the conduction processes of the different types of devices are all in a complete conduction state and cannot cause breakdown, and the performance of the device is fully exerted. And because the same first drive circuit and the same second drive circuit are adopted, high-low level signals in different voltage ranges can be output, no material mixing risk exists in the production process of the power device 100, the material organization is facilitated, and the material cost is reduced. In addition, the upper resistor group 134 and the lower resistor group 135 can respectively control the first driving circuit 129 and the second driving circuit 120 to be switched on and off, so that reliable switching on and switching off of different types of devices are guaranteed.

Referring to fig. 1, in some embodiments, the first driving circuit 129 includes a UH driving circuit 101, a VH driving circuit 102, and a WH driving circuit 103; the second driver circuit 120 includes a UL/VL/WL driver circuit 104. In this embodiment, the UH driver circuit 101, the VH driver circuit 102, the WH driver circuit 103, and the UL/VL/WL driver circuit 104 may be driver circuits in the electric appliance 1000, for example, three-phase driver circuits of a compressor of an air conditioner, wherein the UL/VL/WL driver circuit 104 includes the UL driver circuit, the VL driver circuit, and the WL driver circuit, the UH driver circuit 101 is connected to the UL driver circuit, the VH driver circuit 102 is connected to the VL driver circuit, and the WH driver circuit 103 is connected to the WL driver circuit.

The upper bridge arm switching tube 127 includes a first upper bridge arm switching tube 121, a second upper bridge arm switching tube 122, and a third upper bridge arm switching tube 123. The lower bridge arm switching tubes 128 include a first lower bridge arm switching tube 124, a second lower bridge arm switching tube 125 and a third lower bridge arm switching tube 126. The upper resistor group 134 includes a first gate-on resistor H-RON1, a second gate-on resistor H-RON2, a third gate-on resistor H-RON3, a first gate-off resistor H-ROFF1, a second gate-off resistor H-ROFF12, and a third gate-off resistor H-ROFF 3. One end of each of the H-RON1 and the H-ROFF1 is connected with the UH driving circuit 101, and the other end of each of the H-RON1 and the H-ROFF1 is connected with a control electrode of the first upper bridge arm switching tube 121 to control the on and off of the first upper bridge arm switching tube 121. One end of each of the H-RON2 and the H-ROFF2 is connected with the VH drive circuit 102, and the other end is connected with the control electrode of the second upper bridge arm switch tube 122 to control the on and off of the second upper bridge arm switch tube 122. One end of each of the H-RON3 and the H-ROFF3 is connected with the WH driving circuit 103, and the other end of each of the H-RON3 and the H-ROFF3 is connected with a control electrode of the third upper bridge arm switching tube 123 to control the third upper bridge arm switching tube 123 to be switched on and off. The lower resistor group 135 includes a fourth gate-on resistor L-RON1, a fifth gate-on resistor L-RON2, a sixth gate-on resistor L-RON3, a fourth gate-off resistor L-ROFF1, a fifth gate-off resistor L-ROFF2, and a sixth gate-off resistor L-ROFF 3. One end of the L-RON1 and one end of the L-ROFF1 are connected with the UL/VL/WL driving circuit 104, and the other end of the L-RON1 and the L-ROFF1 are connected with the control electrode of the first lower bridge arm switching tube 124 so as to control the first lower bridge arm switching tube 124 to be switched on and switched off. One end of the L-RON2 and one end of the L-ROFF2 are connected with the UL/VL/WL driving circuit 104, and the other end of the L-RON2 and the L-ROFF2 are connected with the control electrode of the second lower bridge arm switch tube 125 to control the on and off of the second lower bridge arm switch tube 125. One end of the L-RON3 and one end of the L-ROFF3 are connected with the UL/VL/WL driving circuit 104, and the other end of the L-RON3 and the L-ROFF3 are connected with the control electrode of the third lower bridge arm switch tube 126 to control the on and off of the third lower bridge arm switch tube 126. The control input end SS is connected to the UH driving circuit 101, the VH driving circuit 102 and the WH driving circuit 103, and the UH driving circuit 101, the VH driving circuit 102 and the WH driving circuit 103 respectively drive the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122 and the third upper bridge arm switching tube 123. The UH driving circuit 101 is connected with a first upper bridge arm switch tube 121, the VH driving circuit 102 is connected with a second upper bridge arm switch tube 122, and the WH driving circuit 103 is connected with a third upper bridge arm switch 123; the control input end SS is connected with the UL/VL/WL driving circuit 104, the UL/VL/WL driving circuit 104 drives the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125 and the third lower bridge arm switching tube 126, and the UL/VL/WL driving circuit 104 is connected with the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125 and the third lower bridge arm switching tube 126 respectively.

Wherein the first level is a power supply level VCC, the second level is 0, and the third level is a half power supply level VCC (i.e., VCC/2); the first voltage range is 0V to-3V, the second voltage range is 0V to 15V, and the third voltage range is 0V to 20V.

More, the power device 100 further includes a VCC terminal, a GND terminal, and a reference power terminal Vreg, and when the control input terminal SS is connected to the VCC terminal through a bonding wire (shown in fig. 2), the control input terminal SS is connected to a first level; when the control input terminal SS is connected with the GND terminal through the bonding line 115, the control input terminal SS is connected to the second level; when the control input terminal SS is connected to the reference power source terminal Vreg through the bonding line 115, the control input terminal SS is switched in the third level.

Specifically, referring to fig. 1, a UH driver circuit 101, a VH driver circuit 102, a WH driver circuit 103, and a UL/VL/WL driver circuit 104 are integrated inside an HVIC tube 111, a VCC terminal of the HVIC tube 111 is used as a positive terminal VDD of a low-voltage power supply of the power device 100, and the VDD is generally 15V; inside the HVIC tube 111, the VCC terminal is connected to the positive terminals of the power supplies of the UH driver circuit 101, the VH driver circuit 102, the WH driver circuit 103, the UL/VL/WL driver circuit 104, and the positive terminal of the power supply of the reference power supply terminal Vreg; here, the reference power source terminal Vreg is a voltage source having a voltage value VCC/2 generated inside the HVIC tube 111.

The HIN1 end of the HVIC tube 111 is used as the U-phase upper bridge arm input end UHIN of the power device 100 and is connected with the input end of the UH drive circuit 101 in the HVIC tube 111; the HIN2 end of the HVIC tube 111 is used as a V-phase upper bridge arm input end VHIN of the power device 100 and is connected with the input end of the VH driving circuit 102 inside the HVIC tube 111; the HIN3 end of the HVIC tube 111 serves as the W-phase upper bridge arm input end WHIN of the power device 100, and is connected with the input end of the WH driving circuit 103 inside the HVIC tube 111; the LIN1 end of the HVIC tube 111 serves as the U-phase lower bridge arm input end ULINs of the power device 100, and is connected to the first input end of the UL/VL/WL driver circuit 104 inside the HVIC tube 111; the LIN2 end of the HVIC tube 111 serves as the V-phase lower bridge arm input end VLIN of the power device 100, and is connected to the second input end of the UL/VL/WL driver circuit 104 inside the HVIC tube 111; the LIN3 terminal of the HVIC transistor 111 serves as the W-phase lower arm input terminal WLIN of the power device 100, and is connected to the third input terminal of the UL/VL/WL driver circuit 104 inside the HVIC transistor 111. Here, the U, V, W three-phase six-input of the power device 100 receives either a 0V or 5V input signal.

The GND terminal of the HVIC tube 111 serves as a low-voltage power supply negative terminal COM of the power device 100, and is connected to the power supply negative terminals of the UH driver circuit 101, the VH driver circuit 102, the WH driver circuit 103, and the UL/VL/WL driver circuit 104. The VB1 terminal of the HVIC tube 111 is connected to the positive terminal of the high-voltage region power supply of the UH driver circuit 101 inside the HVIC tube 111, and one terminal of the capacitor 131 is connected to the outside of the HVIC tube 111, and serves as the positive terminal of the U-phase high-voltage region power supply of the power device 100. The high level output terminal (i.e., the terminal P-HO 1) and the low level output terminal (i.e., the terminal N-HO 1) of the UH driver circuit 101 are connected to the first gate-on resistor H-RON1 and the first gate-off resistor H-ROFF1, respectively, outside the HVIC tube 111. The VS1 end of the HVIC tube 111 is connected to the negative end of the high-voltage region power supply of the UH driver circuit 101 inside the HVIC tube 111, and is connected to the output negative electrode of the first upper arm switch tube 121, the output positive electrode of the first lower arm switch tube 124, and the other end of the capacitor 131 outside the HVIC tube 111, and serves as the negative end UVS of the U-phase high-voltage region power supply of the power device 100.

The VB2 terminal of the HVIC tube 111 is connected to the positive terminal of the high-voltage power supply of the VH driver circuit 102 inside the HVIC tube 111, and one terminal of the capacitor 132 is connected to the outside of the HVIC tube 111 as the positive terminal of the U-phase high-voltage power supply of the power device 100. The high level output terminal (i.e., the terminal P-HO 2) and the low level output terminal (i.e., the terminal N-HO 2) of the VH driver circuit 102 are connected to the second gate-on resistor H-RON2 and the second gate-off resistor H-ROFF2, respectively, outside the HVIC tube 111. The VS2 end of the HVIC tube 111 is connected to the negative end of the high-voltage region power supply of the VH driving circuit 102 inside the HVIC tube 111, and is connected to the negative output electrode of the upper arm power tube 122, the positive output electrode of the second lower arm switching tube 125, and the other end of the capacitor 132 outside the HVIC tube 111, and serves as the negative W-phase high-voltage region power supply terminal VVS of the power device 100.

The VB3 terminal of the HVIC tube 111 is connected to the positive terminal of the high voltage region power supply of the WH driver circuit 103 inside the HVIC tube 111, and one terminal of the capacitor 133 is connected outside the HVIC tube 111 as the positive terminal of the W-phase high voltage region power supply of the power device 100. The high level output terminal (i.e., the terminal P-HO 3) and the low level output terminal (i.e., the terminal N-HO 3) of the WH driving circuit 103 are connected to the third gate-on resistor H-RON3 and the second gate-off resistor H-ROFF3, respectively, outside the HVIC transistor 111. The VS3 end of the HVIC tube 111 is connected to the negative end of the high voltage region power supply of the WH drive circuit 103 inside the HVIC tube 111, and is connected to the output negative electrode of the power tube 123, the output positive electrode of the third lower arm switch tube 126, and the other end of the capacitor 133 outside the HVIC tube 111, and serves as the negative end WVS of the W-phase high voltage region power supply of the power device 100.

UL/VL/WL driver circuit 104 includes a second output sub-circuit 1042, a third output sub-circuit 1043, and a fourth output sub-circuit 1044. The high level output terminal (i.e., the P-LO1 terminal) and the low level output terminal (i.e., the N-LO1 terminal) of the second output sub-circuit 1042 are connected to the fourth gate-on resistor H-RON4 and the fourth gate-off resistor H-ROFF4, respectively, outside the HVIC tube 111. The high level output terminal (i.e., P-LO2) and the low level output terminal (N-LO2) of the third output sub-circuit 1043 are connected to the fifth gate-on resistor H-RON5 and the fifth gate-off resistor H-ROFF5, respectively, outside the HVIC tube 111. The high level output terminal (i.e., P-LO3) and the low level output terminal (N-LO3) of the fourth output sub-circuit 1044 are connected to the sixth gate-on resistor H-RON6 and the sixth gate-off resistor H-ROFF6, respectively, outside the HVIC 111. The output cathode of the first lower bridge arm switching tube 124 is used as a U-phase low-voltage reference end UN of the power device 100; the output cathode of the second lower bridge arm switching tube 125 is used as a V-phase low-voltage reference end VN of the power device 100; the output cathode of the third lower bridge arm switching tube 126 serves as a W-phase low-voltage reference terminal WN of the power device 100; the output positive electrode of the first upper bridge arm switching tube 121, the output positive electrode of the second upper bridge arm switching tube 122 and the output positive electrode of the third upper bridge arm switching tube 123 are connected to each other, and serve as a high-voltage input end P of the power device 100, and P is generally connected to 300V. In this embodiment, the supply voltage of VDD is 15V.

In this embodiment, the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125, and the third lower bridge arm switching tube 126 may be a combination of a Si IGBT tube (i.e., Si device) and a Si FRD tube (Fast recovery Diode) connected in parallel, a combination of a Si IGBT tube and a GaN SBD (Schottky Barrier Diode) tube, a GaN MOS tube (Metal Oxide Semiconductor, i.e., GaN device), a combination of a GaN MOS tube and a FRD tube, or a combination of a GaN MOS tube and a GaN SBD tube; the transistor may be a combination of a Si IGBT tube and a SiC SBD tube, a SiC MOS tube (i.e., SiC device), a combination of a SiC MOS tube and an FRD tube, or a combination of a SiCMOS tube and a SiC SBD tube.

In the power device 100, the HVIC tube 111 functions to: when the control input SS is VCC level, P-HO 1-P-HO 3, N-HO 1-N-HO 3, P-LO 1-P-LO 3, and N-LO 1-N-LO 3 output high and low level signals of 0V-3V, that is, when the control input SS is first level, the UH driver 101, VH driver 102, WH driver 103, and UL/VL/WL driver 104 output high and low level signals of a first voltage range; when the level of the control input terminal SS is 0, P-HO 1-P-HO 3, N-HO 1-N-HO 3, P-LO 1-P-LO 3, and N-LO 1-N-LO 3 output high-low level signals of 0V-15V, that is, when the control input terminal SS is a second level, the UH driving circuit 101, the VH driving circuit 102, the WH driving circuit 103, and the UL/VL/WL driving circuit 104 output high-low level signals of a second voltage range; when the control input SS is VCC/2 level, P-HO 1-P-HO 3, N-HO 1-N-HO 3, P-LO 1-P-LO 3, and N-LO 1-N-LO 3 output high and low level signals of 0V-20V, that is, when the control input SS is third level, the UH driver 101, VH driver 102, WH driver 103, and UL/VL/WL driver 104 output high and low level signals of a third voltage range.

In practical applications, referring to fig. 1 and fig. 2, the power device 100 includes a first connection portion 116, a second connection portion 117, and an SSS terminal, wherein the first connection portion 116 is used to connect the VCC terminal and the VDD terminal, the second connection portion 117 is used to connect the GND terminal and the COM terminal, and the SSS terminal is used to connect the SS terminal and the reference power source terminal Vreg. The first connection portion 116 and the second connection portion 117 may be wires, electrodes, or the like having a conductive transmission function.

Specifically, when the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125 and the third lower bridge arm switching tube 126 all include GaN devices (the GaN devices are GaN MOS tubes 1211 shown in fig. 4 to 6, for example, the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125 and the third lower bridge arm switching tube 126 are all in the GaN MOS tube 1211 shown in fig. 4, or the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125 and the third lower bridge arm switching tube 126 are all in the GaN tube 1211 and Si FRD tube 1212 shown in fig. 5, or the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the second upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second, The second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125, and the third lower bridge arm switching tube 126 are all GaN MOS tube 1211 and GaN SBD tube 1212 shown in fig. 6, or a combination of GaN MOS tube 1211 and SiC SBD tube 1212), inside the power device 100, the SSS end is connected to the VCC end through the bonding wire 115, the control input end SS is connected to the first level, and the first driving circuit 129 and the second driving circuit 120 output high-low level signals within the first voltage range.

When the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125 and the third lower bridge arm switching tube 126 all include Si devices (the Si devices are Si IGBT tubes 1211 shown in fig. 7 to 8; for example, the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125 and the third lower bridge arm switching tube 126 are all in a combination manner of the Si IGBT tube 1211 and the Si FRD tube 1212 shown in fig. 7; or the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125 and the third lower bridge arm switching tube 126 are all in a combination manner of the Si tube 1211 and the GaN SBD tube 1212 shown in fig. 8, or a combination manner of the Si tube 1211 and the SBD tube 1212), in the power device 100, the control input terminal SS is connected to the GND terminal through the bonding line 115, the control input terminal SS is connected to the second level, and the first driving circuit 129 and the second driving circuit 120 output high and low level signals in the second voltage range.

When the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125 and the third lower bridge arm switching tube 126 all include SiC devices (the SiC devices are SiC MOS tubes 1211 shown in fig. 9 to 11, for example, the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125 and the third lower bridge arm switching tube 126 are SiC MOS tubes 1211 shown in fig. 9, or the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125 and the third lower bridge arm switching tube 126 are combination of the SiCMOS tubes 1211 and the FRD tubes 1212 shown in fig. 10, or the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower, The second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125 and the third lower bridge arm switching tube 126 are all in a combination mode of a SiC MOS tube 1211 and a SiC SBD tube 1212 or a GaNSBD tube 1212 shown in fig. 11), in the power device 100, the SSS end is connected with the reference power supply end Vreg through the bonding wire 115, the control input end SS is connected to the third level, and the first driving circuit 129 and the second driving circuit 120 output high-low level signals in the third voltage range;

as can be seen from the above, the power supply voltage of the power device 100 according to the embodiment of the present disclosure is 15V, and the power consumption of the HVIC tube 111 is not substantially increased; the driving GaN device, the driving Si device and the driving SiC device are the same HVIC tube 111, no material mixing risk exists in the production process, material organization is facilitated, and material cost is reduced; the GaN device is driven to use 3V voltage, the Si device is driven to use 15V voltage, the SiC device is driven to use 20V voltage, the GaN device, the SiC device and the Si device are in a complete conduction state in the conduction process, meanwhile, breakdown cannot be caused, and the respective performances are exerted.

Referring to fig. 1 and fig. 3, in some embodiments, the power device 100 includes a controller 130, the control input terminal SS is connected to the controller 130, and the controller 130 is configured to control the control input terminal SS to access the first level, the second level or the third level.

The controller 130 may be a digital circuit including a circuit for outputting the first level, the second level, or the third level, and may include a flip-flop, etc., but is not limited thereto. The controller 130 may be mounted inside the HVIC tube 111, for example, between the control input SS and SSs terminals or elsewhere. The controller 130 may also be mounted outside the HVIC tube 111, such as near the control input SS or elsewhere. Or the controller 130 is mounted on a microprocessor of the appliance.

Fig. 4 to 11 show a combination manner of the upper arm switching tube 127 and the lower arm switching tube 128, where the first upper arm switching tube 121, the second upper arm switching tube 122, the third upper arm switching tube 123, the first lower arm switching tube 124, the second lower arm switching tube 125, and the third lower arm switching tube 126 are completely identical in structure, and the first upper arm switching tube 121 is taken as an example to explain:

the first upper arm switch transistor 121 shown in fig. 4 is a GaN MOS transistor 1211: the drain of the GaN MOS tube 1211 is used as the output anode of the first upper arm switch tube 121; the source of the GaN MOS 1211 is used as the output cathode of the first upper arm switch tube 121; the gate of GaN MOS 1211 is used as the gate of first upper arm switch transistor 121.

The first upper arm switch tube 121 shown in fig. 5 is a combination of a GaN MOS tube 1211 and a Si FRD tube 1212: the drain electrode of the GaN MOS tube 1211 is connected to the cathode of the Si FRD tube 1212, and serves as the output anode of the first upper bridge arm switching tube 121; the source electrode of the GaN MOS tube 1211 is connected to the anode of the Si FRD tube 1212, and serves as the output cathode of the first upper bridge arm switching tube 121; the gate of GaN MOS 1211 is used as the gate of first upper arm switch transistor 121.

The first upper bridge arm switch tube 121 of fig. 6 includes the following combination: (1) a GaN MOS tube 1211 and a GaN SBD tube 1212, wherein a drain of the GaN MOS tube 1211 is connected to a cathode of the GaN SBD tube 1212, and is used as an output anode of the first upper arm switch tube 121; the source of the GaN MOS tube 1211 is connected to the anode of the GaN SBD tube 1212, and is used as the output cathode of the first upper bridge arm switching tube 121; the grid of the GaN MOS tube 1211 is used as the control electrode of the first upper bridge arm switching tube 121; (2) a GaN MOS tube 1211 and a SiC SBD tube 1212, wherein a drain of the GaN MOS tube 1211 is connected to a cathode of the SiCSBD tube 1212, and is used as an output anode of the first upper arm switching tube 121; the source of the GaN MOS tube 1211 is connected to the anode of the SiC SBD tube 1212, and serves as the output cathode of the first upper bridge arm switching tube 121; the gate of GaN MOS 1211 is used as the gate of first upper arm switch transistor 121.

The first upper arm switching tube 121 shown in fig. 7 is a combination of the Si IGBT tube 1211 and the Si FRD tube 1212: the collector of the Si IGBT tube 1211 is connected to the cathode of the Si FRD tube 1212, and serves as the output anode of the first upper arm switching tube 121; an emitter of the Si IGBT tube 1211 is connected to an anode of the Si FRD tube 1212, and serves as an output cathode of the first upper bridge arm switching tube 121; the gate of the Si IGBT tube 1211 serves as the control electrode of the first upper arm switching tube 121.

The first upper bridge arm switch tube 121 shown in fig. 8 includes the following combination: (1) a combination mode of a Si IGBT tube 1211 and a GaNSBD tube 1212, wherein a collector electrode of the Si IGBT tube 1211 is connected with a cathode of the GaN SBD tube 1212 and is used as an output anode of the first upper arm switch tube 121; the emitter of the Si IGBT tube 1211 is connected to the anode of the GaN SBD tube 1212, and serves as the output cathode of the first upper bridge arm switching tube 121; the grid electrode of the Si IGBT 1211 serves as the control electrode of the first upper arm switching tube 121; (2) a combination mode of the Si IGBT 1211 and the SiC SBD tube 1212, wherein cathodes of the Si IGBT 1211 and the SiC SBD tube 1212 are connected and serve as an output anode of the first upper arm switching tube 121; an emitter of the Si IGBT tube 1211 is connected with an anode of the Si SBD tube and serves as an output cathode of the first upper bridge arm switching tube 121; the gate of the Si IGBT tube 1211 serves as the control electrode of the first upper arm switching tube 121.

The first upper arm switching transistor 121 shown in fig. 9 is a SiC MOS transistor 1211: the drain electrode of the SiC MOS tube 1211 serves as the output positive electrode of the first upper arm switching tube 121; the source of the SiC MOS tube 1211 is used as the output cathode of the first upper arm switch tube 121; the gate of the SiC MOS transistor 1211 serves as the control electrode of the first upper arm switching transistor 121.

The first upper arm switching tube 121 shown in fig. 10 is a combination of the SiC MOS tube 1211 and the Si FRD tube 1212: the drain electrode of the SiC MOS tube 1211 is connected to the cathode of the Si FRD tube 1212, and serves as the output anode of the first upper bridge arm switching tube 121; the source of the SiC MOS tube 1211 is connected to the anode of the Si FRD tube 1212, and serves as the output negative electrode of the first upper bridge arm switching tube 121; the gate of the SiC MOS transistor 1211 serves as the control electrode of the first upper arm switching transistor 121.

The first upper arm switch tube 121 shown in fig. 11 includes the following combination: (1) a combination mode of the SiC MOS tube 1211 and the SiCSBD tube 1212, wherein a drain of the SiC MOS tube 1211 is connected to a cathode of the SiC SBD tube 1212, and serves as an output anode of the first upper arm switching tube 121; the source of the SiC MOS tube 1211 is connected to the anode of the SiC SBD tube 1212, and serves as the output cathode of the first upper bridge arm switching tube 121; the gate of the SiC MOS tube 1211 serves as the control electrode of the first upper arm switching tube 121; (2) a combination mode of the SiC MOS tube 1211 and the GaN SBD tube 1212, wherein a drain of the SiC MOS tube 1211 is connected to a cathode of the GaN SBD tube 1212, and serves as an output anode of the first upper arm switch tube 121; the source of the SiC MOS tube 1211 is connected to the anode of the GaN SBD tube 1212, and serves as the output cathode of the first upper bridge arm switching tube 121; the gate of the SiC MOS transistor 1211 serves as the control electrode of the first upper arm switching transistor 121.

It is understood that the second upper bridge arm switch tube 122 can be any one of the switch tubes shown in fig. 4 to 11; the third upper bridge arm switching tube 123 may be any one of the switching tubes shown in fig. 4 to 11; the first lower arm switch tube 124 may be any one of the switch tubes shown in fig. 4 to 11; the second lower arm switch tube 125 may be a switch tube in any one combination manner shown in fig. 4 to 11; the third lower arm switch tube 126 may be any one of the switch tubes shown in fig. 4 to 11.

The above-described configurations of the first upper arm switching tube 121, the second upper arm switching tube 122, the third upper arm switching tube 123, the first lower arm switching tube 124, the second lower arm switching tube 125, and the third lower arm switching tube 126 are the same as each other: in the actual power device 100, all of the first upper arm switching tube 121, the second upper arm switching tube 122, the third upper arm switching tube 123, the first lower arm switching tube 124, the second lower arm switching tube 125, and the third lower arm switching tube 126 are GaN MOS type switching tubes as shown in fig. 4; or, the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125, and the third lower bridge arm switching tube 126 are all switching tubes of a combination mode of GaN MOS and Si FRD shown in fig. 5; or, all of the first upper arm switching tube 121, the second upper arm switching tube 122, the third upper arm switching tube 123, the first lower arm switching tube 124, the second lower arm switching tube 125, and the third lower arm switching tube 126 are switching tubes of a combination mode of a GaN MOS tube and a GaN SBD tube shown in fig. 6, or switching tubes of a combination mode of a GaN MOS tube and a SiC SBD tube; or, the first upper bridge arm switching tube 121, the second upper bridge arm switching tube 122, the third upper bridge arm switching tube 123, the first lower bridge arm switching tube 124, the second lower bridge arm switching tube 125, and the third lower bridge arm switching tube 126 are all switching tubes of a combination mode of the Si IGBT and the SiFRD shown in fig. 7; or, all of the first upper arm switching tube 121, the second upper arm switching tube 122, the third upper arm switching tube 123, the first lower arm switching tube 124, the second lower arm switching tube 125, and the third lower arm switching tube 126 are switching tubes of a combination manner of a Si IGBT tube and a GaN SBD tube shown in fig. 8, or switching tubes of a combination manner of a Si IGBT tube and a SiC SBD tube; alternatively, the first upper arm switching tube 121, the second upper arm switching tube 122, the third upper arm switching tube 123, the first lower arm switching tube 124, the second lower arm switching tube 125, and the third lower arm switching tube 126 are all SiC MOS type switching tubes shown in fig. 9; or, all of the first upper arm switching tube 121, the second upper arm switching tube 122, the third upper arm switching tube 123, the first lower arm switching tube 124, the second lower arm switching tube 125, and the third lower arm switching tube 126 are switching tubes of a combination method of SiC MOS and SiFRD shown in fig. 10; alternatively, all of the first upper arm switching tube 121, the second upper arm switching tube 122, the third upper arm switching tube 123, the first lower arm switching tube 124, the second lower arm switching tube 125, and the third lower arm switching tube 126 are switching tubes of a combination type of SiC MOS and SiC SBD tubes or a combination type of SiC MOS and GaN SBD tubes shown in fig. 11.

Referring to fig. 12 to 14, fig. 12, 13 and 14 are embodiments of a UH driver circuit 101, a VH driver circuit 102 and a WH driver circuit 103, respectively. In the following, the UH driver circuit 101 is taken as an example for explanation, and the structures of the VH driver circuit 102 and the WH driver circuit 103 are completely the same as those of the UH driver circuit 101, and are not described again here.

Referring to fig. 12, in some embodiments, the UH driver circuit 101 includes: a first input sub-circuit 1011, a first switch tube 1012, a second switch tube 1013, a third switch tube 1014, a fourth switch tube 1021, a first output sub-circuit 1017, a first voltage output sub-circuit 1023 and a second voltage output sub-circuit 1024. The first input sub-circuit 1011 is connected to the control input SS. The first input sub-circuit 1011 includes a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. When the control input end SS is at a first level, the first output end and the second output end output trigger pulses, and the third output end outputs trigger pulses with a first time length; when the control input end SS is at a second level, the first output end and the second output end output trigger pulses, the third output end outputs trigger pulses of a second time length, and the first time length is greater than the second time length; when the control input terminal SS is at the third level, the first output terminal and the second output terminal output the trigger pulse, and the fourth output terminal outputs the trigger pulse of the second time length.

The first switch tube 1012 is connected to the first output end, and when the first output end outputs a trigger pulse, the first switch tube 1012 is turned on; the second switching tube 1013 is connected to the second output end, and when the second output end outputs the trigger pulse, the second switching tube 1013 is turned on; the third switch tube 1014 is connected to the third output terminal, and when the third output terminal outputs a trigger pulse, the third switch 1014 is turned on; the fourth switch tube 1021 is connected to the fourth output end, and when the fourth output end outputs the trigger pulse, the fourth switch tube 1021 is turned on.

The first voltage output sub-circuit 1023 is connected to the first switch tube 1012, the second switch tube 1013 and the third switch tube 1014 respectively; the second voltage output sub-circuit 1024 is connected with the fourth switch tube 1021; the first output sub-circuit 1017 is connected to the first voltage output sub-circuit 1023 and the second voltage output sub-circuit 1024, respectively.

With continued reference to fig. 12, in some embodiments, the first voltage output sub-circuit 1023 includes a latch and buck circuit 1016 connected to the first switch 1012 and the second switch 1013, a first switch module 1018, and a first latch circuit 1015 connected to the third switch 1014. The first switching module 1018 is connected to the latch and buck circuit 1016 and the power supply, respectively. When the third switch 1014 is not turned on, the first voltage output sub-circuit 1023 is not connected to the first output sub-circuit 1017 (i.e., the first switching module 1018 is in a floating state, i.e., the fixed end of the first switching module 1018 is neither connected to the 1 selection terminal nor the 0 selection terminal); when the third switch 1014 is turned on for a first time period (i.e., when the control input SS is at a first level), the first latch circuit 1015 is configured to control the first switching module 1018 to operate to connect the latch and voltage-dropping circuit 1016 to the first output sub-circuit 1017 (i.e., the fixed end of the first switching module 1018 is connected to the 1 selection end), and the output voltage of the latch and voltage-dropping circuit 1016 is used as the output voltage of the first voltage output sub-circuit 1023 (i.e., the first voltage range (0V-3V)); when the third switch 1014 is turned on for a second time period (i.e., when the control input SS is at a second level), the first latch circuit 1015 is configured to control the first switching module 1018 to operate to connect the VB1 terminal to the first output sub-circuit 1017 (i.e., the first switching module 1018 is in a closed state, and the fixed terminal thereof is connected to the movable terminal), and the voltage at the VB1 terminal is used as the output voltage of the first voltage output sub-circuit 1023 (i.e., the second voltage range (0V-15V)).

With continued reference to fig. 12, in some embodiments, the second voltage output sub-circuit 1024 includes a boost module 1022, a second switching module 1019, and a second latch circuit 1020 connected to the fourth switching tube 1021. The second switching module 1019 is respectively connected to the first output sub-circuit 1017 and the boost module 1022, the second latch circuit 1020 controls the second switching module 1019, when the fourth switching tube 1021 is not turned on, the second switching module 1019 is in an open state, so that the first output sub-circuit 1017 is disconnected from the second voltage output sub-circuit 1024, when the fourth switching tube 1021 is turned on for a second time period (i.e., when the control input terminal SS is the third level), the second latch circuit 1020 controls the second switching module 1019 to connect the boost module 1022 with the first output sub-circuit 1017 (i.e., the second switching module 1019 is in a closed state, and the fixed terminal is connected with the active terminal), and the output voltage of the boost module 1022 is used as the output voltage of the second voltage output sub-circuit 1024 (i.e., the third voltage range (0V to 20V)).

Referring to fig. 1 and 12, in the UH driver circuit 101, the VCC terminal is connected to the positive terminal of the power supply of the first input sub-circuit 1011, the HIN1 is connected to the input terminal of the first input sub-circuit 1011, and the control input terminal SS is connected to the control terminal of the first input sub-circuit 1011. The first output terminal of the first input sub-circuit 1011 is connected to the gate of the first switch tube 1012, the second output terminal of the first input sub-circuit 1011 is connected to the gate of the second switch tube 1013, the third output terminal of the first input sub-circuit 1011 is connected to the gate of the third switch tube 1014, and the fourth output terminal of the first input sub-circuit 1011 is connected to the gate of the fourth switch tube 1021. The GND terminal is connected to the negative terminal of the power supply of the first input sub-circuit 1011, the substrate and source of the first switching tube 1012, the substrate and source of the second switching tube 1013, the substrate and source of the third switching tube 1014, and the substrate and source of the fourth switching tube 1021.

The drain of the first switch tube 1012 enters the high voltage region and is connected to the first input of the latch and buck circuit 1016; the drain of the second switch tube 1013 enters the high voltage region and is connected to the second input of the latch and buck circuit 1016; the drain of the third switch transistor 1014 enters a high voltage region and is connected with the enable terminal of the first latch circuit 1015; the drain of the fourth switch tube 1021 enters the high voltage region and is connected to the enable terminal of the second latch circuit 1020. A first output terminal of the latch and buck circuit 1016 is connected to a 1 select terminal of a first switching module 1018 (analog switch in fig. 12); a second output terminal of the latch and buck circuit 1016 is connected to an input terminal of the first output sub-circuit 1017; an output terminal of the first latch circuit 1015 is connected to a control terminal of the first switching module 1018; the fixed end of the first switching module 1018 is connected with the positive end of the power supply of the first output sub-circuit 1017; the output end of the boost module 1022 is connected to the active end of the second switching module 1019; an output terminal of the second latch circuit 1020 is connected to a control terminal of the second switching module 1019. VB1 is connected to the positive terminal of the power supply for the first latch circuit 1015, the positive terminal of the power supply for the second latch circuit 1020, the positive terminal of the power supply for the latch and buck circuit 1016, the positive terminal of the power supply for the boost module 1022, and the 0 select terminal of the first switching module 1018. The VS1 is connected to the power supply negative terminal of the first latch circuit 1015, the power supply negative terminal of the second latch circuit 1020, the power supply negative terminal of the latch and buck circuit 1016, the power supply negative terminal of the boost module 1022, and the power supply negative terminal of the first output sub-circuit 1017. After the capacitor 131 is charged at the terminal VB1 at the VCC terminal to obtain sufficient electric power, the terminal VB1 can obtain an output voltage 15V with respect to the terminal VS 1.

The first input sub-circuit 1011 functions to: on the rising edge of the signal at the input terminal of the first input sub-circuit 1011, the first output terminal of the first input sub-circuit 1011 outputs a pulse signal with a pulse width of about 300 ns; at the falling edge of the signal at the input end of the first input sub-circuit 1011, the second output end of the first input sub-circuit 1011 outputs a pulse signal with a pulse width of about 300 ns; when the control input terminal of the first input sub-circuit 1011 is at VCC level, a pulse signal with a pulse width of about 600ns (i.e., a first time length) is output at the third output terminal of the first input sub-circuit 1011; when the control input terminal of the first input sub-circuit 1011 is at 0 level, a pulse signal with a pulse width of about 300ns (i.e., a second time length) is output at the third output terminal of the first input sub-circuit 1011; when the control input terminal of the first input sub-circuit 1011 is at VCC/2 level, a pulse signal having a pulse width of about 300ns (i.e., a second time duration) is output at the fourth output terminal of the first input sub-circuit 1011.

The first latch circuit 1015 functions to: when the signal at the input end of the first latch circuit 1015 appears at a low level of 600ns, the output end of the first latch circuit 1015 outputs a high level, when the signal at the input end of the first latch circuit 1015 appears at a low level of 300ns, the output end of the first latch circuit 1015 outputs a low level, and when the signal at the input end of the first latch circuit 1015 never appears at a low level, the output end of the first latch circuit 1015 outputs a VCC/2 voltage.

The latch and buck circuit 1016 functions to: when the first input end of the latch and voltage-reducing circuit 1016 has low level of 300ns, the second output end of the latch and voltage-reducing circuit 1016 outputs continuous high level; when the low level of 300ns appears at the second input terminal of the latch and voltage-reducing circuit 1016, a low level is continuously outputted at the second output terminal of the latch and voltage-reducing circuit 1016, that is, the two pulse signals split from the signal of HIN1 at the two output terminals of the first input sub-circuit 1011 are recombined into a complete signal. The latch and voltage-reducing circuit 1016 includes a voltage-reducing circuit therein, and a voltage of 3V with respect to VS1 is output from a second output terminal of the latch and voltage-reducing circuit 1016.

The second latch circuit 1020 functions to: when a low level of 300ns appears at the first input of the latch and buck circuit 1016, a sustained high level is output at the second output of the latch and buck circuit 1016, otherwise a low level is output.

The first output sub-circuit 1017 functions to: and outputting a signal with the voltage value at the high level consistent with the positive end of the power supply, the voltage value at the low level consistent with the negative end of the power supply and the phase consistent with the HIN 1. Here, the narrow pulse signal of 300ns (i.e., the first time length) or 600ns (i.e., the second time length) is used to control the first switch tube 1012, the second switch tube 1013, the third switch tube 1014 and the fourth switch tube 1021, so as to reduce the power consumption by shortening the on-time of the first switch tube 1012, the second switch tube 1013, the third switch tube 1014 and the fourth switch tube 1021.

The UH driving circuit 101 can output high and low level signals in the first voltage range, the second voltage range and the third voltage range according to the following operation principle:

after the signal of HIN1 passes through the first input sub-circuit 1011, a narrow pulse of 300ns is output at the first output end and the second output end of the first input sub-circuit 1011 at the rising edge and the falling edge of the signal respectively, the narrow pulse controls the first switch tube 1012 and the second switch tube 1013 to be conducted for 300ns respectively, so that the first input end and the second input end of the latch and voltage-reducing circuit 1016 generate low level of 300ns respectively, and the latch and voltage-reducing circuit 1016 is internally provided with devices such as an RS flip-flop, so that the two low level signals are recombined into a complete signal which is in phase with HIN 1.

1. When the upper arm switch tube 127 and the lower arm switch tube 128 both include GaN MOS tubes, the control input terminal SS is connected to a VCC level (first level), a high level does not occur at the fourth output terminal of the first input sub-circuit 1011, the fourth switch tube 1021 cannot be turned on, a low level does not occur at the input terminal of the second latch circuit 1020, the output terminal of the second latch circuit 1020 maintains the low level, and thus the second switching module 1019 is in a disconnected state. And 600ns (i.e. a first time length) high level pulse appears at the third output end of the first input sub-circuit 1011, 600ns conduction appears at the third switch tube 1014, 600ns low level appears at the input end of the first latch circuit 1015, the output end of the first latch circuit 1015 outputs from low to high level, so that the 1 selection end of the first switching module 1018 is connected with the fixed end, the positive end of the power supply of the first output sub-circuit 1017 is connected with the first output end of the latch and voltage-reducing circuit 1016, and the high level output end (i.e. the P-HO1 end) and the low level output end (i.e. the N-HO1 end) of the first output sub-circuit 1017 output 3V and 0V voltages respectively.

2. When the upper arm switching tube 127 and the lower arm switching tube 128 both include Si IGBT tubes, the input terminal SS is controlled to be connected to a 0 level (second level), so that a high level does not appear at the fourth output terminal of the first input sub-circuit 1011, the fourth switching tube 1021 cannot be turned on, a low level does not appear at the input terminal of the second latch circuit 1020, the output terminal of the second latch circuit 1020 maintains the low level, and the second switching module 1019 is in a disconnected state. And a high level pulse of 300ns (i.e. a second time length) appears at the third output terminal of the first input sub-circuit 1011, a conduction of 300ns appears at the third switching tube 1014, a low level of 300ns appears at the input terminal of the first latch circuit 1015, the output terminal of the first latch circuit 1015 goes from high to low level, so that the 0 selection terminal of the first switching module 1018 is connected with the fixed terminal, the positive supply power terminal of the first output sub-circuit 1017 is connected with VB1, and the high level output terminal (i.e. the P-HO1 terminal) and the low level output terminal (i.e. the N-HO1 terminal) of the first output sub-circuit 1017 output voltages of 15V and 0V, respectively.

3. When the upper arm switching tube 127 and the lower arm switching tube 128 both include SiC MOS tubes, the control input terminal SS is connected to VCC/2 level (third level), so that the third output terminal of the first input sub-circuit 1011 does not have a high level, the third switching tube 1014 is not turned on, the input terminal of the first latch circuit 1015 does not have a low level, the output terminal of the first latch circuit 1015 always outputs a low level, and the first switching module 1018 is in a suspended state. And a high level pulse of 300ns (i.e. a second time length) appears at the fourth output terminal of the first input sub-circuit 1011, a conduction of 300ns appears at the fourth switch tube 1021, a low level of 300ns appears at the input terminal of the second latch circuit 1020, the output terminal of the second latch circuit 1020 outputs a high level, the active terminal and the fixed terminal of the second switch module 1019 are connected, the second switch module 1019 is in a closed state, the positive terminal of the power supply of the first output sub-circuit 1017 is connected with the output terminal of the second boost module 1022, and the high level output terminal (i.e. the P-HO1 terminal) and the low level output terminal (i.e. the N-HO1 terminal) of the first output sub-circuit 1017 output voltages of 20V and 0V, respectively.

Referring to fig. 15, the UL/VL/WL driver circuit 104 includes a second input sub-circuit 1041, a buck sub-circuit 1048, a boost sub-circuit 1050, a switch module 1049, and a third voltage output sub-circuit 1051 connected to the second input sub-circuit 1041, the switch module 1049, the buck sub-circuit 1048, and the boost sub-circuit 1050. The second input sub-circuit 1041 includes a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, and a fifth output terminal, wherein when the control input terminal SS inputs the first level, the fourth output terminal outputs the first trigger pulse; when the control input end SS inputs a second level, the fourth output end outputs a second trigger pulse, and the first trigger pulse and the second trigger pulse are opposite; when the control input end SS outputs a third level, the fifth output end outputs a trigger pulse; the voltage-reducing sub-circuit 1048 reduces the power supply voltage to a first voltage range; the boost sub-circuit 1050 boosts the power supply voltage to a third voltage range; the switch module 1049 is connected to the step-down sub-circuit 1048, and the switch module 1049 is controlled by a fifth output end; when the fourth output end outputs the first trigger pulse, the third voltage output sub-circuit 1051 outputs a high-low level signal in the first voltage range; when the fourth output terminal outputs the second trigger pulse, the third voltage output sub-circuit 1051 outputs a high-low level signal in the second voltage range; when the fifth output terminal outputs the trigger pulse, the third voltage output sub-circuit 1051 outputs a high-low level signal of the third voltage range.

Referring to fig. 15, in some embodiments, the third voltage output sub-circuit 1051 includes a second output sub-circuit 1042, a third output sub-circuit 1043, a fourth output sub-circuit 1044, a third switching module 1045, a fourth switching module 1046, and a fifth switching module 1047, respectively. The first output terminal, the second output terminal, and the third output terminal of the second input sub-circuit 1041 are respectively connected to the second output sub-circuit 1042, the third output sub-circuit 1043, and the fourth output sub-circuit 1044, and the third switching module 1045, the fourth switching module 1046, and the fifth switching module 1047 are respectively connected to the second output sub-circuit 1042, the third output sub-circuit 1043, and the fourth output sub-circuit 1044. The third switching module 1045, the fourth switching module 1046, and the fifth switching module 1047 select the power voltage or the output voltage of the step-down sub-circuit 1048 as the output voltage of the third voltage output sub-circuit 1051 according to the output of the fourth output terminal of the second input sub-circuit 1041.

As shown in fig. 15, in the UL/VL/WL driver circuit 104, the VCC terminal is connected to the positive terminal of the power supply of the second input sub-circuit 1041, the positive terminal of the power supply of the boost sub-circuit 1050, the positive terminal of the power supply of the buck sub-circuit 1048, the 0 selection terminal of the third switching module 1045, the 0 selection terminal of the fourth switching module 1046, and the 0 selection terminal of the fifth switching module 1047. LIN1 is connected to a first input of second input sub-circuit 1041. LIN2 is connected to a second input of second input sub-circuit 1041. LIN3 is connected to a third input of second input sub-circuit 1041.

The control input terminal SS is connected to the control terminal of the second input sub-circuit 1041, and the first output terminal of the second input sub-circuit 1041 is connected to the input terminal of the second output sub-circuit 1042; a second output terminal of the second input sub-circuit 1041 is connected to an input terminal of the third output sub-circuit 1043; a third output terminal of the second input sub-circuit 1041 is connected to an input terminal of a fourth output sub-circuit 1044; a fourth output end of the second input sub-circuit 1011 is connected to a control end of the third switching module 1045, a control end of the fourth switching module 1046, and a control end of the fifth switching module 1047, respectively.

The GND terminal is connected to the negative terminal of the power supply of the second input sub-circuit 1041, the negative terminal of the power supply of the second step-down sub-circuit 1048, the negative terminal of the power supply of the second output sub-circuit 1042, the negative terminal of the power supply of the third output sub-circuit 1043, and the negative terminal of the power supply of the fourth output sub-circuit 1044; an output end of the voltage-reducing sub-circuit 1048 is connected to a 1 selection end of the third switching module 1045, a 1 selection end of the fourth switching module 1046, and a 1 selection end of the fifth switching module 1047, respectively.

The second input sub-circuit 1041 functions as: outputting a signal at a first output terminal of the second input sub-circuit 1041, which is in phase with the first input terminal of the second input sub-circuit 1041; a signal in phase with the second input terminal of the second input sub-circuit 1041 is output at the second output terminal of the second input sub-circuit 1041; a signal in phase with the third input terminal of the second input sub-circuit 1041 is output at the third output terminal of the second input sub-circuit 1041.

When the control input terminal SS of the second input sub-circuit 1041 is at VCC level, a high level is output at the fourth output terminal of the second input sub-circuit 1041; when the control input terminal SS of the second input sub-circuit 1041 is at 0 level, a low level is output at the fourth output terminal of the second input sub-circuit 1041; when the control input terminal SS of the second input sub-circuit 1041 is at VCC/2 level, a high level is output at the fifth output terminal of the second input sub-circuit 1041.

The buck subcircuit 1048 functions as: the output terminal of the step-down sub-circuit 1048 outputs a voltage of 3V to the GND terminal. The function of the boost sub-circuit 1050 is: the output terminal of the booster sub-circuit 1050 outputs a voltage of 15V to the GND terminal.

The second output sub-circuit 1042 is used for outputting a signal whose voltage value at high level is consistent with the positive terminal of the power supply, and whose voltage value at low level is consistent with the negative terminal of the power supply, and whose phase is consistent with LIN 1; the third output sub-circuit 1043 functions to output a signal whose voltage value at high level is identical to the positive terminal of the power supply, whose voltage value at low level is identical to the negative terminal of the power supply, and whose phase is identical to LIN 2; the fourth output sub-circuit 1044 is configured to output a signal having a voltage value at a high level corresponding to the positive terminal of its power supply, a voltage value at a low level corresponding to the negative terminal of its power supply, and a phase corresponding to LIN 3.

The operation principle that UL/VL/WL driver circuit 104 can output high and low levels of the first voltage range, the second voltage range, and the third voltage range is as follows:

1. when the upper arm switch tube 127 and the lower arm switch tube 128 both comprise GaN MOS tubes, the control input terminal SS is VCC level, so that the fourth output terminal of the UL/VL/WL driver circuit 104 outputs a low-to-high level (first trigger pulse), the fixed terminal of the third switching module 1045 is connected to the 1 selection terminal of the third switching module 1045, the fixed terminal of the fourth switching module 1046 is connected to the 1 selection terminal of the fourth switching module 1046, the fixed terminal of the fifth switching module 1047 is connected to the 1 selection terminal of the fifth switching module 1047, the fifth output terminal outputs a low level, the switching module 1049 is in an off state, so that the high level output terminal (i.e., the P-LO1 terminal) and the low level output terminal (i.e., the N-LO1 terminal) of the second output sub-circuit 1042, the high level output terminal (i.e., the P-LO2 terminal) and the low level output terminal (i.e., terminal N-LO2), and the high (i.e., terminal P-LO3) and low (i.e., terminal N-LO3) outputs 3V and 0V, respectively, of the fourth output sub-circuit 1044.

2. When the upper arm switching tube 127 and the lower arm switching tube 128 both include Si IGBT tubes, the control input terminal SS is at 0 level, so that the fourth output terminal of the UL/VL/WL driver 104 outputs a high-to-low level (second trigger pulse), the fixed terminal of the third switching module 1045 is connected to the 0 selection terminal of the third switching module 1045, the fixed terminal of the fourth switching module 1046 is connected to the 0 selection terminal of the fourth switching module 1046, the fixed terminal of the fifth switching module 1047 is connected to the 0 selection terminal of the fifth switching module 1047, the fifth output terminal outputs a low level, the switching module 1049 is in an off state, so that the high level output terminal (i.e., the P-LO1 terminal) and the low level output terminal (i.e., the N-LO1 terminal) of the second output sub-circuit 1042, the high level output terminal (i.e., the P-LO2 terminal) and the low level output terminal (i.e., terminal N-LO2), and the high (i.e., terminal P-LO3) and low (i.e., terminal N-LO3) outputs 15V and 0V, respectively, of the fourth output sub-circuit 1044.

3. When the upper arm switching tube 127 and the lower arm switching tube 128 both include SiC MOS tubes, the control input terminal SS is VCC/2 level, so that the fifth output terminal of the UL/VL/WL driver 104 outputs high level, and the switch module 1049 is in a closed state, the fixed terminal of the switch module 1049 is connected to the output terminal of the first buck sub-circuit 1050, the fourth output terminal outputs low level, the third switch module 1045 is in a suspended state, the fourth switch module 1046 is in a suspended state, and the fifth switch module 1047 is in a suspended state, so that the high level output terminal (i.e., the P-LO1 terminal) and the low level output terminal (i.e., the N-LO1 terminal) of the second output sub-circuit 1042, the high level output terminal (i.e., the P-LO2 terminal) and the low level output terminal (i.e., the N-LO2 terminal) of the third output sub-circuit 1043, and the high level output terminal (i.e., P-LO3 terminal) and a low-level output terminal (i.e., N-LO3 terminal) output voltages of 20V and 0V, respectively.

Referring to fig. 16, an electrical apparatus 1000 according to an embodiment of the present application includes the power device 100 according to any one of the above embodiments and a processor 200, and the processor 200 is connected to the power device 100.

In the electric appliance 1000 and the power device 100 according to the embodiment of the present invention, the power device 100 described above can improve the suitability of the Si IGBT tube, the GaN MOS tube, and the SiC MOS tube, and can exert the technical advantages of the Si IGBT tube, the GaN MOS tube, and the SiC MOS tube. The processor 200 is connected to the controller 10 of the power device 100, and when the user operates the electrical appliance 1000, the processor 200 sends a signal to the controller 130 of the power device 100, and the controller 130 controls the control input terminal SS to access the first level, the second level or the third level, so that the electrical appliance 1000 switches the desired function.

The electric appliance 1000 may be an air conditioner, a washing machine, a refrigerator, an induction cooker, or the like, and the power device 100 therein may implement the functions of the power device 100 described in the foregoing section.

Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations of the above embodiments may be made by those of ordinary skill in the art within the scope of the present application, which is defined by the claims and their equivalents.

Claims

1. A power device, comprising:

a control input;

an upper bridge arm switching tube and a lower bridge arm switching tube;

an upper resistor group and a lower resistor group;

the first driving circuit is connected with the control input end and is connected with the upper bridge arm switching tube through the upper resistor group;

the second driving circuit is connected with the control input end and is connected with the lower bridge arm switching tube through the lower resistor group;

the control input end can be connected with a first level, a second level or a third level, when the control input end is connected with the first level, the first driving circuit and the second driving circuit output high and low levels of a first voltage range, when the control input end is connected with the second level, the first driving circuit and the second driving circuit output high and low levels of a second voltage range, when the control input end is connected with the third level, the first driving circuit and the second driving circuit output high and low levels of a third voltage range, and the first voltage range, the second voltage range and the third voltage range are different;

the first drive circuit comprises a UH drive circuit, a VH drive circuit and a WH drive circuit; the UH driver circuit, the VH driver circuit, or the WH driver circuit includes:

a first input sub-circuit connected to the control input, the first input sub-circuit having a first output, a second output, a third output, and a fourth output, wherein, when the control input terminal is at a first level, the first output terminal and the second output terminal output trigger pulses, the third output terminal outputs trigger pulses of a first time length, when the control input end is at the second level, the first output end and the second output end output trigger pulses, the third output end outputs a trigger pulse with a second time length, the first time length is larger than the second time length, when the control input end is at the third level, the first output end and the second output end output trigger pulses, and the fourth output end outputs the trigger pulses of the second time length;

the first switch tube is connected with the first output end, the second switch tube is connected with the second output end, the third switch tube is connected with the third output end, and the fourth switch tube is connected with the fourth output end;

the first voltage output sub-circuit is respectively connected with the first switching tube, the second switching tube and the third switching tube;

the second voltage output sub-circuit is connected with the fourth switching tube;

and the first output sub-circuit comprises a high-level output end and a low-level output end, and is respectively connected with the first voltage output sub-circuit and the second voltage output sub-circuit.

2. The power device of claim 1, further comprising a VCC terminal, a GND terminal, and a reference power terminal, wherein when the control input terminal is connected to the VCC terminal through a bonding line, the control input terminal is switched in the first level; when the control input end is connected with the GND end through a bonding line, the control input end is connected to the second level; and when the control input end is connected with the reference power end through a bonding line, the control input end is connected to the third level.

3. The power device of claim 1, comprising a controller, wherein the control input is coupled to the controller, and wherein the controller is configured to output the first level, the second level, or the third level.

4. The power device of claim 1, wherein the first voltage range is 0V to 3V, the second voltage range is 0V to 15V, and the third voltage range is 0V to 20V.

5. The power device of any of claims 1-4, wherein the second drive circuit comprises a UL/VL/WL drive circuit; the upper bridge arm switching tubes comprise a first upper bridge arm switching tube, a second upper bridge arm switching tube and a third upper bridge arm switching tube; the lower bridge arm switching tubes comprise a first lower bridge arm switching tube, a second lower bridge arm switching tube and a third lower bridge arm switching tube; wherein the content of the first and second substances,

the control input end is connected with the UH drive circuit, the VH drive circuit and the WH drive circuit, and the UH drive circuit, the VH drive circuit and the WH drive circuit respectively drive the first upper bridge arm switching tube, the second upper bridge arm switching tube and the third upper bridge arm switching tube; the UH drive circuit is connected with the first upper bridge arm switching tube, the VH drive circuit is connected with the second upper bridge arm switching tube, and the WH drive circuit is connected with the third upper bridge arm switching tube;

the control input end is connected with the UL/VL/WL driving circuit, the UL/VL/WL driving circuit drives the first lower bridge arm switching tube, the second lower bridge arm switching tube and the third lower bridge arm switching tube, and the UL/VL/WL driving circuit is respectively connected with the first lower bridge arm switching tube, the second lower bridge arm switching tube and the third lower bridge arm switching tube.

6. The power device according to claim 5, wherein when the first upper bridge arm switching tube, the second upper bridge arm switching tube, the third upper bridge arm switching tube, the first lower bridge arm switching tube, the second lower bridge arm switching tube, and the third lower bridge arm switching tube all include GaN devices, a level of a signal input to the control input terminal is the first level; when the first upper bridge arm switching tube, the second upper bridge arm switching tube, the third upper bridge arm switching tube, the first lower bridge arm switching tube, the second lower bridge arm switching tube, and the third lower bridge arm switching tube all include Si devices, the level of the signal input to the control input terminal is the second level, and when the first upper bridge arm switching tube, the second upper bridge arm switching tube, the third upper bridge arm switching tube, the first lower bridge arm switching tube, the second lower bridge arm switching tube, and the third lower bridge arm switching tube all include SiC devices, the level of the signal input to the control input terminal is the third level.

7. The power device of claim 1, wherein the first voltage output sub-circuit comprises:

the latch and voltage reduction module is connected with the first switch tube and the second switch tube;

the first switching module is respectively connected with the latching and voltage-reducing module, the power supply and the first output sub-circuit;

the first switching module is used for connecting the latching and voltage-reducing module with the first output sub-circuit so that the output voltage of the latching and voltage-reducing module is used as the output voltage of the high-level output end, and the output voltage of the negative end of the power supply is used as the output voltage of the low-level output end; when the third switch tube is turned on for the second time length, the first switching module connects the positive power supply terminal and the first output sub-circuit so that the output voltage of the positive power supply terminal is used as the output voltage of the high-level output terminal, and the output voltage of the negative power supply terminal is used as the output voltage of the low-level output terminal.

8. The power device of claim 7, wherein the second voltage output sub-circuit comprises:

a boost module;

the second switching module is respectively connected with the boosting module and the first output sub-circuit;

and the second latch module is used for controlling the second switching module, when the fourth switching tube is conducted for the second time length, the first switching module is used for connecting the boost module and the first output sub-circuit so that the output voltage of the boost module is used as the output voltage of the high-level output end, and the output voltage of the negative end of the power supply is used as the output voltage of the low-level output end.

9. The power device of claim 5, wherein the upper resistor group comprises a first gate-on resistor, a second gate-on resistor, a third gate-on resistor, a first gate-off resistor, a second gate-off resistor, and a third gate-off resistor, wherein one end of the first gate-on resistor, the second gate-on resistor, and the third gate-on resistor are respectively connected to the high-level output terminal of the UH driving circuit, the high-level output terminal of the VH driving circuit, and the high-level output terminal of the WH driving circuit, and the other end of the first gate-on resistor, the second gate-on resistor, and the third gate-on resistor are respectively connected to the first lower leg switching tube, the second lower leg switching tube, and the third lower leg switching tube; one end of each of the first gate turn-off resistor, the second gate turn-off resistor and the third gate turn-off resistor is connected to the low level output terminal of the UH driving circuit, the low level output terminal of the VH driving circuit and the low level output terminal of the WH driving circuit, and the other end of each of the first gate turn-off resistor, the second gate turn-off resistor and the third gate turn-off resistor is connected to the first lower arm switching tube, the second lower arm switching tube and the third lower arm switching tube.

10. The power device of claim 5, wherein the UL/VL/WL driver circuit comprises:

a second input sub-module, including a first output terminal, a second output terminal, a third output terminal, a fourth output terminal and a fifth output terminal, wherein when the control input terminal is at the first level, the fourth output terminal outputs a first trigger pulse, when the control input terminal is at the second level, the fourth output terminal outputs a second trigger pulse, the second trigger pulse is opposite to the first trigger pulse, and when the control input terminal is at the third level, the fifth output terminal outputs a trigger pulse;

a boost sub-circuit that boosts a power supply voltage to the third voltage range;

a buck sub-circuit that steps down the supply voltage to a first voltage range;

the switch module is connected with the boosting sub-circuit and is controlled by the fifth output end;

and a third voltage output sub-circuit connected to the second input sub-circuit, the switch module, the buck sub-circuit, and the boost sub-circuit, wherein when the fourth output terminal outputs the first trigger pulse, the third output sub-circuit outputs a high-low level signal in the first voltage range, when the fourth output terminal outputs the second trigger pulse, the third output sub-circuit outputs a high-low level signal in the second voltage range, and when the fifth output terminal outputs the trigger pulse, the third output sub-circuit outputs a high-low level signal in the third voltage range.

11. The power device of claim 10, wherein the third voltage output sub-circuit comprises:

a second output sub-circuit, a third output sub-circuit and a fourth output sub-circuit respectively connected to the first output terminal, the second output terminal and the third output terminal of the second input sub-circuit;

a third switching module, a fourth switching module, and a fifth switching module respectively connected to the second output sub-circuit, the third output sub-circuit, and the fourth output sub-circuit, wherein the second output sub-circuit, the third output sub-circuit, and the fourth output sub-circuit each include a high level output terminal and a low level output terminal, and when the fourth output terminal outputs the first trigger pulse, the third switching module, the fourth switching module, and the fifth switching module respectively connect the buck sub-circuit with the second output sub-circuit, the third output sub-circuit, and the fourth output sub-circuit so that the output voltage of the buck sub-circuit is used as the output voltage of the high level output terminal of the second output sub-circuit, the third output sub-circuit, and the fourth output sub-circuit, and the output voltage of the power supply negative terminal is used as the output voltage of the second output sub-circuit, the third output sub-circuit, and the fourth output sub-circuit, The output voltages of the low-level output ends of the third output sub-circuit and the fourth output sub-circuit are respectively controlled by the control circuit; when the fourth output end outputs the second trigger pulse, the third switching module, the fourth switching module, and the fifth switching module connect the positive power supply end with the second output sub-circuit, the third output sub-circuit, and the fourth output sub-circuit, respectively, so that the output voltage of the positive power supply end is used as the output voltage of the high level output end of the second output sub-circuit, the third output sub-circuit, and the fourth output sub-circuit, and the output voltage of the negative power supply end is used as the output voltage of the low level output end of the second output sub-circuit, the third output sub-circuit, and the fourth output sub-circuit; when the fifth output end outputs the trigger pulse, the third switching module, the fourth switching module, and the fifth switching module connect the boost sub-circuit with the second output sub-circuit, the third output sub-circuit, and the fourth output sub-circuit, respectively, so that the output voltage of the boost sub-circuit is used as the output voltage of the high level output end of the second output sub-circuit, the third output sub-circuit, and the fourth output sub-circuit, and the output voltage of the power supply negative terminal is used as the output voltage of the low level output end of the second output sub-circuit, the third output sub-circuit, and the fourth output sub-circuit.

12. The power device according to claim 11, wherein the lower resistor group includes a fourth gate-on resistor, a fifth gate-on resistor, a sixth gate-on resistor, a fourth gate-off resistor, a fifth gate-off resistor, and a sixth gate-off resistor, one end of the fourth gate-on resistor, the fifth gate-on resistor, and the sixth gate-on resistor are respectively connected to the high-level output terminal of the second output sub-circuit, the high-level output terminal of the third output sub-circuit, and the high-level output terminal of the fourth output sub-circuit, and the other end of the fourth gate-on resistor, the fifth gate-on resistor, and the sixth gate-on resistor are respectively connected to the first lower arm switching tube, the second lower arm switching tube, and the third lower arm switching tube; one end of the fourth gate turn-off resistor, one end of the fifth gate turn-off resistor and one end of the sixth gate turn-off resistor are respectively connected with the low level output end of the second output sub-circuit, the low level output end of the third output sub-circuit and the low level output end of the fourth output sub-circuit, and the other end of the fourth gate turn-off resistor, the other end of the fifth gate turn-off resistor and the other end of the sixth gate turn-off resistor are respectively connected with the first lower bridge arm switching tube, the second lower bridge arm switching tube and the third lower bridge arm switching tube.

13. An electrical appliance, characterized in that it comprises a power device according to any one of claims 1-12.

14. The appliance according to claim 13, characterized in that the appliance is an air conditioner.