CN109525127B

CN109525127B - Power device and electric appliance

Info

Publication number: CN109525127B
Application number: CN201811645565.XA
Authority: CN
Inventors: 冯宇翔
Original assignee: Midea Group Co Ltd; GD Midea Air Conditioning Equipment Co Ltd
Current assignee: Midea Group Co Ltd; GD Midea Air Conditioning Equipment Co Ltd
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2020-05-05
Anticipated expiration: 2038-12-29
Also published as: CN109525127A

Abstract

The application discloses power device and electrical apparatus, power device includes: an SS input end; the first to third upper bridge arm switching tubes and the lower bridge arm switching tube; the UH drive circuit, the VH drive circuit, the WH drive circuit and the UL/VL/WL drive circuit are connected with the SS input end and respectively drive the first to third upper bridge arm switch tubes, when the SS input end is at a first level, the UH drive circuit, the VH drive circuit, the WH drive circuit and the UL/VL/WL drive circuit output high-low level signals in a first voltage range, when the SS input end is at a second level, the UH drive circuit, the VH drive circuit, the WH drive circuit and the UL/VL/WL drive circuit output high-low level signals in a second voltage range, when the SS input end is at a third level, the UH drive circuit, the VH drive circuit, the WH drive circuit and the UL/VL/WL drive circuit output high-low level signals in a third voltage range, and therefore silicon, voltage and power consumption can be improved, Suitability for gallium nitride and silicon carbide smart power modules.

Description

Power device and electric appliance

Technical Field

The application relates to the technical field of electric appliances, in particular to a power device and an electric appliance with the same.

Background

An intelligent Power module, i.e., ipm (intelligent Power module), is a Power driving product (Power device) combining Power electronics and integrated circuit technology. The intelligent power module integrates a power switch device (such as a GaN (gallium nitride) device, a Si (silicon) device or a SiC (silicon carbide) device) with a high-voltage integrated circuit, and incorporates a fault detection circuit for overvoltage, overcurrent, overheat, and the like. The intelligent power module receives a control signal of an MCU (Micro Controller Unit) to drive a subsequent circuit to operate, and sends a state detection signal of the system back to the MCU. Compared with the traditional discrete scheme, the intelligent power module wins a bigger and bigger market with the advantages of high integration degree, high reliability and the like, is particularly suitable for a frequency converter of a driving motor and various inverter power supplies, and is an ideal power electronic device for variable-frequency speed regulation, metallurgical machinery, electric traction, servo drive and variable-frequency household appliances.

In practical application, with the continuous improvement of the requirement on the energy consumption of the system, especially in the air conditioner industry, the power consumption of the intelligent power module becomes a main source of the variable frequency electric control power consumption of the variable frequency air conditioner, and how to reduce the power consumption of the intelligent power module becomes an important subject influencing the further popularization and application of the intelligent power module and even the variable frequency air conditioner. The replacement of a Si device by a GaN device or a SiC device is an effective way to reduce the power consumption of an intelligent power module, but brings a new problem, because the GaN device or the SiC device and the Si device have different threshold voltages, generally speaking, the GaN device has a lower threshold voltage than the Si device, if the same type of high-voltage integrated circuit is used for driving, the gate of the GaN device is likely to be broken down, the SiC device has a higher threshold voltage than the Si device, if the same type of high-voltage integrated circuit is used for driving, the conduction process of the SiC device is likely to be incomplete, the advantage of low power consumption of SiC is not achieved, even the opposite effect is achieved, but if different types of high-voltage integrated circuits are used for driving, the difficulty of material organization in the production process is caused, the risk of material mixing is caused, the cost of the intelligent power module is correspondingly increased, and if the GaN device is not broken down, the high-voltage integrated circuit for driving the Si device needs to be powered by lower voltage, which inevitably causes the power consumption of the whole Si intelligent power module to be increased, even the Si device can not work, and the voltage is low enough to cause the high-voltage integrated circuit for driving the GaN device to work normally and has no universality if the peripheral circuit is modified and lower voltage is used for supplying power to the high-voltage integrated circuit for driving the GaN device, and the power consumption of the whole intelligent power module is inevitably increased and is offset with the power reduction of the SiC device if the high-voltage integrated circuit for driving the SiC device is powered by higher voltage, thereby reducing the effect of reducing the power consumption of the intelligent power module using the SiC device, and the peripheral electric control scheme is required to be modified if higher voltage is used for supplying power to the high-voltage integrated circuit for driving the SiC device, the conflict of the intelligent power module with the SiC device is undoubtedly increased, and the high voltage exceeds the withstand voltage of the GaN device, so that the high voltage cannot be generally used for the GaN device.

Disclosure of Invention

The application can improve the adaptability of the silicon intelligent power module, the gallium nitride intelligent power module and the silicon carbide intelligent power module by providing a solution of the power device with high adaptability, so that the technical advantages of the silicon intelligent power module, the gallium nitride intelligent power module and the silicon carbide intelligent power module can be brought into play.

The application provides a power device, including: an SS input end; the first upper bridge arm switching tube to the third upper bridge arm switching tube and the first lower bridge arm switching tube to the third lower bridge arm switching tube; a UH drive circuit, a VH drive circuit and a WH drive circuit which are all connected with the SS input end and respectively drive the first upper bridge arm switching tube to the third upper bridge arm switching tube, wherein the UH drive circuit is connected with a first upper bridge arm switch tube, the VH drive circuit is connected with a second upper bridge arm switch tube, the WH drive circuit is connected with a third upper bridge arm switch tube, wherein, when the SS input terminal is at a first level, the UH drive circuit, the VH drive circuit and the WH drive circuit output high-low level signals in a first voltage range, when the SS input end is at a second level, the UH drive circuit, the VH drive circuit and the WH drive circuit output high-low level signals in a second voltage range, when the SS input end is at a third level, the UH drive circuit, the VH drive circuit and the WH drive circuit output high-low level signals in a third voltage range; and the UL/VL/WL driving circuit is connected with the SS input end and drives the first lower bridge arm switching tube to the third lower bridge arm switching tube, and is respectively connected with the first lower bridge arm switching tube to the third lower bridge arm switching tube, wherein when the SS input end is at a first level, the UL/VL/WL driving circuit outputs high-low level signals in a first voltage range, when the SS input end is at a second level, the UL/VL/WL driving circuit outputs high-low level signals in a second voltage range, and when the SS input end is at a third level, the UL/VL/WL driving circuit outputs high-low level signals in a third voltage range.

The first level is a power supply level VCC, the second level is 0, the third level is VCC/2, the first voltage range is 0-3V, the second voltage range is 0-15V, and the third voltage range is 0-20V.

According to an embodiment of the present application, when the first to third upper arm switching tubes and the first to third lower arm switching tubes include Si devices, the SS input terminal is set to a second level, when the first to third upper arm switching tubes and the first to third lower arm switching tubes include SiC devices, the SS input terminal is set to a third level, and when the first to third upper arm switching tubes and the first to third lower arm switching tubes include GaN devices, the SS input terminal is set to a first level.

According to an embodiment of the present application, the UH driver circuit, the VH driver circuit, or the WH driver circuit includes: the first input sub-circuit is connected with an SS input end, the first input sub-circuit is provided with a first output end to a fourth output end, when the SS input end is at a second level, the first output end and the second output end output trigger pulses, the third output end outputs trigger pulses with a first time length, when the SS input end is at a first level, the first output end and the second output end output trigger pulses, the third output end outputs trigger pulses with a second time length, the second time length is larger than the first time length, when the SS input end is at a third level, the first output end and the second output end output trigger pulses, and the fourth output end outputs trigger pulses with a second time length; the first switching tube is connected with the first output end, the second switching tube is connected with the second output end, the third switching tube is connected with the third output end, and the fourth switching tube is connected with the fourth output end; the first voltage output sub-circuit is respectively connected with the first switching tube to the third switching tube; the second voltage output sub-circuit is connected with the fourth switching tube; and the output sub-circuit is respectively connected with the first voltage output sub-circuit and the second voltage output sub-circuit.

According to an embodiment of the present application, the first voltage output sub-circuit includes: the latch and voltage reduction module is connected with the first switch tube and the second switch tube; the first switching module is respectively connected with the latching and voltage reducing module and the power supply; and the first latch module is used for controlling the first switching module, when the third switching tube is conducted for a first time length, the power supply is used as the output voltage of the voltage output sub-circuit, and when the third switching tube is conducted for a second time length, the output voltage of the latch and voltage reduction module is used as the output voltage of the voltage output sub-circuit.

According to an embodiment of the present application, the second voltage output sub-circuit includes: a first boost module; the second switching module is respectively connected with the first voltage output sub-circuit and the first boosting module; and the second latch module is used for controlling the second switching module, when the fourth switching tube is not switched on, the output sub-circuit is connected with the first voltage output sub-circuit, and when the fourth switching tube is switched on for a first time length, the output sub-circuit is connected with the first boosting module.

According to one embodiment of the present application, the UL/VL/WL driver circuit comprises: a second input sub-module, including a first output terminal to a fifth output terminal, wherein when the SS input terminal is at a second level, the fourth output terminal outputs a first trigger pulse, when the SS input terminal is at a first level, the fourth output terminal outputs a second trigger pulse, the first trigger pulse is opposite to the second trigger pulse, and when the SS input terminal is at a third level, the fifth output terminal outputs a trigger pulse; a boost sub-circuit that boosts a power supply voltage to the third voltage range; a buck sub-circuit that steps down the supply voltage to a first voltage range; the switching circuit is connected with the boosting sub-circuit and is controlled by the fifth output end; and the third voltage output sub-circuit is connected with the second input sub-circuit, the switch circuit, the voltage reduction sub-circuit and the voltage boosting sub-circuit, wherein when the fourth output end outputs a first trigger pulse, the second input sub-circuit outputs high and low level signals in a second voltage range, when the fourth output end outputs a second trigger pulse, the second input sub-circuit outputs high and low level signals in a first voltage range, and when the fifth output end outputs a trigger pulse, the second input sub-circuit outputs high and low level signals in a third voltage range.

According to an embodiment of the present application, the third voltage output sub-circuit includes: the UL output module, the VL output module and the WL output module are respectively connected with the first output end to the third output end of the second input sub-circuit; and the third switching module to the fifth switching module are respectively connected with the UL output module, the VL output module and the WL output module, wherein the third switching module to the fifth switching module select a power supply voltage or an output voltage of the voltage reduction sub-circuit as an output voltage of the third voltage output sub-circuit according to a fourth output end of the second input sub-circuit.

One or more technical solutions of the embodiments of the present application have at least the following technical effects or advantages:

the power supply voltage of the power device is 15V, a peripheral circuit does not need to be modified, and the power consumption of the high-voltage integrated circuit is not substantially increased; the driving GaN device, the SiC device and the driving Si device are the same high-voltage integrated circuit, so that no material mixing risk exists in the production process, material organization is facilitated, and material cost is reduced; the GaN device is driven to use 3V voltage, the SiC device is driven to use 20V voltage, and the Si device is driven to use 15V voltage, so that the GaN device, the SiC device and the Si device are in a complete conduction state in the conduction process and cannot be broken down, and the respective performances are exerted.

Drawings

FIG. 1a is a circuit configuration diagram of a related art smart power module;

FIG. 1b is a schematic diagram of a proposed circuit for an intelligent power module in a related art;

fig. 2 is a circuit configuration diagram of a power device according to an embodiment of the present application;

FIGS. 3a to 3h are schematic views of a switching tube according to an embodiment of the present invention;

FIG. 4a is a schematic diagram of a UH driver circuit in accordance with one embodiment of the present application; and

FIG. 4b is a schematic diagram of a UL/VL/WL driver circuit according to an embodiment of the present application.

Detailed Description

Before the embodiments of the present application are described, a related art power device, such as the smart power module 100, is described with reference to fig. 1a and 1 b.

Referring to fig. 1a, a power supply positive terminal VCC of an HVIC (High Voltage Integrated Circuit) tube 111 in the intelligent power module 100 is used as a low Voltage area power supply positive terminal VDD of the intelligent power module 100, and VDD is generally 15V; the HIN1 end of the HVIC tube 111 is used as the U-phase upper bridge arm input end UHIN of the intelligent power module 100 and is connected with the input end of the UH drive circuit 101 in the HVIC tube 111; the HIN2 end of the HVIC tube 111 is used as the V-phase upper bridge arm input end VHIN of the intelligent power module 100 and is connected with the input end of the VH drive circuit 102 inside the HVIC tube 111; the HIN3 end of the HVIC tube 111 serves as the W-phase upper bridge arm input end WHIN of the intelligent power module 100, and is connected with the input end of the WH driving circuit 103 inside the HVIC tube 111; the LIN1 end of the HVIC tube 111 serves as the U-phase lower bridge arm input end ULINs of the intelligent power module 100, and is connected to the input end of the UL driving circuit 104 inside the HVIC tube 111; the LIN2 end of the HVIC tube 111 serves as the V-phase lower bridge arm input end VLIN of the intelligent power module 100, and is connected to the input end of the VL drive circuit 105 inside the HVIC tube 111; the LIN3 end of the HVIC tube 111 serves as the W-phase lower bridge arm input end WLIN of the intelligent power module 100, and is connected to the input end of the WL driver circuit 106 inside the HVIC tube 111; here, six input ends of U, V, W three phases of the intelligent power module 100 all receive input signals of 0V or 5V; the GND terminal of the HVIC tube 111 serves as the low-voltage-area power supply negative terminal COM of the intelligent power module 100, and is connected to the low-voltage-area power supply negative terminals of the UH driver circuit 101, the VH driver circuit 102, the WH driver circuit 103, the UL driver circuit 104, the VL driver circuit 105, and the WL driver circuit 106.

The VB1 end of the HVIC tube 111 is connected with the positive end of the high-voltage area power supply of the UH drive circuit 101 inside the HVIC tube 111, and the outside of the HVIC tube 111 is connected with one end of the capacitor 131 and is used as the positive end UVB of the U-phase high-voltage area power supply of the intelligent power module 100; the HO1 end of the HVIC tube 111 is connected with the output end of the UH drive circuit 101 in the HVIC tube 111, and is connected with the grid electrode of a U-phase upper bridge arm IGBT (Insulated Gate Bipolar Transistor) tube 121 outside the HVIC tube 111; the VS1 end of the HVIC tube 111 is connected to the negative end of the high voltage region power supply of the UH driver circuit 101 inside the HVIC tube 111, and is connected to the emitter of the IGBT tube 121, the anode of the FRD (Fast Recovery Diode) tube 141, the collector of the U-phase lower arm IGBT tube 124, the cathode of the FRD tube 144, and the other end of the capacitor 131 outside the HVIC tube 111, and serves as the negative end UVS of the U-phase high voltage region power supply of the intelligent power module 100.

The VB2 end of the HVIC tube 111 is connected to the positive end of the high-voltage region power supply of the VH driver circuit 102 inside the HVIC tube 111, and one end of the capacitor 132 is connected outside the HVIC tube 111 as the positive end VVB of the V-phase high-voltage region power supply of the intelligent power module 100; the HO2 end of the HVIC tube 111 is connected with the output end of the VH drive circuit 102 in the HVIC tube 111, and is connected with the grid of the V-phase upper bridge arm IGBT tube 122 outside the HVIC tube 111; the VS2 end of the HVIC tube 111 is connected to the negative end of the high voltage area power supply of the VH drive circuit 102 inside the HVIC tube 111, and is connected to the emitter of the IGBT tube 122, the anode of the FRD tube 142, the collector of the V-phase lower arm IGBT tube 125, the cathode of the FRD tube 145, and the other end of the capacitor 132 outside the HVIC tube 111, and serves as the negative end VVS of the W-phase high voltage area power supply of the intelligent power module 100.

The VB3 end of the HVIC tube 111 is connected to the positive end of the high voltage area power supply of the WH drive circuit 103 inside the HVIC tube 111, and one end of the capacitor 133 is connected outside the HVIC tube 111 as the positive end WVB of the W-phase high voltage area power supply of the intelligent power module 100; the HO3 end of the HVIC tube 111 is connected with the output end of the WH drive circuit 103 in the HVIC tube 111, and is connected with the grid of the W-phase upper bridge arm IGBT tube 123 outside the HVIC tube 111; the VS3 end of the HVIC tube 111 is connected to the negative end of the high voltage area power supply of the WH drive circuit 103 inside the HVIC tube 111, and is connected to the emitter of the IGBT tube 123, the anode of the FRD tube 143, the collector of the W-phase lower arm IGBT tube 126, the cathode of the FRD tube 146, and the other end of the capacitor 133 outside the HVIC tube 111, and serves as the negative end WVS of the W-phase high voltage area power supply of the intelligent power module 100.

The LO1 end of the HVIC tube 111 is connected with the output end of the UL driving circuit 104 inside the HVIC tube 111, and is connected with the grid electrode of the U-phase lower bridge arm IGBT tube 124 outside the HVIC tube 111; the LO2 end of the HVIC tube 111 is connected with the output end of the VL drive circuit 105 in the HVIC tube 111, and is connected with the grid of the V-phase lower bridge arm IGBT tube 125 outside the HVIC tube 111; the LO3 end of the HVIC tube 111 is connected with the output end of the WL driving circuit 106 inside the HVIC tube 111, and is connected with the grid electrode of the W-phase lower bridge arm IGBT tube 126 outside the HVIC tube 111; the emitter of the IGBT tube 124 is connected to the anode of the FRD tube 144, and serves as a U-phase low-voltage reference end UN of the intelligent power module 100; the emitter of the IGBT tube 125 is connected to the anode of the FRD tube 145, and serves as the V-phase low-voltage reference terminal VN of the intelligent power module 100; the emitter of the IGBT tube 126 is connected to the anode of the FRD tube 146, and serves as a W-phase low-voltage reference terminal WN of the intelligent power module 100; the collector of the IGBT tube 121, the cathode of the FRD tube 141, the collector of the IGBT tube 122, the cathode of the FRD tube 142, the collector of the IGBT tube 123, and the cathode of the FRD tube 143 are connected to each other, and serve as a high voltage input terminal P of the intelligent power module 100, where P is generally connected to 300V.

The HVIC tube 111 functions to:

VCC is the positive end of the power supply of the HVIC tube 111, and GND is the negative end of the power supply of the HVIC tube 111; the VCC-GND voltage is typically 15V; VB1 and VS1 are respectively the positive pole and the negative pole of the power supply of the U-phase high-voltage area, and HO1 is the output end of the U-phase high-voltage area; VB2 and VS2 are respectively the positive pole and the negative pole of the power supply of the V-phase high-voltage area, and HO2 is the output end of the V-phase high-voltage area; VB3 and VS3 are respectively the positive pole and the negative pole of the power supply of the W-phase high-voltage area, and HO3 is the output end of the W-phase high-voltage area; the LO1, LO2 and LO3 are the output terminals of the U-phase, V-phase and W-phase low-voltage regions, respectively.

Transmitting 0 or 5V logic input signals of input terminals HIN1, HIN2, HIN3 and LIN1, LIN2 and LIN3 to output terminals HO1, HO2, HO3 and LO1, LO2 and LO3 respectively, wherein HO1 is a logic output signal of VS1 or VS1+15V, HO2 is a logic output signal of VS2 or VS2+15V, HO3 is a logic output signal of VS3 or VS3+15V, and LO1, LO2 and LO3 are logic output signals of 0 or 15V; input signals of the same phase cannot be simultaneously high, that is, HIN1 and LIN1, HIN2 and LIN2, HIN3 and LIN3 cannot be simultaneously high.

The recommended circuit of the smart power module 100 in actual operation is shown in fig. 1 b:

an external capacitor 135 between the UVB and the UVS; an external capacitor 136 is arranged between the VVB and the VVS; a capacitor 137 is externally connected between the WVB and the WVS; here, the

capacitors

131, 132, 133 mainly play a role of filtering, and the

capacitors

135, 136, 137 mainly play a role of storing electricity; UN, VN, WN are connected with Pin7 of MCU tube 200 and connected with one end of resistor 138; the other end of the resistor 138 is COM; the Pin1 of the MCU tube 200 is connected with the UHIN end of the intelligent power module 100; the Pin2 of the MCU tube 200 is connected with the VHIN end of the intelligent power module 100; the Pin3 of the MCU tube 200 is connected with the WHIN end of the intelligent power module 100; the Pin4 of the MCU tube 200 is connected with the ULIN end of the intelligent power module 100; the Pin5 of the MCU tube 200 is connected with the VLIN end of the intelligent power module 100; pin6 of MCU tube 200 is connected to WLIN terminal of intelligent power module 100.

The U-phase is taken as an example to illustrate the working state of the intelligent power module 100:

1. when the Pin4 of the MCU tube 200 sends a high level signal, the Pin1 of the MCU tube 200 must send a low level signal, which makes LIN1 high and HIN1 low, at this time, LO1 outputs high and HO1 outputs low, so that the IGBT tube 124 is turned on, the IGBT tube 121 is turned off, and the VS1 voltage is about 0V; the FRD tube 144 is forward biased, VCC charges the capacitor 131 and the capacitor 135 through the IGBT tube 124, and when the duration of the LIN1 being high level is long enough or the remaining capacity before the capacitor 131 and the capacitor 135 are charged is large enough, the VB1 obtains a voltage close to 15V for VS 1;

2. when Pin1 of MCU tube 200 sends out a high level signal, Pin4 of MCU tube 200 must send out a low level signal, which makes LIN1 low and HIN1 high, at this time, LO1 outputs low and HO1 outputs high, so that IGBT tube 124 is turned off, IGBT tube 121 is turned on, VS1 voltage is about 300V, VB1 voltage is raised to about 315V, the U-phase high voltage region is maintained to operate through the electric quantity of capacitor 131 and capacitor 135, if the duration of HIN1 high level is short enough or the electric quantity stored in capacitor 131 and capacitor 135 is enough, VB1 can maintain the voltage of VS1 above 14V during the U-phase high voltage region operation.

Therefore, the power device with high adaptability is provided, the adaptability of the silicon intelligent power module, the gallium nitride intelligent power module and the silicon carbide intelligent power module can be improved, and the technical advantages of the silicon intelligent power module, the gallium nitride intelligent power module and the silicon carbide intelligent power module can be brought into play.

In order to better understand the above technical solutions, exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.

Fig. 2 is a circuit configuration diagram of a power device according to an embodiment of the present application.

As shown in fig. 2, the power device 4100 includes: the switching circuit comprises an SS input end, first to third upper bridge

arm switching tubes

4121, 4122 and 4123, first to third lower bridge

arm switching tubes

4124, 4125 and 4126, a UH driving circuit 4101, a VH driving circuit 4102 and a WH driving circuit 4103 which are connected with the SS input end and respectively drive the first to third upper bridge

arm switching tubes

4121, 4122 and 4123, and a UL/VL/WL driving circuit 4104 which is connected with the SS input end and drives the first to third lower bridge

arm switching tubes

4124, 4125 and 4126.

The UH driving circuit 4101 is connected with a first upper bridge arm switching tube 4121, the VH driving circuit 4102 is connected with a second upper bridge arm switching tube 4122, the WH driving circuit 4103 is connected with a third upper bridge arm switching tube 4123, and the UL/VL/WL driving circuit 4104 is respectively connected with first to third lower bridge

arm switching tubes

4124, 4125 and 4126, wherein when the SS input end is at a first level, the UH driving circuit 4101, the VH driving circuit 4102 and the WH driving circuit 4103 output high-low level signals of a first voltage range, when the SS input end is at a second level, the UH driving circuit 4101, the VH driving circuit 4102 and the WH driving circuit 4103 output high-low level signals of a second voltage range, and when the SS input end is at a third level, the UH driving circuit 4101, the VH driving circuit 4102 and the WH driving circuit 4103 output high-low level signals of a third voltage range; when the SS input terminal is at the first level, the UL/VL/WL driver circuit 4104 outputs a high/low level signal in the first voltage range, when the SS input terminal is at the second level, the UL/VL/WL driver circuit 4104 outputs a high/low level signal in the second voltage range, and when the SS input terminal is at the third level, the UL/VL/WL driver circuit 4104 outputs a high/low level signal in the third voltage range. The first level is a power supply level VCC, the second level is 0, the third level is VCC/2, the first voltage range is 0-3V, the second voltage range is 0-15V, and the third voltage range is 0-20V.

Specifically, referring to fig. 2, a UH driver circuit 4101, a VH driver circuit 4102, a WH driver circuit 4103, and a UL/VL/WL driver circuit 4104 are integrated inside an HVIC tube 4111, and a VCC terminal of the HVIC tube 4111 serves as a low-voltage region power supply positive terminal VDD of the power device 4100, and VDD is generally 15V; inside the HVIC tube 4111, the VCC terminal is connected to the positive terminals of the power supply sources of the UH drive circuit 4101, the VH drive circuit 4102, the WH drive circuit 4103, and the UL/VL/WL drive circuit 4104.

The HIN1 end of the HVIC tube 4111 is used as the U-phase upper bridge arm input end UHIN of the power device 4100, and is connected with the input end of the UH drive circuit 4101 inside the HVIC tube 4111; the HIN2 end of the HVIC tube 4111 serves as the V-phase upper arm input terminal VHIN of the power device 4100, and is connected to the input terminal of the VH drive circuit 4102 inside the HVIC tube 4111; the HIN3 end of the HVIC tube 4111 serves as the W-phase upper bridge arm input end WHIN of the power device 4100, and is connected with the input end of the WH drive circuit 4103 inside the HVIC tube 4111; the LIN1 end of the HVIC tube 4111 serves as the U-phase lower arm input terminal ULINs of the power device 4100, and is connected to the first input end of the UL/VL/WL driver circuit 4104 inside the HVIC tube 4111; the LIN2 end of the HVIC tube 4111 serves as the V-phase lower arm input terminal VLIN of the power device 4100, and is connected to the second input terminal of the UL/VL/WL driver circuit 4104 inside the HVIC tube 4111; the LIN3 end of the HVIC tube 4111 is used as the W-phase lower bridge arm input end WLIN of the power device 4100, and is connected with the third input end of the UL/VL/WL driving circuit 4104 inside the HVIC tube 4111; here, six input terminals of U, V, W three phases of the power device 4100 receive input signals of 0V or 5V; the GND terminal of the HVIC tube 4111 serves as the negative terminal COM of the low-voltage power supply of the power device 100, and is connected to the negative terminal COM of the power supply of the UH driver circuit 4101, the VH driver circuit 4102, the WH driver circuit 4103, and the UL/VL/WL driver circuit 4104.

The VB1 end of HVIC tube 4111 is connected inside HVIC tube 4111 to the positive end of the high voltage region power supply of UH driver circuit 4101, and outside HVIC tube 4111 is connected to one end of capacitor 4131 and serves as the positive end UVB of the U-phase high voltage region power supply of power device 4100; the HO1 end of the HVIC tube 4111 is connected to the output end of the UH driver circuit 4101 inside the HVIC tube 4111, and is connected to the control electrode of the U-phase upper arm switch tube 4121 outside the HVIC tube 4111; the VS1 end of the HVIC tube 4111 is connected to the negative end of the high voltage region power supply of the UH driver circuit 4101 inside the HVIC tube 4111, and is connected to the negative output terminal of the U-phase upper arm switch tube 4121, the positive output terminal of the U-phase lower arm switch tube 4124, and the other end of the capacitor 4131 outside the HVIC tube 4111, and serves as the negative U-phase high voltage region power supply terminal UVS of the power device 4100.

A VB2 end of the HVIC tube 4111 is connected to the positive end of the high-voltage region power supply of the VH driver circuit 4102 inside the HVIC tube 4111, and one end of a capacitor 4132 is connected outside the HVIC tube 4111 as the positive end VVB of the U-phase high-voltage region power supply of the power device 4100; an HO2 terminal of the HVIC tube 4111 is connected to an output terminal of the VH drive circuit 4102 inside the HVIC tube 4111, and is connected to a control electrode of the V-phase upper arm switching tube 4122 outside the HVIC tube 4111; the VS2 end of the HVIC tube 4111 is connected to the negative end of the high voltage region power supply of the VH drive circuit 4102 inside the HVIC tube 4111, and is connected to the negative output electrode of the upper arm switch tube 4122, the positive output electrode of the V-phase lower arm switch tube 4125, and the other end of the capacitor 4132 outside the HVIC tube 4111, and serves as the negative W-phase high voltage region power supply end VVS of the power device 4100.

A VB3 end of the HVIC tube 4111 is connected to the positive end of the high-voltage power supply of the WH drive circuit 4103 inside the HVIC tube 4111, and one end of a capacitor 4133 is connected outside the HVIC tube 4111 as the positive end WVB of the W-phase high-voltage power supply of the power device 4100; the HO3 end of the HVIC tube 4111 is connected to the output end of the WH drive circuit 4103 inside the HVIC tube 4111, and is connected to the control electrode of the W-phase upper arm switch tube 4123 outside the HVIC tube 4111; the VS3 end of the HVIC tube 4111 is connected to the negative end of the high voltage region power supply of the WH drive circuit 4103 inside the HVIC tube 4111, and is connected to the negative output terminal of the switch tube 4123, the positive output terminal of the W-phase lower arm switch tube 4126, and the other end of the capacitor 4133 outside the HVIC tube 4111, and serves as the negative W-phase high voltage region power supply terminal WVS of the power device 4100.

The LO1 end of the HVIC tube 4111 is connected with the control electrode of the U-phase lower bridge arm switching tube 4124; the LO2 end of the HVIC tube 4111 is connected with the control electrode of the V-phase lower bridge arm switching tube 4125; an LO3 end of the HVIC tube 4111 is connected with a control electrode of the W-phase lower bridge arm switching tube 4126; the output negative electrode of the U-phase lower arm switching tube 4124 serves as a U-phase low-voltage reference end UN of the power device 4100; the output negative electrode of the V-phase lower arm switching tube 4125 serves as a V-phase low-voltage reference terminal VN of the power device 4100; the output negative electrode of the W-phase lower arm switching tube 4126 serves as a W-phase low-voltage reference terminal WN of the power device 4100.

The output positive electrode of the U-phase upper arm switching tube 4121, the output positive electrode of the V-phase upper arm switching tube 4122, and the output positive electrode of the W-phase upper arm switching tube 4123 are connected to each other, and serve as a high voltage input terminal P of the power device 4100, where P is generally 300V. Here, the supply voltage of VDD is 15V.

Here, the switching tubes 4121 to 4126 may be a combination of an IGBT (i.e., a Si device) and an FRD tube connected in parallel, a combination of an IGBT (IGBT tube) and a GaN SBD (Schottky Barrier Diode) tube, a GaN nmos (Metal Oxide Semiconductor) tube (i.e., a GaN device), a combination of a GaN MOS tube and an FRD tube, or a combination of a GaN MOS tube and a GaN SBD tube; the transistor may be a combination of an IGBT transistor and a SiC SBD transistor, a SiC MOS transistor (i.e., a SiC device), a combination of a SiC MOS transistor and an FRD transistor, or a combination of a SiC MOS transistor and a SiC SBD transistor.

HVIC tube 4111 functions as:

1. when the SS input terminal is at VCC level, HO1 to HO3 and LO1 to LO3 output high and low level signals of 0 to 3V, that is, when the SS input terminal is at the first level, UH driver circuit 4101, VH driver circuit 4102, WH driver circuit 4103 and UL/VL/WL driver circuit 4104 output high and low level signals of the first voltage range;

2. when the SS input terminal is at 0 level, HO1 to HO3 and LO1 to LO3 output high and low level signals of 0 to 15V, that is, when the SS input terminal is at the second level, UH driver circuit 4101, VH driver circuit 4102, WH driver circuit 4103 and UL/VL/WL driver circuit 4104 output high and low level signals of the second voltage range;

3. when the SS input terminal is at VCC/2 level, HO1 to HO3 and LO1 to LO3 output high-low level signals of 0 to 20V, that is, when the SS input terminal is at the third level, UH driver circuit 4101, VH driver circuit 4102, WH driver circuit 4103 and UL/VL/WL driver circuit 4104 output high-low level signals in the third voltage range.

In practical application, when the switching tubes 4121-4126 are combination schemes including IGBT tubes, the SS input terminal is set to a second level (e.g., 0); when the switch tubes 4121-4126 are combined with GaN MOS tubes, the SS input terminal is set to a first level (e.g., VCC); when the switching tubes 4121-4126 are combined with SiC MOS tubes, the SS input is set to a third level (e.g., VCC/2).

Therefore, the power supply voltage of the power device is 15V, the peripheral circuit does not need to be modified, and the power consumption of the high-voltage integrated circuit is not substantially increased; the driving GaN device, the SiC device and the driving Si device are the same high-voltage integrated circuit, so that no material mixing risk exists in the production process, material organization is facilitated, and material cost is reduced; the GaN device is driven to use 3V voltage, the SiC device is driven to use 20V voltage, and the Si device is driven to use 15V voltage, so that the GaN device, the SiC device and the Si device are in a complete conduction state in the conduction process and cannot be broken down, and the respective performances are exerted. The GaN/SiC intelligent power module solution completely compatible with the traditional Si intelligent power module plays an important role in upgrading and updating the intelligent power module, popularizing and applying the intelligent power module and saving energy of variable-frequency household appliances, particularly variable-frequency air conditioners.

The present application is further described with reference to the following specific examples.

Fig. 3a to 3h illustrate different combinations of switching tubes, since the switching tubes 4121 to 4126 have the same structure, taking the U-phase upper arm switching tube 4121 as an example:

fig. 3a shows the combination of Si IGBT and Si FRD: the collector of the Si IGBT tube 41211 is connected to the cathode of the Si FRD tube 41212, and serves as the output anode of the U-phase upper arm switching tube 4121; an emitting electrode of the Si IGBT tube 41211 is connected with an anode of the Si FRD tube 41212 and is used as an output cathode of the U-phase upper bridge arm switching tube 4121; the gate of the Si IGBT 41211 serves as the control electrode of the U-phase upper arm switching tube 4121.

FIG. 3b shows the combination of Si IGBT and GaN SBD tube or SiC SBD tube: the collector of the Si IGBT tube 41211 is connected with the cathode of the GaN SBD tube or the SiC SBD tube 41212 and is used as the output anode of the U-phase upper bridge arm switch tube 4121; an emitting electrode of the Si IGBT tube 41211 is connected with an anode of the GaN SBD tube or the SiC SBD tube 41212 and is used as an output cathode of the U-phase upper bridge arm switch tube 4121; the gate of the Si IGBT 41211 serves as the control electrode of the U-phase upper arm switching tube 4121.

Fig. 3c shows the GaN MOS approach: the drain electrode of the GaN MOS transistor 41211 is used as the output anode of the U-phase upper arm switching transistor 4121; the source electrode of the GaN MOS transistor 41211 is used as the output negative electrode of the U-phase upper arm switching transistor 4121; the gate of the GaN MOS transistor 41211 serves as the control electrode of the U-phase upper arm switching transistor 4121.

Fig. 3d shows the combination of GaN MOS and Si FRD: the drain electrode of the GaN MOS tube 41211 is connected with the cathode of the Si FRD tube 41212 and serves as the output anode of the U-phase upper arm switching tube 4121; the source electrode of the GaN MOS tube 41211 is connected with the anode of the SiFRD tube 41212 and serves as the output cathode of the U-phase upper arm switch tube 4121; the gate of the GaN MOS transistor 41211 serves as the control electrode of the U-phase upper arm switching transistor 4121.

FIG. 3e shows the combination of GaN MOS and GaN SBD or SiC SBD tubes: the drain electrode of the GaN MOS tube 41211 is connected with the cathode of the GaN SBD tube or the SiC SBD tube 41212 and is used as the output anode of the U-phase upper bridge arm switch tube 4121; the source electrode of the GaN MOS transistor 41211 is connected with the anode of the GaN SBD transistor or the SiC SBD transistor 41212 and serves as the output cathode of the U-phase upper arm switching transistor 4121; the gate of the Si IGBT 41211 serves as the control electrode of the U-phase upper arm switching tube 4121.

Fig. 3f shows the SiC MOS approach: the drain electrode of the SiC MOS transistor 41211 serves as the output anode of the U-phase upper arm switching transistor 4121; the source electrode of the SiC MOS transistor 41211 serves as the output negative electrode of the U-phase upper arm switching transistor 4121; the gate of the SiC MOS transistor 41211 serves as the control electrode of the U-phase upper arm switching transistor 4121.

Fig. 3g shows the combination of SiC MOS and Si FRD: the drain electrode of the SiC MOS transistor 41211 is connected to the cathode of the Si FRD transistor 41212, and serves as the output anode of the U-phase upper arm switching transistor 4121; the source electrode of the SiC MOS transistor 41211 is connected to the anode of the SiFRD transistor 41212, and serves as the output cathode of the U-phase upper arm switching transistor 4121; the gate of the SiC MOS transistor 41211 serves as the control electrode of the U-phase upper arm switching transistor 4121.

FIG. 3h shows the combination of SiC MOS and SiC SBD or GaN SBD: the drain electrode of the SiC MOS transistor 41211 is connected to the cathode of the SiC SBD transistor or GaN SBD transistor 41212 and serves as the output anode of the U-phase upper arm switching transistor 4121; the source electrode of the SiC MOS transistor 41211 is connected to the anode of the SiC SBD transistor or GaN SBD transistor 41212, and serves as the output cathode of the U-phase upper arm switching transistor 4121; the gate of the Si IGBT 41211 serves as the control electrode of the U-phase upper arm switching tube 4121.

Fig. 4a and 4b show embodiments of upper and lower bridge driving circuits, and since the structure of the UH driving circuit 4101, the VH driving circuit 4102 and the WH driving circuit 4103 are identical, the structure of the UH driving circuit 4101 is illustrated in fig. 4a, and the structure of the UL/VL/WL driving circuit 4104 is illustrated in fig. 4 b.

The structure of the UH driver circuit 4101, VH driver circuit 4102 or WH driver circuit 4103 will be described first with reference to fig. 4 a.

Referring to fig. 4a, the UH drive circuit 4101, VH drive circuit 4102, or WH drive circuit 4103 includes: a first input sub-circuit 41011, the first input sub-circuit 41011 being connected to the SS input terminal, the first input sub-circuit 41011 having a first output terminal to a fourth output terminal, wherein when the SS input terminal is at a second level, the first output terminal and the second output terminal output a trigger pulse, the third output terminal outputs a trigger pulse of a first time length, when the SS input terminal is at the first level, the first output terminal and the second output terminal output a trigger pulse, the third output terminal outputs a trigger pulse of a second time length, the second time length being greater than the first time length; when the SS input end is at a third level, the first output end and the second output end output trigger pulses, and the fourth output end outputs trigger pulses with a second time length; first to fourth switching tubes 41012, 41013, 41014 and 41021, the first switching tube 41012 being connected to the first output terminal, the second switching tube 41013 being connected to the second output terminal, the third switching tube 41014 being connected to the third output terminal, the fourth switching tube 41021 being connected to the fourth output terminal; a first voltage output sub-circuit 41023, the first voltage output sub-circuit 41023 is respectively connected with the first switching tube to the third switching tube 41012, 41013 and 41014; a second voltage output sub-circuit 41024, wherein the second voltage output sub-circuit 41024 is connected with the fourth switching tube 41021; the output sub-circuit 41017 and the output sub-circuit 41017 are connected to the first voltage output sub-circuit 41023 and the second voltage output sub-circuit 41024, respectively.

With continued reference to fig. 4a, the first voltage output sub-circuit 41023 comprises: a latch and buck module 41016, a first switching module 41018, and a first latch module 41015. The latch and buck module 41016 is connected to the first switch tube 41012 and the second switch tube 41013, the first switch module 41018 is connected to the latch and buck module 41016 and the power supply, the first latch module 41015 is connected to the third switch tube 41014, the latch module 41015 controls the first switch module 41018, when the third switch tube 41014 is conducted for a first time period, the power supply is used as the output voltage of the first voltage output sub-circuit 41023, and when the third switch tube 41014 is conducted for a second time period, the output voltage of the latch and buck module 41016 is used as the output voltage of the first voltage output sub-circuit 41023.

With continued reference to fig. 4a, second voltage output subcircuit 41024 includes: a first boosting block 41022, a second switching block 41019 and a second latch block 41020. The second switching module 41019 is respectively connected to the first voltage output sub-circuit 41023 and the first boosting module 41022, the second latch module 41020 is connected to the fourth switching tube 41021, the second latch module 41020 controls the second switching module 41019, when the fourth switching tube 41021 is not conducted, the output sub-circuit 41017 is connected to the first voltage output sub-circuit 41023, and when the fourth switching tube 41021 is conducted for a first time period, the output sub-circuit 41017 is connected to the first boosting module 41022.

Specifically, as shown in fig. 4 a: inside the UH drive circuit 4101, VCC is connected to the positive terminal of the power supply of the first input sub-circuit 41011, HIN1 is connected to the input terminal of the first input sub-circuit 41011, SS input terminal is connected to the control terminal of the first input sub-circuit 41011, first output terminal of the first input sub-circuit 41011 is connected to the gate of the first switching tube (e.g., high-voltage DMOS tube) 41012, second output terminal of the first input sub-circuit 41011 is connected to the gate of the second switching tube (high-voltage DMOS tube) 41013, third output terminal of the first input sub-circuit 41011 is connected to the gate of the third switching tube (high-voltage DMOS tube) 41014, fourth output terminal of the first input sub-circuit 41011 is connected to the gate of the fourth switching tube (high-voltage DMOS tube) 41021, GND is connected to the negative terminal of the power supply of the first input sub-circuit 41011, the substrate and source of the first switching tube 41012, the substrate and source of the second switching tube 41013, and the substrate 41014 and source of the third switching tube 41014 are connected to the substrate and source of the second switching, The substrate and the source of the fourth switching tube 41021 are connected.

The drain of the first switching tube 41012 is connected to the first input terminal of the latch and buck module 41016, the drain of the second switching tube 41013 is connected to the second input terminal of the latch and buck module 41016, the drain of the third switching tube 41014 is connected to the enable terminal of the first latch module 41015, the drain of the fourth switching tube 41021 is connected to the enable terminal of the second latch module 41020, the first output terminal of the latch and buck module 41016 is connected to the 1 selection terminal of the first switching module (e.g., analog switch) 41018, the second output terminal of the latch and buck module 41016 is connected to the input terminal of the first output sub-circuit 41017, the output terminal of the first latch module 41015 is connected to the control terminal of the first switching module 41018, the positive terminal of the first switching module 41018 is connected to the power supply terminal of the first output sub-circuit 41017, the output terminal of the first boost module 41022 is connected to the active terminal of the second switching module 41019, the output terminal of the second latch module 41020 is connected to the control terminal of the second switching module 41019, VB1 is connected to the positive terminal of the power supply of the latch module 41015, the positive terminal of the power supply of the latch and buck circuit 41016, the positive terminal of the power supply of the first boost module 41022, and the 0 selection terminal of the first switching module 41018, VS1 is connected to the negative terminal of the power supply of the first latch module 41015, the negative terminal of the power supply of the second latch module 41020, the negative terminal of the power supply of the latch and buck circuit 41016, the negative terminal of the power supply of the first boost module 41022, and the negative terminal of the power supply of the first output sub-circuit 41017, and HO1 is connected to the output terminal of the first output sub-circuit 41017.

The role of the first input sub-circuit 41011 is:

on the rising edge of the signal at the input of the first input sub-circuit 41011, the first output of the first input sub-circuit 41011 outputs a pulse signal with a pulse width of about 300 ns; at the falling edge of the signal at the input terminal of the first input sub-circuit 41011, the second output terminal of the first input sub-circuit 41011 outputs a pulse signal with a pulse width of about 300 ns; when the SS input terminal of the first input sub-circuit 41011 is at VCC level, a pulse signal with a pulse width of about 600ns is output at the third output terminal of the first input sub-circuit 41011; when the SS input terminal of the first input sub-circuit 41011 is at 0 level, a pulse signal with a pulse width of about 300ns is output at the third output terminal of the first input sub-circuit 41011; when the SS input terminal of the first input sub-circuit 41011 is at VCC/2 level, a pulse signal having a pulse width of about 300ns is output at the fourth output terminal of the first input sub-circuit 41011.

The first latching module 41015 functions to:

the output terminal of the first latch module 41015 outputs a high level when the signal at the input terminal of the first latch module 41015 has a low level of 600ns, the output terminal of the first latch module 41015 outputs a low level when the signal at the input terminal of the first latch module 41015 has a low level of 300ns, and the output terminal of the first latch module 41015 outputs a VCC/2 voltage when the signal at the input terminal of the first latch module 41015 never has a low level.

The latch and buck module 41016 functions to:

when the first input terminal of the latching and voltage reducing module 41016 has a low level of 300ns, the second output terminal of the latching and voltage reducing module 41016 outputs a continuous high level; when the 300ns low level appears at the second input terminal of the latch and buck module 41016, a sustained low level is output at the first output terminal of the latch and buck module 41016. That is, two pulse signals split from the signal of HIN1 at two output terminals of the first input sub-circuit 41011 are re-integrated into a complete signal, and the latch and buck module 41016 has a buck circuit therein, and outputs a voltage of 3V for VS1 at a second output terminal of the latch and buck module 41016.

The second latch module 41020 functions as:

when the first input terminal of the latch and buck module 41016 is at the low level of 300ns, the second output terminal of the latch and buck module 41016 outputs a high level continuously, otherwise, the second output terminal outputs a low level.

The output sub-circuit 41017 functions to:

and outputting a signal with the voltage value consistent with the positive end of the power supply at the high level or the voltage value consistent with the negative end of the power supply at the low level and the phase consistent with the HIN 1.

Here, the narrow pulse signal of 300ns/600ns is used to control the first to

third switching tubes

41012, 41013, 41014 and the fourth switching tube 41020, so as to reduce the power consumption by shortening the conduction time of the first to

third switching tubes

41012, 41013, 41014 and the fourth switching tube 41020.

The working principle is as follows:

after the signal of HIN1 passes through the first input sub-circuit 41011, a narrow pulse of 300ns is output at the first output end and the second output end of the first input sub-circuit 41011 at the rising edge and the falling edge of the signal, respectively, the narrow pulse controls the first switch tube 41012 and the second switch tube 41013 to conduct for 300ns, respectively, so that the first input end and the second input end of the latch and buck module 41016 generate low levels of 300ns, respectively, and the latch and buck module 41016 is internally provided with devices such as an RS flip-flop, and the two low level signals are recombined into a complete signal in phase with HIN 1.

When no GaN MOS transistor or SiC MOS transistor exists in the switch transistor, the SS input terminal is at 0 level, the fourth output terminal of the first input sub-circuit 41011 does not generate a high level pulse, the fourth switch transistor 41021 is not conducted, the input terminal of the second latch module 41020 does not generate a low level, the second switching module 41019 is in an off state, the third output terminal of the first input sub-circuit 41011 generates a 300ns high level pulse, the third switch transistor 41014 generates a 300ns conduction, the input terminal of the first latch module 41015 generates a 300ns low level, the output terminal of the first latch module 41015 outputs a high level to a low level, the positive terminal of the power supply of the output sub-circuit 41017 is connected to VB1, that is, the output sub-circuit 17 outputs a high-low level signal of 0 to 15V.

When a GaN MOS transistor exists in the switching tube, the SS input terminal is VCC level, the fourth output terminal of the first input sub-circuit 41011 does not have high level, the fourth switching tube 41021 is not turned on, the input terminal of the second latch module 41020 does not have low level, the output terminal of the second latch module 41020 keeps low level, the second switching module 41019 is in off state, the third output terminal of the first input sub-circuit 41011 has high level pulse of 600ns, the third switching tube 41014 has conduction of 600ns, the input terminal of the first latch module 41015 has low level of 600ns, the output terminal of the first latch module 41015 outputs high level from low level, the power supply of the output sub-circuit 41017 is connected with the positive terminal of the latch and voltage reduction circuit 41016, that is, the output sub-circuit 41017 outputs high and low level signals of 0 to 3V.

When SiC MOS transistors exist in the power transistor, SS is VCC/2 level, the third output terminal of the first input sub-circuit 41011 does not have high level, the third switching transistor 41014 is not turned on, the input terminal of the first latch module 41015 does not have low level, the output terminal of the first latch module 41015 is always at low level, the first switching module 41018 is in a suspended state, a 300ns high level pulse appears at the fourth output terminal of the first input sub-circuit 41011, a 300ns conduction appears at the fourth switching transistor 41021, a 300ns low level appears at the input terminal of the second latch module 41020, the output terminal of the second latch module 41020 outputs high level, the power supply of the output sub-circuit 41017 is connected with the positive terminal of the first boost module 41022, that is, the output sub-circuit 41017 outputs high and low level signals of 0 to 20V.

The structure of the UL/VL/WL driver circuit 4104 will be described below with reference to FIG. 4 b.

Referring to fig. 4b, the UL/VL/WL driver circuit 4104 includes: a second input sub-circuit 41041, a boost sub-circuit 41050, a buck sub-circuit 41048, a switching circuit 41019, and a second voltage output sub-circuit 41049. The second input sub-circuit 41041 includes first to fourth output terminals, wherein the fourth output terminal outputs a first trigger pulse when the SS input terminal is at the second level, the fourth output terminal outputs a second trigger pulse when the SS input terminal is at the first level, the first trigger pulse is opposite to the second trigger pulse, and the fifth output terminal outputs a trigger pulse when the SS input terminal is at the third level. The boost sub-circuit 41050 boosts the supply voltage to the third voltage range. The buck subcircuit 41048 steps down the power supply voltage to a first voltage range. The switching circuit 41019 is connected to the boosting sub-circuit 41050, and the switching circuit 41019 is controlled by a fifth output terminal. The third voltage output sub-circuit 41051 is connected to the second input sub-circuit 41041, the boosting sub-circuit 41050, the switching circuit 41019 and the step-down sub-circuit 41048, wherein when the fourth output terminal outputs the first trigger pulse, the second input sub-circuit 41041 outputs a high-low level signal of the second voltage range, when the fourth output terminal outputs the second trigger pulse, the second input sub-circuit 41041 outputs a high-low level signal of the first voltage range, and when the fifth output terminal outputs the trigger pulse, the second input sub-circuit 41041 outputs a high-low level signal of the third voltage range.

With continued reference to fig. 4b, the third voltage output sub-circuit 41051 comprises: a UL output module 41042, a VL output module 41043, and a WL output module 41044 connected to the first to third output terminals of the second input sub-circuit 41041, respectively; third to

fifth switching modules

41045, 41046 and 41047 connected to the UL output module 41042, the VL output module 41043 and the WL output module 41044, respectively, wherein the third to

fifth switching modules

41045, 41046 and 41047 select the power supply voltage or the output voltage of the step-down sub-circuit 41048 as the output voltage of the third voltage output sub-circuit 41051 according to the fourth output terminal of the second input sub-circuit 41041.

Specifically, as shown in fig. 4 b: inside the UL/VL/WL driver circuit 4104, VCC is connected to the power supply source positive terminal of the second input sub-circuit 41041, the power supply source positive terminal of the voltage boosting sub-circuit 41050, the power supply source positive terminal of the voltage lowering sub-circuit 41048, the 0 selection terminal of the third changeover switch (e.g., analog switch) 41045, the 0 selection terminal of the fourth changeover switch (e.g., analog switch) 41046, the 0 selection terminal of the fifth changeover switch (e.g., analog switch) 41047, LIN1 is connected to the first input terminal of the second input sub-circuit 41041, LIN2 is connected to the second input terminal of the second input sub-circuit 41041, LIN3 is connected to the third input terminal of the second input sub-circuit 41041, and the SS input terminal is connected to the control terminal of the second input sub-circuit 41041.

A first output terminal of the second input sub-circuit 41041 is connected to an input terminal of the UL output circuit 41042, a second output terminal of the second input sub-circuit 41041 is connected to an input terminal of the VL output circuit 41043, a third output terminal of the second input sub-circuit 41041 is connected to an input terminal of the WL output circuit 41044, a fourth output terminal of the second input sub-circuit 41011 is connected to a control terminal of the second switching module 41045, a control terminal of the third switching module 41046, and a control terminal of the fourth switching module 41047, respectively, GND is connected to a power supply source negative terminal of the second input sub-circuit 41041, a power supply source negative terminal of the step-down sub-circuit 41048, a power supply source negative terminal of the UL output circuit 41042, a power supply source negative terminal of the VL output circuit 41043, and a power supply source negative terminal of the WL output circuit 41044, output terminals of the step-down sub-circuit 41048 are connected to a 1 selection terminal of the third switching module 41045, a 1 selection terminal of the fourth switching module 41046, and a 1 selection terminal of the fifth switching module 41047, the LO1 is connected to the output terminal of the UL output circuit 41042, the LO2 is connected to the output terminal of the VL output circuit 41043, and the LO3 is connected to the output terminal of the WL output circuit 41043.

The second input sub-circuit 41041 functions as:

a signal in phase with the first input terminal of second input sub-circuit 41041 is output at a first output terminal of second input sub-circuit 41041, a signal in phase with the second input terminal of second input sub-circuit 41041 is output at a second output terminal of second input sub-circuit 41041, and a signal in phase with the third input terminal of second input sub-circuit 41041 is output at a third output terminal of second input sub-circuit 41041. When the SS input terminal of the second input sub-circuit 41041 is at VCC level, a high level is output at the fifth output terminal of the second input sub-circuit 41041, when the SS input terminal of the second input sub-circuit 41041 is at 0 level, a low level is output at the fourth output terminal of the second input sub-circuit 41041, and when the SS input terminal of the second input sub-circuit 41041 is at VCC/2 level, a high level is output at the fourth output terminal of the second input sub-circuit 41041.

The buck subcircuit 41048 functions to:

a voltage of 3V to GND is output from the output terminal of the step-down sub-circuit 41048.

The function of the boost sub-circuit 41050 is:

the output terminal of the boosting sub-circuit 41050 outputs a voltage of 20V with respect to GND.

The UL output circuit 41042 functions to:

and outputting a signal with the voltage value at the high level consistent with the positive end of the power supply, the voltage value at the low level consistent with the negative end of the power supply and the phase consistent with LIN 1.

The VL output circuit 41043 functions to:

and outputting a signal with the voltage value at the high level consistent with the positive end of the power supply, the voltage value at the low level consistent with the negative end of the power supply and the phase consistent with LIN 2.

The role of the WL output circuit 41044 is:

and outputting a signal with the voltage value at the high level consistent with the positive end of the power supply, the voltage value at the low level consistent with the negative end of the power supply and the phase consistent with LIN 3.

The working principle is as follows:

after the signals of LIN1, LIN2 and LIN3 pass through the second input sub-circuit 41041, the signals are respectively output at the first output terminal, the second output terminal and the third output terminal of the second input sub-circuit 41041 with the same phases as LIN1, LIN2 and LIN3, and the signals are shaped into square waves.

When a Si IGBT tube exists in the switching tube, the SS input terminal is at 0 level, the fourth output terminal of the second input sub-circuit 4104 outputs a level from high to low, the fixed terminal of the third switching module 41045 is connected to the 0 selection terminal of the third switching module 41045, the fixed terminal of the fourth switching module 41046 is connected to the 0 selection terminal of the fourth switching module 41046, and the fixed terminal of the fifth switching module 41047 is connected to the 0 selection terminal of the fifth switching module 41047, so that the LO1 outputs a signal of 0 to 15V in phase with the input terminal of the UL output circuit 41042, the LO2 outputs a signal of 0 to 15V in phase with the input terminal of the VL output circuit 41043, and the LO3 outputs a signal of 0 to 15V in phase with the input terminal of the WL output circuit 41044.

When a GaN MOS transistor exists in the switching tube, the SS input terminal is VCC level, the fourth output terminal of the second input sub-circuit 41041 outputs level from low to high, the fixed terminal of the third switching module 41045 is connected to the 1 selection terminal of the third switching module 41045, the fixed terminal of the fourth switching module 41046 is connected to the 1 selection terminal of the fourth switching module 41046, and the fixed terminal of the fifth switching module 41047 is connected to the 1 selection terminal of the fifth switching module 41047, so that the LO1 outputs signals of 0 to 3V in phase with the input terminal of the UL output circuit 41042, the LO2 outputs signals of 0 to 3V in phase with the input terminal of the VL output circuit 41043, and the LO3 outputs signals of 0 to 3V in phase with the input terminal of the WL output circuit 41044.

When there is a SiC MOS transistor in the switching transistor, the SS input terminal is VCC/2 level, the fourth output terminal of the second input sub-circuit 41041 is kept at low level, the third switching module 41045 is in a floating state, the fourth switching module 41046 is in a floating state, the fifth switching module 41047 is in a floating state, the fifth output terminal of the second input sub-circuit 41041 is at high level, the fixed terminal of the switching circuit 41019 is connected to the output terminal of the boost sub-circuit 41050, so that the LO1 outputs a signal of 0 to 20V in phase with the input terminal of the UL output circuit 41042, the LO2 outputs a signal of 0 to 20V in phase with the input terminal of the VL output circuit 41043, and the LO3 outputs a signal of 0 to 20V in phase with the input terminal of the WL output circuit 41044.

The technical scheme in the embodiment of the application at least has the following technical effects or advantages:

In order to achieve the purpose, the application also provides an electric appliance which comprises the power device.

In the embodiment of the present application, the electrical appliance may be an air conditioner, a washing machine, a refrigerator, an induction cooker, or the like, and the power device therein may implement the functions of the power device described in the foregoing section.

The electric appliance can improve the adaptability of the silicon intelligent power module, the gallium nitride intelligent power module and the silicon carbide intelligent power module through the power device, and the technical advantages of the silicon intelligent power module, the gallium nitride intelligent power module and the silicon carbide intelligent power module can be brought into play.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.

Claims

1. A power device, comprising:

an SS input end;

the first upper bridge arm switching tube to the third upper bridge arm switching tube and the first lower bridge arm switching tube to the third lower bridge arm switching tube;

a UH drive circuit, a VH drive circuit and a WH drive circuit which are all connected with the SS input end and respectively drive the first upper bridge arm switching tube to the third upper bridge arm switching tube, wherein the UH drive circuit is connected with a first upper bridge arm switch tube, the VH drive circuit is connected with a second upper bridge arm switch tube, the WH drive circuit is connected with a third upper bridge arm switch tube, wherein, when the SS input terminal is at a first level, the UH drive circuit, the VH drive circuit and the WH drive circuit output high-low level signals in a first voltage range, when the SS input end is at a second level, the UH drive circuit, the VH drive circuit and the WH drive circuit output high-low level signals in a second voltage range, when the SS input end is at a third level, the UH drive circuit, the VH drive circuit and the WH drive circuit output high-low level signals in a third voltage range;

and the UL/VL/WL driving circuit is connected with the SS input end and drives the first lower bridge arm switching tube to the third lower bridge arm switching tube, and is respectively connected with the first lower bridge arm switching tube to the third lower bridge arm switching tube, wherein when the SS input end is at a first level, the UL/VL/WL driving circuit outputs high-low level signals in a first voltage range, when the SS input end is at a second level, the UL/VL/WL driving circuit outputs high-low level signals in a second voltage range, and when the SS input end is at a third level, the UL/VL/WL driving circuit outputs high-low level signals in a third voltage range.

2. The power device according to claim 1, wherein the first level is a power supply level VCC, the second level is 0, the third level is VCC/2, the first voltage range is 0 to 3V, the second voltage range is 0 to 15V, and the third voltage range is 0 to 20V.

3. The power device of claim 1, wherein the SS input is set to a second level when the first to third upper arm switching tubes and the first to third lower arm switching tubes include Si devices, the SS input is set to a third level when the first to third upper arm switching tubes and the first to third lower arm switching tubes include SiC devices, and the SS input is set to a first level when the first to third upper arm switching tubes and the first to third lower arm switching tubes include GaN devices.

4. The power device of claim 1, wherein the UH, VH, or WH driver circuit comprises:

the first input sub-circuit is connected with an SS input end, the first input sub-circuit is provided with a first output end to a fourth output end, when the SS input end is at a second level, the first output end and the second output end output trigger pulses, the third output end outputs trigger pulses with a first time length, when the SS input end is at a first level, the first output end and the second output end output trigger pulses, the third output end outputs trigger pulses with a second time length, the second time length is larger than the first time length, when the SS input end is at a third level, the first output end and the second output end output trigger pulses, and the fourth output end outputs trigger pulses with the first time length;

the first switching tube is connected with the first output end, the second switching tube is connected with the second output end, the third switching tube is connected with the third output end, and the fourth switching tube is connected with the fourth output end;

the first voltage output sub-circuit is respectively connected with the first switching tube to the third switching tube;

the second voltage output sub-circuit is connected with the fourth switching tube;

and the output sub-circuit is respectively connected with the first voltage output sub-circuit and the second voltage output sub-circuit.

5. The power device of claim 4, wherein the first voltage output sub-circuit comprises:

the latch and voltage reduction module is connected with the first switch tube and the second switch tube;

the first switching module is respectively connected with the latching and voltage reducing module and the power supply;

and the first latch module is used for controlling the first switching module, when the third switching tube is conducted for a first time length, the power supply is used as the output voltage of the first voltage output sub-circuit, and when the third switching tube is conducted for a second time length, the output voltage of the latch and voltage reduction module is used as the output voltage of the first voltage output sub-circuit.

6. The power device of claim 4, wherein the second voltage output sub-circuit comprises:

a first boost module;

the second switching module is respectively connected with the first voltage output sub-circuit and the first boosting module;

and the second latch module is used for controlling the second switching module, when the fourth switching tube is not switched on, the output sub-circuit is connected with the first voltage output sub-circuit, and when the fourth switching tube is switched on for a first time length, the output sub-circuit is connected with the first boosting module.

7. The power device of claim 1, wherein the UL/VL/WL driver circuit comprises:

a second input sub-module, including a first output terminal to a fifth output terminal, wherein when the SS input terminal is at a second level, the fourth output terminal outputs a first trigger pulse, when the SS input terminal is at a first level, the fourth output terminal outputs a second trigger pulse, the first trigger pulse is opposite to the second trigger pulse, and when the SS input terminal is at a third level, the fifth output terminal outputs a trigger pulse;

a boost sub-circuit that boosts a power supply voltage to the third voltage range;

a buck sub-circuit that steps down the supply voltage to a first voltage range;

the switching circuit is connected with the boosting sub-circuit and is controlled by the fifth output end;

and the third voltage output sub-circuit is connected with the second input sub-circuit, the switch circuit, the voltage reduction sub-circuit and the voltage boosting sub-circuit, wherein when the fourth output end outputs a first trigger pulse, the second input sub-circuit outputs high and low level signals in a second voltage range, when the fourth output end outputs a second trigger pulse, the second input sub-circuit outputs high and low level signals in a first voltage range, and when the fifth output end outputs a trigger pulse, the second input sub-circuit outputs high and low level signals in a third voltage range.

8. The power device of claim 7, wherein the third voltage output sub-circuit comprises:

the UL output module, the VL output module and the WL output module are respectively connected with the first output end to the third output end of the second input sub-circuit;

and the third switching module to the fifth switching module are respectively connected with the UL output module, the VL output module and the WL output module, wherein the third switching module to the fifth switching module select a power supply voltage or an output voltage of the voltage reduction sub-circuit as an output voltage of the third voltage output sub-circuit according to a fourth output end of the second input sub-circuit.

9. An electrical appliance comprising a power device according to any one of claims 1-8.

10. The appliance according to claim 9, wherein the appliance is an air conditioner.