CN109887987B - Array substrate and display module - Google Patents
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- CN109887987B CN109887987B CN201910310317.8A CN201910310317A CN109887987B CN 109887987 B CN109887987 B CN 109887987B CN 201910310317 A CN201910310317 A CN 201910310317A CN 109887987 B CN109887987 B CN 109887987B
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Abstract
The invention provides an array substrate and a display module. The problem of functional circuit unit in the screen body frame and walk the line and receive the space restriction of arc frame, lead to walking the line and lay the difficulty is solved. The method comprises the following steps: the display device comprises a display area with arc corners and a frame area outside the display area, wherein a plurality of functional circuit units electrically connected with the display area are arranged in the frame area, the functional circuit units are distributed along a first direction serving as the extending direction of the display area, and any one functional circuit unit comprises: the signal line group comprises a plurality of transistor groups which are arranged on the same layer and distributed along a second direction perpendicular to the first direction, and a signal line group arranged between the transistor groups, wherein the signal line in the signal line group is electrically connected with the corresponding transistor group.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a display module.
Background
Narrow-frame technology of Active-matrix organic light-emitting diode (AMOLED) display screen technology is receiving attention, and narrower frames are designed, which is beneficial to improving the competitiveness of products. With the increasingly common chamfer design of the display area of the display screen in the market, the technology of realizing the narrow frame in the arc area is also very important. However, the functional circuit units and the routing wires in the screen frame are limited by the space of the arc frame, which causes difficulty in routing wires.
Disclosure of Invention
In view of the foregoing, the present invention provides an array substrate and a display module. The problem of functional circuit unit in the screen body frame and walk the line and receive the space restriction of arc frame, lead to walking the line and lay the difficulty is solved.
An embodiment of the present invention provides an array substrate and a display module, including: the display device comprises a display area with arc corners and a frame area outside the display area, wherein a plurality of functional circuit units electrically connected with the display area are arranged in the frame area, the functional circuit units are distributed along a first direction serving as the extending direction of the display area, and any one functional circuit unit comprises: the signal line group comprises a plurality of transistor groups which are arranged on the same layer and distributed along a second direction perpendicular to the first direction, and a signal line group arranged between the transistor groups, wherein the signal line in the signal line group is electrically connected with the corresponding transistor group.
In one embodiment, the number of the transistor groups is the same as the number of colors of the sub-pixels in the display area.
In one embodiment, the display region has three colors of red, green, and blue sub-pixels, the transistor group has a first transistor group adapted to the red sub-pixel, a second transistor group adapted to the blue sub-pixel, and a third transistor group adapted to the green sub-pixel, and the signal line group is disposed in a gap between the first transistor group, the second transistor group, and the third transistor group.
In one embodiment, the third transistor group is close to the display region, the second transistor group is far from the display region, the first transistor group is between the second transistor group and the third transistor group, and the signal line group includes a first signal line group between the first transistor group and the second transistor group, a third signal line group between the first transistor group and the third transistor group, and a second signal line group on a side of the first transistor group far from the third transistor group in the second direction.
In one embodiment, the first transistor group includes first and second transistors connected in parallel, the first and second transistors are distributed along the second direction, the first signal line group includes a first red data line electrically connected to the channel layer of the first transistor and a second switching signal line electrically connected to the channel layer of the second transistor, the third signal line group includes a second red data line electrically connected to the gates of the first and second transistors through a second gate signal data line, and the array substrate further includes a first drain trace electrically connected to the channel layer of the first transistor and the channel layer of the second transistor.
In one embodiment, the first transistor group further comprises: the array substrate further includes a third transistor and a fourth transistor connected in parallel, the third transistor and the fourth transistor are distributed along the second direction, the first signal line group further includes a first switching signal line, the first red data line is electrically connected to a channel layer of the third transistor, the second red data line is electrically connected to a channel layer of the fourth transistor, the first switching signal line is electrically connected to gates of the third transistor and the fourth transistor through a second gate signal data line, and the array substrate further includes a second drain trace electrically connected to the channel layer of the third transistor and the channel layer of the fourth transistor.
In one embodiment, the second transistor group includes fifth and sixth transistors connected in parallel, the fifth and sixth transistors are distributed along the second direction, the first signal line group includes a first blue data line, the second signal line group includes a second blue data line, the first blue data line is electrically connected to a channel layer of the fifth transistor, the second blue data line is electrically connected to a channel layer of the sixth transistor, the first switching signal line is electrically connected to gates of the fifth and sixth transistors through a third gate signal data line, and the first drain trace is electrically connected to the channel layer of the fifth transistor and the channel layer of the sixth transistor.
In one embodiment, the second transistor group further includes a seventh transistor and an eighth transistor connected in parallel, the seventh transistor and the eighth transistor are distributed along the second direction, the first blue data line is electrically connected to a channel layer of the seventh transistor, the second blue data line is electrically connected to a channel layer of the eighth transistor, the second switching signal line is electrically connected to gates of the seventh transistor and the eighth transistor through a fourth gate signal data line, and the second drain trace is electrically connected to the channel layer of the seventh transistor and the channel layer of the eighth transistor.
In one embodiment, the third transistor group includes a ninth transistor, the third signal line group includes a green data line electrically connected to a channel layer of the ninth transistor and a third switching signal line electrically connected to a gate of the ninth transistor through a fifth gate signal data line, and the array substrate further includes a third drain wire electrically connected to the channel layer of the ninth transistor.
A display module comprises the array substrate.
The array substrate and the display module provided by the embodiment of the invention have the advantages that the array substrate is provided with the display area and the frame area, the display area is provided with the arc-shaped corner, the frame area is positioned outside the display area, the frame area is internally provided with a plurality of functional circuit units which are electrically connected with the display area, the functional circuit units are distributed along a first direction which is taken as the extension direction of the display area, any functional circuit unit comprises a plurality of transistors which are distributed on the same layer and along a second direction which is vertical to the first direction and a signal line group arranged among the transistor groups, and the signal lines in the signal line group are in point connection with the corresponding transistor groups. This scheme is through distributing the adjustment along the first direction with a plurality of transistor groups among the prior art and distributing for along the second direction perpendicular with the first direction, has reduced the space that functional circuit unit took up on the horizontal direction, and conventional arc display device's step department contains a plurality of repeated single functional circuit units, and a plurality of functional circuit units are synthesized the space of saving, can reduce the shared space of array substrate greatly, consequently realize narrow arc frame design.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention.
Fig. 2 is an enlarged schematic view a of an array substrate according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of a functional unit according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a functional unit according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention. Fig. 2 is an enlarged schematic view a of an array substrate according to an embodiment of the invention.
As shown in fig. 1 and 2, the array substrate includes: display area 1 and frame district 2, display area 1 has the arc corner, and frame district 2 sets up outside display area 1, is provided with a plurality of functional unit with display area 1 electricity is connected in frame district 2, and these a plurality of functional unit distribute along first direction 01, and wherein first direction 01 is the extending direction of display area 1. Any one of the functional circuit units 3 includes a plurality of transistor groups and a signal group provided between the plurality of transistor groups, wherein the plurality of transistor groups are on the same layer, and the plurality of transistor groups are distributed in the second direction 02, the second direction 02 being a direction perpendicular to the first direction 01. The signal lines in the signal line group are electrically connected with the corresponding transistor groups, and the signal lines are used for providing corresponding signals for the corresponding transistor groups. This scheme is through distributing a plurality of transistor groups among the prior art along first direction 01 and adjusting to distribute along the second direction 02 perpendicular with first direction 01, the space that functional circuit unit 3 took up on the horizontal direction has been reduced, conventional arc display device's step department contains a plurality of repeated functional circuit units 3, a plurality of functional circuit unit 3 synthesize the space of saving, the shared space of array substrate can be greatly reduced, consequently, realize narrow arc frame design. In one embodiment, the functional circuit unit 3 is a test circuit.
In an embodiment of the present invention, the number of the transistor groups is the same as the number of the colors of the sub-pixels in the display area 1. One transistor group drives one color sub-pixel. Preferably, the display region 1 has red, green and blue sub-pixels, and the transistor groups include a first transistor group 03, a second transistor group 04 and a third transistor group, wherein the first transistor group 03 may be a transistor group for driving a red sub-pixel, the second transistor group 04 may be a transistor group for driving a blue sub-pixel, and the third transistor group may be a transistor group for driving a green sub-pixel. The same color sub-pixels are driven by the transistor group, so that a plurality of transistors of the sub-pixels with the same color are arranged together, the space is reasonably utilized, and the problem that wiring is difficult to arrange due to the fact that the functional circuit unit 3 in the frame of the screen body and wiring of the functional circuit unit are limited by the space of the arc-shaped frame is solved.
It is understood that the first transistor group 03 can be a transistor group for driving a red sub-pixel, a transistor group for driving a green sub-pixel, and a transistor group for driving a blue sub-pixel; the second transistor group 04 may be a transistor group for driving the blue sub-pixel, a transistor group for driving the green sub-pixel, or a transistor group for driving the red sub-pixel; the second transistor group 04 may be a transistor group for driving a green sub-pixel, a transistor group for driving a red sub-pixel, or a transistor group for driving a blue sub-pixel, and what color sub-pixel is driven by the first transistor group 03, the second transistor group 04, and the third transistor group may be adjusted according to the actual situation.
In an embodiment of the present invention, signal line groups are disposed in gaps among the first transistor group 03, the second transistor group 04, and the third transistor group, where the signal line groups include signal data lines or switch lines for the first transistor group 03, the second transistor group 04, and the third transistor group, and the signal line groups are disposed among the first transistor group 03, the second transistor group 04, and the third transistor group, so that the arrangement is more compact, and the space utilization is more reasonable.
It is understood that the signal line group may include signal data lines or switch lines, and may also include other types of signal lines, and the specific function of the signal line group is not limited by the present invention.
Fig. 3 is a schematic structural diagram of a functional unit according to an embodiment of the present invention.
As shown in fig. 3, the third transistor group is close to the display region 1, the second transistor group 04 is far from the display region 1, and the first transistor group 03 is between the second transistor group 04 and the third transistor group 05 along the second direction 02. The signal line group includes a first signal line group 06, a second signal group 06, and a third signal line group 08, and the first signal line group 06, the second signal group, and the third signal line group 08 are arranged in parallel along the second direction 02, wherein the first signal line group 06 is disposed between the first transistor group 03 and the second transistor group 04, the third transistor group 05 is disposed between the first transistor group 03 and the third transistor group 05, and the second signal line group 07 is disposed on a side of the first transistor group 03 away from the third transistor group 05. The first signal line group 06 may include: a first red data line 061, a first switching signal line 062, and a second switching signal line 063; the second signal line group 07 includes a first blue data line 064 and a second blue data line 071; the third signal line group 08 includes a green data line 083, a third switching signal line 082 and a second red data line 081. Here, the green data line 083, the third switching signal line 082, the second red data line 081, the first red data line 061, the first switching signal line 062, the second switching signal line 063, the first blue data line 064, and the second blue data line 071 are sequentially arranged along the second direction 02. Through setting up red data line into two and including first red data line 061 and second red data line 081, blue data line sets up into two and includes first blue data line 064 and second blue data line 071, the length of red and blue data line along first direction 01 has been shortened, consequently, can shorten the width of functional circuit unit 3 along first direction 01, make functional circuit unit 3 reduce in the required space of first direction 01, functional circuit unit 3 and its line of having solved in the screen body frame receive the space restriction of arc frame, lead to the problem that the line was laid difficultly.
It is to be understood that the green data line 083, the third switching signal line 082, the second red data line 081, the first red data line 061, the first switching signal line 062, the second switching signal line 063, the first blue data line 064, and the second blue data line 071 are sequentially arranged along the second direction 02, or may be arranged in a predetermined order, and the arrangement order of the green data line 083, the third switching signal line 082, the second red data line 081, the first red data line 061, the first switching signal line 062, the second switching signal line 063, the first blue data line 064, and the second blue data line 071 may be adjusted according to actual requirements, the present invention does not limit the specific arrangement order of the green data line 083, the third switching signal line 082, the second red data line 081, the first red data line 061, the first switching signal line 062, the second switching signal line 063, the first blue data line 064, and the second blue data line 071.
Fig. 4 is a schematic structural diagram of a functional unit according to another embodiment of the present invention.
As shown in fig. 4, the first transistor group 03 may be adapted to the red sub-pixel, and the first transistor group 03 includes a first transistor 011 and a second transistor 012 connected in parallel, in which the first transistor 011 and the second transistor 012 are distributed in the second direction 02, and the first transistor 011 and the second transistor 012 share one drain and source. The first signal line group 06 includes a first red data line 061 and a second switching signal line 063, and the third signal line group 08 includes a second red data line 081. The first red data line 061 is electrically connected to a channel layer of the first transistor 011 and the second red data line 081 is electrically connected to a channel layer of the second transistor 012, where the first red data line 061 may be a source signal data line of the first transistor 011 and the second red data line 081 may be a source signal data line of the second transistor 012. The second switching signal line 063 is electrically connected to the gates of the first transistor 011 and the second transistor 012 through a second gate signal data line. The array substrate further includes a first drain trace 09, the first drain trace 09 is electrically connected to the channel layer of the first transistor 011 and the channel layer of the second transistor 012, wherein the first drain trace 09 is electrically connected to the drain of the first transistor 011 and the drain of the second transistor 012. Through setting up red data line into two and including first red data line 061 and second red data line 081, the length of red data line along first direction 01 has been shortened, consequently can shorten the width of functional circuit unit 3 along first direction 01, make functional circuit unit 3 reduce in the required space of first direction 01, functional circuit unit 3 and its line of having solved in the screen body frame receive the space restriction of arc frame, lead to the problem that the line was laid difficultly.
It is understood that the first red data line 061 and the second red data line 081 may be included, and a plurality of red data lines, such as a third red data line and a fourth red data line, may be further included, and the number of red data lines may be adjusted according to actual requirements, and the number of red data lines is not limited in the present invention.
In an embodiment of the invention, the first transistor group 03 further includes a third transistor 013 and a fourth transistor 014 connected in parallel, the third transistor 013 and the fourth transistor 014 are distributed along the second direction 02, the first signal line group 06 further includes a first switching signal line 062, the first red data line 061 is electrically connected to a channel layer of the third transistor 013, and the second red data line 081 is electrically connected to a channel layer of the fourth transistor 014, wherein the first red data line 061 may be a source signal data line of the third transistor 013, and the second red data line 081 may be a source signal data line of the fourth transistor 014. The first switching signal line 062 is electrically connected to gates of the third transistor 013 and the fourth transistor 014 through a second gate signal data line, and the array substrate further includes a second drain wire 11 electrically connected to a channel layer of the third transistor 013 and a channel layer of the fourth transistor 014, wherein the second drain wire 11 may be electrically connected to a drain of the third transistor 013 and a drain of the fourth transistor 014. Through setting up red data line into two and including first red data line 061 and second red data line 081, the length of red data line along first direction 01 has been shortened, consequently can shorten the width of functional circuit unit 3 along first direction 01, make functional circuit unit 3 reduce in the required space of first direction 01, functional circuit unit 3 and its line of having solved in the screen body frame receive the space restriction of arc frame, lead to the problem that the line was laid difficultly.
It is understood that the first transistor 011, the second transistor 012, the third transistor 013 and the fourth transistor 014 can be transistors emitting red light, which can include the first transistor 011, the second transistor 012, the third transistor 013 and the fourth transistor 014, and can further include more transistors emitting red light, the number of the transistors emitting red light can be adjusted according to actual requirements, and the specific number of the transistors emitting red light is not limited in the present invention.
In an embodiment of the present invention, the second transistor group 04 includes a fifth transistor 025 and a sixth transistor 026 connected in parallel, and the fifth transistor 025 and the sixth transistor 026 are distributed along the second direction 02. The first signal line group 06 includes a first blue data line 064, the second signal line group 07 includes a second blue data line 071, the first blue data line 064 is electrically connected to a channel layer of the fifth transistor 025, and the second blue data line 071 is electrically connected to a channel layer of the sixth transistor 026, wherein the first blue-red data line may be a source signal data line of the fifth transistor 025, and the second blue data line 071 may be a source signal data line of the sixth transistor 026. The first switching signal line 062 is electrically connected with gates of the fifth transistor 025 and the sixth transistor 026 through a third gate signal data line, and the first drain trace 09 is electrically connected with a channel layer of the fifth transistor 025 and a channel layer of the sixth transistor 026, wherein the first drain trace 09 may be electrically connected with a drain of the fifth transistor 025 and a drain of the sixth transistor 026. Through setting up blue data line into two and including first blue data line 064 and second blue data line 071, shortened blue data line along the length of first direction 01, consequently can shorten the width of functional circuit unit 3 along first direction 01, make functional circuit unit 3 reduce in the required space of first direction 01, solved functional circuit unit 3 in the screen body frame and walk the space restriction that receives the arc frame thereof, lead to walking the problem of laying the difficulty.
It is understood that the first blue data line 064 and the second blue data line 071 may be included, and a plurality of blue data lines, such as a third blue data line and a fourth blue data line, may be further included, and the number of blue data lines may be adjusted according to actual requirements, and the number of blue data lines is not limited in the present invention.
In an embodiment of the present invention, the second transistor group 04 further includes a seventh transistor 027 and an eighth transistor 028 connected in parallel, the seventh transistor 027 and the eighth transistor 028 are distributed along the second direction 02, the first blue data line 064 is electrically connected to a channel layer of the seventh transistor 027, and the second blue data line 071071 is electrically connected to a channel layer of the eighth transistor 028, wherein the first blue-red data line may be a source signal data line of the seventh transistor 027, and the second blue data line 071 may be a source signal data line of the eighth transistor 028. The second switching signal line 063 is electrically connected to the gates of the seventh transistor 027 and the eighth transistor 028 through a fourth gate signal data line, and the second drain trace 11 is electrically connected to the channel layer of the seventh transistor 027 and the channel layer of the eighth transistor 028, where the second drain trace 11 may be electrically connected to the drain of the seventh transistor 027 and the drain of the eighth transistor 028. Through setting up blue data line into two and including first blue data line 064 and second blue data line 071, shortened blue data line along the length of first direction 01, consequently can shorten the width of functional circuit unit 3 along first direction 01, make functional circuit unit 3 reduce in the required space of first direction 01, solved functional circuit unit 3 in the screen body frame and walk the space restriction that receives the arc frame thereof, lead to walking the problem of laying the difficulty.
It is understood that the fifth transistor 025, the sixth transistor 026, the seventh transistor 027, and the eighth transistor 028 can be blue light emitting transistors, which can include the first transistor 011, the second transistor 012, the third transistor 013, and the fourth transistor 014, and can further include more blue light emitting transistors, the number of blue light emitting transistors can be adjusted according to actual requirements, and the specific number of blue light emitting transistors is not limited in the present invention.
In an embodiment of the invention, the third transistor group 05 includes a ninth transistor 029, the third signal line group 08 includes a green data line 083 and a third switch signal line 082, the green data line 083 is electrically connected to a channel layer of the ninth transistor 029, where the green data line 083 may be a source signal data line of the ninth transistor 029, the third switch signal line 082 is electrically connected to a gate of the ninth transistor 029 through a fifth gate signal data line, the array substrate further includes a third drain trace 10 electrically connected to the channel layer of the ninth transistor 029, and the third drain trace 10 may be electrically connected to a drain of the ninth transistor 029.
In an embodiment of the present invention, compared with the prior art, the red data line and the blue data line are split into a plurality of parts, and the plurality of parts are electrically connected by a connection line, for example, the red data line is split into a first red data line 061 and a second red data line 081, the blue data line is split into a first blue data line 064 and a second blue data line 071, the first red data line 061 and the second red data line 081 are electrically connected, the first blue data line 064 and the second blue data line 071 are electrically connected, the first red data line 061 is simultaneously connected to the channel layer of the first transistor 011 and the channel layer of the second transistor 012, and the first transistor 011 and the second transistor 012 are connected in parallel, so that the aspect ratio of the first transistor 011 and the second transistor 012 connected in parallel is consistent with the aspect ratio of the transistor in the prior art, thereby ensuring a light emitting effect.
In an embodiment of the present invention, the maximum distance between the first drain trace 09 and the second drain trace 11 is 20-50 μm, and the maximum distance between the first drain trace 09 and the second drain trace 11 in the prior art is generally greater than 65 μm, so that the functional circuit unit 3 in this embodiment is shortened by at least 15 μm compared with the prior art, and thus the space occupied by the functional circuit unit 3 in the horizontal direction is reduced, the step of the conventional arc display device includes the repeated functional circuit unit 3, the saved spaces of the plurality of functional circuit units 3 are combined, the space occupied by the array substrate can be greatly reduced, and the problem that the critical space distance of the layout is reduced due to the overlarge space occupied by the functional circuit unit 3 in the horizontal direction, and thus the narrow arc frame cannot be realized is solved.
In an embodiment of the present invention, the display module includes the array substrate described in any of the above embodiments, the array substrate has a display area 1 and a frame area 2, wherein the display area 1 has an arc-shaped corner, the frame area 2 is located outside the display area 1, a plurality of functional unit circuits electrically connected to the display area 1 are disposed in the frame area 2, the plurality of functional unit circuits 3 are distributed along a first direction 01 which is an extending direction of the display area 1, any one of the functional unit circuits 3 includes a plurality of transistors which are disposed on the same layer and are distributed along a second direction 02 which is perpendicular to the first direction 01, and a signal line group disposed between the transistor groups, and a signal line in the signal line group is point-connected to a corresponding transistor group. This scheme is through distributing a plurality of transistor groups among the prior art along first direction 01 and adjusting to distribute along the second direction 02 perpendicular with first direction 01, the space that functional circuit unit 3 took up on the horizontal direction has been reduced, conventional arc display device's step department contains a plurality of repeated functional circuit units 3, a plurality of functional circuit unit 3 synthesize the space of saving, the shared space of array substrate can be greatly reduced, consequently, realize narrow arc frame design.
It can be understood that the display module can be a computer, a mobile phone or a vehicle-mounted electronic display device, and the specific type of the display device is not limited in the invention.
In an embodiment of the invention, the display module further includes a pixel layer, where the pixel layer includes at least one pixel repeating unit, and the pixel repeating unit includes two red sub-pixels, two green sub-pixels, and two blue sub-pixels, where the two red sub-pixels, the two green sub-pixels, and the two blue sub-pixels are arranged in a matrix of two rows and three columns, the two green sub-pixels are respectively located in a first row, a second column, a first row, a third column, and a second row, the two blue sub-pixels are respectively located in the first row, the third column, and the second row, the first column, and the second column. The first transistor 011 and the second transistor 012 connected in parallel drive the first red sub-pixel, when the second switch signal line 063 inputs signal, the gates of the first transistor 011 and the second transistor 012 are turned on, the signals of the first red data line 061 and the second red data line 081 are transmitted to the anode of the first red sub-pixel through the sources of the first transistor 011 and the second transistor 012 and the drains of the first transistor 011 and the second transistor 012, respectively, to drive the anode of the first red sub-pixel to emit light. The third transistor 013 and the fourth transistor 014 connected in parallel drive the second red subpixel, and when a signal is input to the first switching signal line 062, gates of the third transistor 013 and the fourth transistor 014 are turned on, and signals of the first red data line 061 and the second red data line 081 are transmitted to an anode of the second red subpixel through sources of the third transistor 013 and the fourth transistor 014 and drains of the third transistor 013 and the fourth transistor 014, respectively, to drive the anode of the second red subpixel to emit light. The fifth transistor 025 and the sixth transistor 026 connected in parallel drive the first blue subpixel, and when a signal is input to the first switching signal line 062, gates of the fifth transistor 025 and the sixth transistor 026 are turned on, and signals of the first blue data line 064 and the second blue data line 071 are transmitted to an anode of the first blue subpixel through sources of the fifth transistor 025 and the sixth transistor 026 and drains of the fifth transistor 025 and the sixth transistor 026, respectively, to drive the anode of the first blue subpixel to emit light. The seventh transistor 027 and the eighth transistor 028 connected in parallel drive the second blue sub-pixel, when a signal is input to the second switching signal line 063, gates of the seventh transistor 027 and the eighth transistor 028 are turned on, and signals of the first blue data line 064 and the second blue data line 071 are transmitted to an anode of the second blue sub-pixel through sources of the seventh transistor and the eighth transistor 028 and drains of the seventh transistor 027 and the eighth transistor 028, respectively, to drive the anode of the second blue sub-pixel to emit light. The ninth transistor 029 drives to simultaneously drive the first green sub-pixel and the second green sub-pixel, when a signal is input to the third switch signal line 082, the gate of the ninth transistor 029 is turned on, and a signal of the green data line 083 is transmitted to the anode of the first green sub-pixel and the anode of the second green sub-pixel through the source and the drain of the ninth transistor 029, so that the first green sub-pixel and the second green sub-pixel are driven to emit light.
It is to be understood that the arrangement of the pixel repeating units may be as described in the above embodiments, and the pixel repeating units may also be adjusted according to actual situations.
It is also understood that the array substrate can be used for performing unit tests, and the invention is not limited to the specific application of the array substrate.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and the like that are within the spirit and principle of the present invention are included in the present invention.
Claims (10)
1. An array substrate, comprising:
a display area (1) having an arc-shaped corner and a frame area (2) located outside the display area (1), the frame area being located at the arc-shaped corner, a plurality of functional circuit units (3) electrically connected to the display area (1) being provided in the frame area (2), the plurality of functional circuit units (3) being distributed along a first direction (01) being an extension direction of the display area (1),
any one of the functional circuit units (3) includes: the signal line group comprises a plurality of transistor groups which are distributed on the same layer along a second direction (02) perpendicular to the first direction (01), and signal line groups arranged among the transistor groups, wherein signal lines in the signal line groups are electrically connected with the corresponding transistor groups.
2. An array substrate according to claim 1, wherein the number of transistor groups is the same as the number of sub-pixel colors in the display area (1).
3. An array substrate according to claim 2, wherein the display area (1) has three color sub-pixels of red, green and blue,
the transistor group has a first transistor group (03) adapted to the red sub-pixel, a second transistor group (04) adapted to the blue sub-pixel and a third transistor group (05) adapted to the green sub-pixel,
the signal line group is arranged in a gap among the first transistor group (03), the second transistor group (04) and the third transistor group (05).
4. An array substrate according to claim 3, wherein along the second direction (02), the third transistor group (05) is close to the display area (1), the second transistor group (04) is far from the display area (1), the first transistor group (03) is between the second transistor group (04) and the third transistor group (05),
the signal line groups include a first signal line group (06) between a first transistor group (03) and a second transistor group (04), a third signal line group (08) between the first transistor group (03) and a third transistor group (05), and a second signal line group (07) on a side of the first transistor group (03) remote from the third transistor group (05).
5. An array substrate according to claim 4, characterized in that the first transistor group (03) comprises a first transistor (011) and a second transistor (012) connected in parallel, the first transistor (011) and the second transistor (012) being distributed along the second direction (02),
the first signal line group (06) includes a first red data line (061) and a second switching signal line (063), the third signal line group (08) includes a second red data line (081),
the first red data line (061) is electrically connected to a channel layer of the first transistor (011), the second red data line (081) is electrically connected to a channel layer of the second transistor (012), the second switching signal line (063) is electrically connected to gates of the first transistor (011) and the second transistor (012) through a second gate signal data line,
the array substrate further includes a first drain trace (09) electrically connected to the channel layer of the first transistor (011) and the channel layer of the second transistor (012).
6. An array substrate according to claim 5, wherein the first transistor group (03) further comprises: a third transistor (013) and a fourth transistor (014) connected in parallel, the third transistor (013) and the fourth transistor (014) being distributed along the second direction (02),
the first signal line group (06) further comprises a first switching signal line (062),
the first red data line (061) is electrically connected to a channel layer of the third transistor (013), the second red data line (081) is electrically connected to a channel layer of the fourth transistor (014), the first switching signal line (062) is electrically connected to gates of the third transistor (013) and the fourth transistor (014) through a second gate signal data line,
the array substrate further includes a second drain trace (11) electrically connected to the channel layer of the third transistor (013) and the channel layer of the fourth transistor (014).
7. An array substrate according to claim 6, wherein the second transistor group (04) comprises a fifth transistor (025) and a sixth transistor (026) connected in parallel, the fifth transistor (025) and the sixth transistor (026) being distributed along the second direction (02),
the first signal line group (06) includes a first blue data line (064), the second signal line group (07) includes a second blue data line (071),
the first blue data line (064) is electrically connected to a channel layer of the fifth transistor (025), the second blue data line (071) is electrically connected to a channel layer of the sixth transistor (026), the first switching signal line (062) is electrically connected to gates of the fifth transistor (025) and the sixth transistor (026) through a third gate signal data line,
the first drain trace (09) is electrically connected with a channel layer of the fifth transistor (025) and a channel layer of the sixth transistor (026).
8. An array substrate according to claim 7, wherein the second transistor group (04) further comprises a seventh transistor (027) and an eighth transistor (028) connected in parallel, the seventh transistor (027) and the eighth transistor (028) being distributed along the second direction (02),
the first blue data line (064) is electrically connected to a channel layer of the seventh transistor (027), the second blue data line (071) is electrically connected to a channel layer of the eighth transistor (028), the second switching signal line (063) is electrically connected to gates of the seventh transistor (027) and the eighth transistor (028) through a fourth gate signal data line,
the second drain trace (11) is electrically connected to a channel layer of the seventh transistor (027) and a channel layer of the eighth transistor (028).
9. An array substrate according to claim 4, wherein the third transistor group (05) comprises a ninth transistor (029),
the third signal line group (08) includes a green data line (083) and a third switching signal line (082),
the green data line (083) is electrically connected to a channel layer of the ninth transistor (029), the third switch signal line (082) is electrically connected to a gate of the ninth transistor (029) through a fifth gate signal data line,
the array substrate further comprises a third drain trace (10) electrically connected to the channel layer of the ninth transistor (029).
10. A display module comprising the array substrate of any one of claims 1-9.
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