CN109885154B - Low-power-consumption register with bypass channel - Google Patents

Low-power-consumption register with bypass channel Download PDF

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CN109885154B
CN109885154B CN201910152944.3A CN201910152944A CN109885154B CN 109885154 B CN109885154 B CN 109885154B CN 201910152944 A CN201910152944 A CN 201910152944A CN 109885154 B CN109885154 B CN 109885154B
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unit
pipe
output
bypass
buffer
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CN109885154A (en
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余宁梅
马文恒
许兰
黄自力
张文东
刘和娜
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Jiangxi Tianyi Semiconductor Co ltd
Shenzhen Wanzhida Technology Co ltd
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract

The invention discloses a low-power-consumption register with a bypass channel, which comprises a storage unit and a buffer output unit, wherein the storage unit is connected with the buffer output unit; the storage gating unit is used for controlling the opening and closing of the storage unit and the buffer output unit; the buffer gating unit is used for controlling the on and off of the bypass unit and the output isolation unit. The storage gating unit and the buffer gating unit adjust the working modes of the circuit at different frequencies, so that the register or bypass of input data is controlled, and the power consumption is reduced.

Description

Low-power-consumption register with bypass channel
Technical Field
The invention belongs to the technical field of registers, and relates to a low-power-consumption register with a bypass channel.
Background
With the continuous development of semiconductor technology, the performance requirements for chips are increasing. To achieve higher performance, chip designers use a variety of different performance enhancement methods in conducting circuit design. In order to increase the operating frequency of the chip, registers need to be inserted into the logic circuits so that the same logic circuit can be executed in a pipelined manner. In this way, logic can be multiplexed, greatly improving peak performance of the chip. At the same time, advances in technology have led to an increasing amount of resources on the chip. As on-chip device density increases, power consumption problems become more and more severe, and become a bottleneck limiting further development of processors. In the chip design process, the designer is more concerned about how to achieve higher peak performance, so a large number of pipeline registers are inserted at different positions of the circuit, so that the circuit can work at the highest operating frequency, thereby achieving the best performance, but at the same time, a large amount of redundant energy consumption is introduced.
A common approach to reduce power consumption is to employ Dynamic Voltage Frequency Scaling (DVFS) techniques: when the working load is higher, the power supply voltage and the working frequency are improved; when the workload is low, the supply voltage and the operating frequency are reduced. Because the power consumption of the chip is mainly composed of dynamic power consumption and static power consumption, the static power consumption and the dynamic power consumption can be greatly reduced after the voltage and the operating frequency are reduced by adopting the DVFS technology. Since the circuit is designed to achieve higher performance at the beginning of the design, the pipeline registers inserted in the original design to boost the frequency are completely disabled after the operating frequency is reduced. Although signals do not pass through the registers directly to the final output terminal and timing violations and logic errors are not generated, the registers become redundant logic of the chip completely when the circuit operates at low load and low frequency. Because the register device has a complex structure and a large number of transistors, the probability of signal inversion is higher than that of conventional logic, and therefore, the register consumes more energy than a logic circuit. Considering the existence of a large number of pipeline registers in the circuit, when the chip works in a low-load state, the pipeline registers can generate great energy waste, and the operation efficiency of the chip is reduced.
Disclosure of Invention
The invention aims to provide a low-power-consumption register with a bypass channel, which solves the problem that the register in the prior art needs to consume great energy.
The low-power-consumption register with the bypass channel comprises a storage unit and a buffer output unit, wherein the storage unit is connected with the buffer output unit, a storage gating unit is connected with the buffer output unit and the storage unit, the buffer output unit is connected with the bypass unit and an output isolation unit, and the buffer gating unit is connected with the bypass unit and the output isolation unit; the storage gating unit is used for controlling the opening and closing of the storage unit and the buffer output unit; the buffer gating unit is used for controlling the on and off of the bypass unit and the output isolation unit.
The present invention is also characterized in that,
the buffer gate control unit is a PMOS tube, the source electrode of the PMOS tube is connected with VDD, the drain electrode of the PMOS tube is connected with the source ends of all the PMOS tubes of the storage unit and the buffer output unit, and the grid electrode is a gate control enabling signal PG1; when PG1 is 0, the PMOS tube is started to supply power to the storage unit and the buffer output unit; and when PG1 is 1, stopping supplying power to the storage unit and the buffer output unit.
The storage gate control unit is a PMOS tube, the source electrode of the PMOS tube is connected with VDD, the drain electrode of the PMOS tube is connected with the source ends of all the PMOS tubes of the storage unit and the buffer output unit, and the grid electrode is a gate control enabling signal PG2; when PG2 is 0, the bypass unit and the output isolation port are opened, and when PG2 is 1, the buffer output unit, the bypass unit and the output isolation unit are closed.
The transistor-level structure diagram bypass unit of the bypass unit comprises 4 NMOS pipes of an N1 pipe, an N2 pipe, an N3 pipe and an N4 pipe, and 4 PMOS pipes of a P1 pipe, a P2 pipe, a P3 pipe and a P4 pipe; the bypass unit is provided with three signals, namely a data input signal D, a bypass enabling signal BP and an output signal Q; the source electrode of the P1 pipe is connected with the high level VDD, the grid electrode of the P1 pipe and the grid electrode of the N1 pipe are controlled by BP signals, the drain electrode of the P1 pipe is connected with the drain electrode of the N1 pipe to control the grid electrode of the P2 pipe, the source electrode of the P2 pipe is connected with the VDD, the drain electrode of the P3 pipe is connected with the drain electrode of the N2 pipe, the grid electrode of the P3 pipe is connected with the grid electrode of the N2 pipe to serve as a D port of data input, the source electrode of the N2 pipe is connected with the source electrode of the N3 pipe, the grid electrode of the N3 pipe is controlled by BP signals, the source electrode of the N3 pipe is grounded, the grid electrode of the P4 pipe is connected with the drain electrode of the P3 pipe, the source electrode of the P3 pipe is connected with the VDD, the drain electrode of the N4 pipe is grounded.
The output isolation unit consists of an N1 pipe, an N2 pipe, 2 NMOS pipes, a P1 pipe and 2 PMOS pipes; the output isolation unit has an intermediate output signal
Figure BDA0001982046920000031
Isolation enable signal Z, output signal Q1 three signals; the source electrode of the P1 tube is connected with the VDD, the drain electrode is connected with the source electrode of the P2 tube, the drain electrode of the P2 tube is connected with the drain electrodes of the N1 and N2 tubes, the source electrodes of the N1 tube and the N2 tube are grounded, and the grid electrodes of the P1 tube and the N2 tube are connected by->
Figure BDA0001982046920000032
Control, the grid electrode of the P2 tube is connected with the grid electrode of the N1 tubeControlled by signal Z.
The invention has the beneficial effects that the storage gating unit and the buffer gating unit adjust the working modes of the circuit at different frequencies, thereby controlling the register or bypass of input data and reducing the power consumption.
Drawings
FIG. 1 is a schematic diagram of a low power register with bypass channels according to the present invention;
FIG. 2 is a schematic diagram of a low power register bypass unit with bypass channels according to the present invention;
FIG. 3 is a circuit diagram of a transistor level of a low power register bypass cell with bypass channel according to the present invention;
FIG. 4 is a schematic diagram of a low power register isolation output unit with bypass according to the present invention;
FIG. 5 is a circuit diagram of a transistor stage of a low power register isolation output unit with bypass channels according to the present invention.
Detailed Description
The invention will be described in detail below with reference to the drawings and the detailed description.
The invention discloses a low-power-consumption register with a bypass channel, which is shown in figure 1. The device comprises a storage unit and a buffer output unit, wherein the storage unit is connected with the buffer output unit, a storage gating unit is connected with the buffer output unit and the storage unit, the buffer output unit is connected with a bypass unit and an output isolation unit, and the buffer gating unit is connected with the bypass unit and the output isolation unit; the storage gating unit is used for controlling the opening and closing of the storage unit and the buffer output unit, and the storage gating unit is switched through an input signal PG1; the buffer gating unit is used for controlling the on and off of the bypass unit and the output isolation unit, and the buffer gating unit is switched through an input signal PG2. The bypass unit is directly connected with the input signal D and the output node Q of the buffer output unit to form a bypass channel. The input node of the isolated output unit is the intermediate signal of the register
Figure BDA0001982046920000041
Output ofThe signal is Q1.
The storage gate control unit is actually a PMOS transistor, the source electrode of the PMOS transistor is connected to VDD, the drain electrode is connected to the source ends of all PMOS transistors of the storage unit and the buffer output unit, and the gate electrode is a gate control enable signal PG1. When PG1 is 0, the PMOS tube is started to supply power to the storage unit and the buffer output unit, so that the two units are started; when PG1 is 1, power supply to the memory cell and the buffer output cell is stopped, so both cells are in an off state.
The buffer gate control unit is a PMOS tube, the source electrode of the PMOS tube is connected with VDD, the drain electrode of the PMOS tube is connected with the source ends of all the PMOS tubes of the storage unit and the buffer output unit, and the grid electrode is a gate control enabling signal PG2. When the gate control enabling signal PG2 of the buffer gate control unit is 0, the bypass unit and the output isolation port are opened, and when PG2 is 1, the buffer output unit, the bypass unit and the output isolation unit are closed.
As shown in fig. 2, the bypass unit has 2 input signals including a data input signal D and a bypass enable signal BP, and an output signal Q. The output signal Q is connected to the output node Q of the buffered output unit. The truth table of the bypass unit is shown in table 1, and when the bypass enable signal BP is invalid (i.e., BP is 0), the output signal Q of the bypass unit is in an unstable state; when the bypass enable signal BP is valid (i.e., BP is 1), the output signal Q of the bypass unit outputs the value of the current input signal D.
Truth table for bypass cell
Figure BDA0001982046920000051
TABLE 1
As shown in fig. 3, the transistor-level structure diagram bypass unit of the bypass unit is composed of 4 NMOS transistors of N1, N2, N3, N4, and 4 PMOS transistors of P1, P2, P3, P4. The source electrode of the P1 pipe is connected with the high level VDD, the grid electrode of the P1 pipe and the grid electrode of the N1 pipe are controlled by BP signals, the drain electrode of the P1 pipe is connected with the drain electrode of the N1 pipe to control the grid electrode of the P2 pipe, the source electrode of the P2 pipe is connected with the VDD, the source electrode of the drain electrode of the P3 pipe is connected with the drain electrode of the N2 pipe, the grid electrode of the P3 pipe is connected with the grid electrode of the N2 pipe to serve as a D port of data input, the source electrode of the N2 pipe is connected with the source electrode of the N3 pipe, the grid electrode of the N3 pipe is controlled by BP signals, the source electrode of the N3 pipe is grounded, the grid electrode of the P4 pipe is connected with the drain electrode of the P3 pipe, the drain electrode of the P3 pipe is connected with the drain electrode of the N4 pipe, and the source electrode of the N4 pipe is grounded.
When the bypass enable signal BP is 0, the P2 and N3 pipes are turned off, and the output Q is in an unstable state. When the bypass enable signal BP is 1, the P2 pipe and the N3 pipe are conducted, and if the input signal D is 1 at this time, the N2 pipe is conducted, the node
Figure BDA0001982046920000067
Grounded VSS, node->
Figure BDA0001982046920000068
0, node
Figure BDA0001982046920000069
Outputting a signal Q through an inverter, wherein the node Q outputs 1; if the input signal D is 0, the P3 pipe is conducted, and the node +.>
Figure BDA00019820469200000610
To VDD, node->
Figure BDA0001982046920000066
1, node->
Figure BDA0001982046920000065
The signal Q is output through the inverter, and the node Q outputs 0. It can thus be seen that the circuit configuration shown in fig. 3 can perform the circuit functions required by the bypass unit.
As shown in FIG. 4, the output isolation unit has 2 input signals, the intermediate output signal of the register
Figure BDA00019820469200000611
And an isolation enable signal Z;1 output signal Q1. The truth table of the output isolation unit is shown in Table 2, when the enable signal Z is active (i.e., Z is 1), no matter the node +.>
Figure BDA0001982046920000064
Why the output signal Q1 of the output isolation unit is 0. When the off signal Z is inactive (i.e., Z is 0), the output signal Q1 of the output isolation unit outputs the value of Q.
Truth table for output isolation unit
Figure BDA0001982046920000061
TABLE 2
As shown in FIG. 5, the output isolation unit is composed of an N1 pipe, an N2 pipe, 2 NMOS pipes, a P1 pipe and 2 PMOS pipes. The source electrode of the P1 tube is connected with the VDD, the drain electrode is connected with the source electrode of the P2 tube, the drain electrode of the P2 tube is connected with the drain electrodes of the N1 and N2 tubes, the source electrodes of the N1 and N2 tubes are grounded, and the grid electrodes of the P1 and N2 tubes are connected with each other
Figure BDA0001982046920000062
The gate connections of P2 and N1 are controlled by signal Z.
When the isolation enable signal Z is 1, the N1 pipe is turned on, the P2 pipe is turned off, and the node Q1 is connected to VSS, no matter
Figure BDA0001982046920000063
What value is input, node Q1 outputs 0. When the turn-off signal Z is 0, the N1 pipe is turned off and the P2 pipe is turned on, if +.>
Figure BDA0001982046920000071
When the signal is 1 (i.e. Q is 0), the N2 pipe is conducted, the node Q1 is connected to VSS, the node Q1 outputs 0, and at the moment, the signal Q1 and the Q value are the same; if at this time->
Figure BDA0001982046920000072
When the value is 0 (i.e. Q is 1), the P1 pipe is conducted, the node Q1 is connected to VDD, the node Q1 outputs 1, and the value of the Q1 output is still the same as the value of Q. It can be seen that the circuit structure shown in fig. 5 can perform the circuit functions required for isolating the output unit.
When the circuit is in a high-frequency mode, the pipeline register works normally, and at the moment, the gating signal PG1 and the gating signal PG2 are both 0, and the storage unit, the buffer output unit, the bypass unit and the output isolation unit are all in normal working states. Selecting an appropriate output port as an output according to the designed circuit, and selecting an output Q of the buffer output unit as the output port if the designed circuit does not generate a logic error after the bypass unit is turned on; if the designed circuit generates a logic error after the bypass unit is turned on, the isolated output port Q1 should be selected as the output port. When the register works normally, the enable signal Z of the isolated output port should be set to 0, so that the isolated output port Q1 outputs the same value as Q, and logic errors are prevented from being generated. When the circuit is switched to a low-frequency mode, a pipeline register is not required to work, in order to reduce power consumption, the gating signal PG1 is made to be 1, the gating unit 1 controls the storage unit and the buffer output unit to be turned off, the gating signal PG2 is made to be 0, and the gating unit 2 controls the bypass unit and the isolation output port to be turned on. But it may also be an option to not turn off the memory cells and the buffer output cells if the circuit designer wants to keep the values of the previous registers. In this case, the bypass enable signal BP is asserted (i.e., 1), the bypass unit directly transfers the input data D to the output node Q, and the bypass unit controls the output signal Q. If the bypass unit is not turned on after the memory unit and the buffer output port are turned off (i.e., PG1 is 1 and bp is 0), this control is not allowed in the present design, which results in an unstable output signal Q. When the bypass unit works in the low frequency mode, in order to prevent logic loop errors, the enable signal Z of the isolation output unit is enabled, and the Q1 output is directly set to 0. In addition, in the case where the entire register unit does not operate, in order to reduce power consumption, the entire register may be turned off by the gate unit 1 and the gate unit 2 (i.e., PG1 and PG2 are both 1).

Claims (3)

1. The low-power-consumption register with the bypass channel is characterized by comprising a storage unit and a buffer output unit, wherein the storage unit is connected with the buffer output unit, the storage gating unit is connected with the buffer output unit and the storage unit, the buffer output unit is connected with the bypass unit and the output isolation unit, and the buffer gating unit is connected with the bypass unit and the output isolation unit;
the storage gating unit is used for controlling the on and off of the storage unit and the buffer output unit;
the buffer gating unit is used for controlling the bypass unit and the output isolation unit to be turned on and off;
the buffer gate control unit is a PMOS tube, the source electrode of the PMOS tube is connected with VDD, the drain electrode of the PMOS tube is connected with the source ends of all the PMOS tubes of the storage unit and the buffer output unit, and the grid electrode is a gate control enabling signal PG1; when PG1 is 0, the PMOS tube is started to supply power to the storage unit and the buffer output unit; when PG1 is 1, stopping supplying power to the storage unit and the buffer output unit;
the storage gate control unit is a PMOS tube, the source electrode of the PMOS tube is connected with VDD, the drain electrode of the PMOS tube is connected with the source ends of all the PMOS tubes of the storage unit and the buffer output unit, and the grid electrode is a gate control enabling signal PG2; when PG2 is 0, the bypass unit and the output isolation port are opened, and when PG2 is 1, the buffer output unit, the bypass unit and the output isolation unit are closed;
when the circuit is in a high-frequency mode, the pipeline register normally works, and at the moment, the gate control signal PG1 and the gate control signal PG2 are both 0, and the storage unit, the buffer output unit, the bypass unit and the output isolation unit are in normal working states; when the circuit is switched to a low-frequency mode, a pipeline register is not required to work, in order to reduce power consumption, the gating signal PG1 is made to be 1, the storage gating unit controls the storage unit and the buffer output unit to be turned off, the gating signal PG2 is made to be 0, and the buffer gating unit controls the bypass unit and the isolation output port to be turned on.
2. The low power register with bypass channel according to claim 1, wherein the transistor level structure diagram bypass unit of the bypass unit is composed of 4 NMOS tubes of N1 tube, N2 tube, N3 tube, N4 tube and 4 PMOS tubes of P1 tube, P2 tube, P3 tube, P4 tube; the bypass unit is provided with three signals, namely a data input signal D, a bypass enabling signal BP and an output signal Q; the source electrode of the P1 pipe is connected with a high level VDD, the grid electrode of the P1 pipe and the grid electrode of the N1 pipe are controlled by BP signals, the drain electrode of the P1 pipe is connected with the drain electrode of the N1 pipe to control the grid electrode of the P2 pipe, the source electrode of the P2 pipe is connected with the source electrode of the P3 pipe, the drain electrode of the P3 pipe is connected with the drain electrode of the N2 pipe, the grid electrode of the P3 pipe is connected with the grid electrode of the N2 pipe to serve as a D port for data input, the source electrode of the N2 pipe is connected with the source electrode of the N3 pipe, the grid electrode of the N3 pipe is controlled by BP signals, the source electrode of the N3 pipe is grounded, the grid electrode of the P4 pipe and the grid electrode of the N4 pipe are connected to the drain electrode of the P3 pipe, the source electrode of the P3 pipe is connected with the drain electrode of the N4 pipe, and the source electrode of the N4 pipe is grounded.
3. The low power consumption register with bypass channel as claimed in claim 1, wherein the output isolation unit is composed of N1 pipe, N2 pipe, 2 NMOS pipes and 2 PMOS pipes of P1 pipe and P2 pipe; the output isolation unit has an intermediate output signal
Figure QLYQS_1
Three signals of an isolation enabling signal Z and an output signal Q1; the source electrode of the P1 pipe is connected with the VDD, the drain electrode is connected with the source electrode of the P2 pipe, the drain electrode of the P2 pipe is connected with the drain electrodes of the N1 pipe and the N2 pipe, the source electrodes of the N1 pipe and the N2 pipe are grounded, and the grid electrodes of the P1 pipe and the N2 pipe are connected by->
Figure QLYQS_2
And the grid connection of the P2 pipe and the N1 pipe is controlled by a signal Z.
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