CN109873642A - A method of for correcting the gain mismatch of segmented analog-digital converter - Google Patents
A method of for correcting the gain mismatch of segmented analog-digital converter Download PDFInfo
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- CN109873642A CN109873642A CN201910056699.6A CN201910056699A CN109873642A CN 109873642 A CN109873642 A CN 109873642A CN 201910056699 A CN201910056699 A CN 201910056699A CN 109873642 A CN109873642 A CN 109873642A
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Abstract
The present invention proposes a kind of correcting algorithm that expense is minimum aiming at the problem that being difficult to and detecting segmented ADC gain mismatch.This algorithm only need to the output codons to ADC carry out some seldom logical operations and can accurately obtain the specific direction of gain mismatch, without complicated digital processing unit, only can a volume be the minimum area and power consumption of increase.This algorithm is a kind of Background calibration algorithm, can track the variation of PVT always, ensure that ADC can be worked normally under various application environments.
Description
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical fields, and in particular to a kind of for correcting segmented analog-digital converter
The algorithm of gain mismatch.
Background technique
The number that the collected analog signal of front-end circuit is converted into for digital processor processes by analog-digital converter (ADC)
Word signal is the bridge for connecting simulated world and digital world.In many electrical systems and instrument, ADC is pass therein
Key module.High-speed ADC even more is difficult to design and demand is huge.
Segmentation structure is a kind of structure of common high-speed ADC.The ADC of this structure is lower with a very fast still precision
" thick ADC " conversion it is high-order as a result, remaining result is then converted by a precision higher but slow " smart ADC ".It is " thick
ADC " can use Flash ADC or high speed Approach by inchmeal (SAR) ADC." smart ADC " is usually to use high-precision comparator
ADC.Conversion in order to guarantee ADC is correct, it is necessary to eliminate the error between two ADC.These errors include different comparators
Offset voltage error and two ADC gains mismatch.The mismatch when error of offset voltage is manufactured from device, compares
The comparison threshold value of device is not identical, it will lead to input conversion in each near threshold voltage and mistake occurs, certainly using imbalance
The comparator and addition redundant digit of calibration can effectively improve this problem.
Gain mismatch refers to that two ADC are obtained when quantifying same signal the result is that deviation by a certain percentage.Believe in input
When number maximum, biggish gain mismatch, which will lead to signal transmitting error, the code word of ADC between two ADC, to restrain.?
Redundant digit is added before first of " smart quantizer ", and the structure of segmented can be allow to tolerate a certain amount of gain mismatch.
This can make the ADC manufactured largely work normally, but still some ADC because manufacture when deviation it is larger, redundant digit
So large gain mismatch cannot be corrected.And ADC in practical applications, the variation of environment temperature and supply voltage can all change
The gain of two ADC, making mismatch is more than tolerable range.The fairly simple existing method for improving gain mismatch generally can be sacrificial
Domestic animal others performance improves design difficulty.The area for increasing ADC per device can effectively reduce gain mismatch with manufacture work
Skill, the fluctuation of environment temperature and supply voltage variation (PVT).But which increase the manufacturing cost of ADC and power consumptions, while also reducing
The sample rate of ADC.Step sampling can eliminate gain mismatch substantially under using in the SAR ADC using CDAC.But
This scheme can greatly increase design difficulty only to using the SAR ADC of CDAC effective.The gain for changing ADC is very simple
It is single, but to detect gain mismatch and judge which rank of ADC bigger error or it is less than normal be highly difficult.
Summary of the invention
The present invention proposes a kind of correction that expense is minimum calculation aiming at the problem that being difficult to and detecting segmented ADC gain mismatch
Method.This algorithm only need to the output codons to ADC carry out some seldom logical operations and can accurately obtain gain mismatch
Specific direction, without complicated digital processing unit, only meeting volume is to increase minimum area and power consumption.This algorithm is a kind of backstage school
Normal operation method can track always the variation of PVT, ensure that ADC can be worked normally under various application environments.
The technical scheme is that a kind of algorithm for detecting segmented ADC gain mismatch.This algorithm to ADC each time
Output codons calculated, obtain the offset direction of gain mismatch.But show that gain is lost only according to certain testing result
If being just adjusted greatly very much, entire algorithm will be not convergent.Because the metastable state in comparator can false triggering gain inspection
The condition of survey, it is necessary to exclude metastable influence.
A method of for correcting the gain mismatch of segmented analog-digital converter, this method comprises:
Step 1: if the output codons of " smart ADC " are all " 0 " or " 1 " and " thick ADC " different with the output codons of " smart ADC "
It is all " 0 " or " 1 ", there may be the gain mismatchs that needs correct by ADC at this time.If the output codons of " smart ADC " are not all " 0 "
Or " 1 ", or the output codons of " smart ADC " and " thick ADC " are all " 0 " or " 1 " simultaneously, there is no needing school under both of these case
Positive gain mismatch.
Step 2: if it is determined that then comparing first bit word and " essence of " thick ADC " there may be gain mismatch in step 1
Whether the first bit word of ADC " is identical.If identical, the gain of " smart ADC " is excessive；If it is different, then the increasing of " smart ADC "
Benefit is too small.The direction of gain mismatch is obtained with this.
Step 3: the false triggering detected in order to prevent needs the result count to detection.When detecting a gain mismatch
Afterwards, ADC conversion end starts counting each time.After counting reaches certain number, if not detecting the identical of certain number
The error in direction or the error for detecting opposite direction illustrate that detection is false triggering；, whereas if detecting certain number
The same direction error, then determine the direction of gain mismatch.
Step 4: after obtaining correct gain mismatch direction from step 3, gain mismatch detection module adjusts output gain
Signal returns to " smart ADC ", adjusts its gain.
The invention has the benefit that
Gain mismatch correcting algorithm in the present invention is realized simple and accurate.All logical operations and technology can pass through rule
The lesser Digital Logical Circuits of mould is realized, without complicated digital signal processor, therefore realizes that simply area occupied is small, function
It consumes small.In addition algorithm eliminates input overflowing and the metastable false triggering of comparator, can accurately detect the side of gain mismatch
To then being calibrated.
Detailed description of the invention
Fig. 1 is the schematic diagram of the segmented ADC with gain mismatch correction module；
Fig. 2 is the schematic diagram determined whether there are gain mismatch；
Fig. 3 is the schematic diagram for determining gain mismatch direction；
Fig. 4 is the flow chart of gain mismatch correcting algorithm；
Specific embodiment
A specific embodiment of the invention is described with reference to the accompanying drawing:
Fig. 1 depicts the segmented ADC with gain mismatch correction module.N " smart ADC " needs N+1 quantization.Preceding M secondary amounts
Change by M " thick ADC " quantization, and by corresponding D1-DMIt is transferred to " smart ADC ".Remaining DM+1-DN+1Quantified by " smart ADC ".
M+1 are redundant digit, it can allow segmented ADC to tolerate a degree of gain mismatch.The output D of ADC1-DN+1It is entered
It is detected to gain mismatch detection module.If detecting gain mismatch, gain mismatch detection module will control " smart ADC " and adjust
Whole gain reduces gain mismatch.
Fig. 2 is the schematic diagram determined whether there are gain mismatch.The exemplary diagram in left side is shown: when the result of " smart ADC "
DM+1-DN+1When being not all 1 or 0, illustrate that gain mismatch is smaller；Intermediate exemplary diagram is shown: as the result D of ADC1-DN+1It is all 1
Or when 0, input overflowing can not determine whether there is gain mismatch；The exemplary diagram on the right is shown: when input overflowing is not present, such as
The result D of fruit " smart ADC "M+1-DN+1It is all 1 or 0, there may be biggish gain mismatchs by ADC.
Fig. 3 is the schematic diagram for determining gain mismatch direction.The exemplary diagram on the left side is shown: if D1=DM+1, illustrate " essence
The gain of the ratio of gains " thick ADC " of ADC " is less than normal, also needs more great talent according to the gain of the gain quantization of " thick ADC ", " smart ADC "
Energy result is within gain mismatch tolerance；If D1≠DM+1, according to identical analysis, it is known that the ratio of gains of " smart ADC "
The gain of " thick ADC " is bigger than normal.
Fig. 4 is the flow chart of gain mismatch correcting algorithm.In conjunction with the description of Fig. 2 and Fig. 3, first determine whether to deposit according to fig. 2
In gain mismatch, i.e. DM+1-DN+1Whether it is all 0 or is all 1, if not mismatch gain is then not detected；If it is judge
D1-DN+1Whether it is all 0 or is all 1, if it is input overflowing, is not detected gain mismatch；It is if not judgement is then continued
No D1=DM+1, if it is " smart ADC " gain is less than normal；It is bigger than normal if not then " smart ADC " gain.
After detecting the presence of gain mismatch as shown above, the gain of ADC can not be directly adjusted, because comparator is metastable
State is possible to this detection of meeting false triggering.Metastable interference in order to prevent needs the result detected to gain mismatch to count
Number.After detecting gain mismatch for the first time, whenever ADC export a result just counts once and to gain mismatch result into
Row counts.There are following three kinds of situations:
1. gain mismatch reaches Y times after ADC exports X result, then determine to be implicitly present in gain mismatch.
2. gain mismatch detects the mismatch in another direction, then illustrates to examine when ADC output is counted without reaching X times
It is wrong to survey result, needs to count again with nearest testing result.
3. gain mismatch does not reach Y times when ADC output, which counts, to be reached X times, then illustrate that testing result may be accidentally to touch
Hair, needs to restart when detecting gain mismatch next time to count.
The occurrence of X and Y is determined by the metastable state rate and ADC input signal of ADC.The more high then X needs of metastable state rate are smaller,
ADC input signal occur big signal probability it is larger when, Y is bigger.The metastable state rate of general ADC is 10-5-10-10.If X=64, Y
=4, then metastable state causes the probability of detection of mismatch false triggering to be 6.35 × 10-15.And metastable state not necessarily will lead to false triggering
Gain mismatch, therefore this probability can be lower in actual conditions.
Illustrate the present invention below with several examples, it is assumed that there are one 10 segmented ADC, its " thick ADC " is 5
Position, " smart ADC " are 6 positions (1+5).There is following example about detection gain mismatch:
It is " 01011111011 ", D that 1.ADC, which exports result,6-D11It is not all 1, gain mismatch is not present.
It is " 11111111111 " that 2.ADC, which exports result, although D6-D11It is all 1, not within gain mismatch tolerance,
But all code words are also all 1, illustrate at this time to may be input overflowing, might not there is gain mismatch.
It is " 00000111111 ", D that 3.ADC, which exports result,6-D11It is all 1, and all code words are not all 1, so in the presence of
Gain mismatch.Again because of D1=0, D6=1, so detecting that " smart ADC " gain is bigger than normal.
It is " 0101000000 ", D that 4.ADC, which exports result,6-D11It is all 0, and all code words are not all 0, increased so existing
Beneficial mismatch.Again because of D1=0, D6=0, so detecting that " smart ADC " gain is less than normal.
There is following example about metastable state false triggering:
Started counting after " smart ADC " is less than normal 1. detecting, 64 times count in, detect 1 time " smart ADC " it is bigger than normal, then from current
Beginning bigger than normal counts again.
Started counting after " smart ADC " is less than normal 2. detecting, 64 times count in, only detect 2 times " smart ADC " it is less than normal, then
This detects be likely to be false triggering caused by metastable state twice.Restart to count after detecting false triggering next time.
Started counting after " smart ADC " is less than normal 3. detecting, 64 times count in, detect 6 times " smart ADC " it is less than normal, then recognize
It is less than normal for " smart ADC " gain, increase " gain of smart ADC " after 64 countings.
From the above description it is recognised that the digital circuit of detection gain mismatch is small.
Claims (1)
1. a kind of method for correcting the gain mismatch of segmented analog-digital converter, this feature are,
Step 1: if the output codons of " smart ADC " are all " 0 " or " 1 " and " thick ADC " different with the output codons of " smart ADC "
It is all " 0 " or " 1 ", there may be the gain mismatchs that needs correct by ADC at this time；If the output codons of " smart ADC " are not all " 0 "
Or " 1 ", or the output codons of " smart ADC " and " thick ADC " are all " 0 " or " 1 " simultaneously, there is no needing school under both of these case
Positive gain mismatch；
Step 2: if it is determined that then comparing first bit word and " smart ADC " of " thick ADC " there may be gain mismatch in step 1
The first bit word it is whether identical；If identical, the gain of " smart ADC " is excessive；If it is different, then the gain of " smart ADC "
It is small；The direction of gain mismatch is obtained with this；
Step 3: the false triggering detected in order to prevent needs the result count to detection, after detecting a gain mismatch, often
One time ADC conversion end starts counting；After counting reaches certain number, if do not detect the same direction of certain number
Error or the error for detecting opposite direction illustrate that detection is false triggering；, whereas if detecting the identical of certain number
The error in direction then determines the direction of gain mismatch；
Step 4: after obtaining correct gain mismatch direction from step 3, gain mismatch detection module is by output gain adjustment signal
Back to " smart ADC ", its gain is adjusted.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112994692A (en) * | 2021-02-26 | 2021-06-18 | 电子科技大学 | Metastable state detection-based interstage gain and capacitance mismatch calibration method for Synthetic Aperture Radar (SAR) ADC |
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2019
- 2019-01-22 CN CN201910056699.6A patent/CN109873642A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112994692A (en) * | 2021-02-26 | 2021-06-18 | 电子科技大学 | Metastable state detection-based interstage gain and capacitance mismatch calibration method for Synthetic Aperture Radar (SAR) ADC |
| CN112994692B (en) * | 2021-02-26 | 2022-03-29 | 电子科技大学 | Metastable state detection-based interstage gain and capacitance mismatch calibration method for Synthetic Aperture Radar (SAR) ADC |
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