CN109873397A - A kind of method, apparatus and system of chip electrostatic protection - Google Patents
A kind of method, apparatus and system of chip electrostatic protection Download PDFInfo
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- CN109873397A CN109873397A CN201910096324.2A CN201910096324A CN109873397A CN 109873397 A CN109873397 A CN 109873397A CN 201910096324 A CN201910096324 A CN 201910096324A CN 109873397 A CN109873397 A CN 109873397A
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Abstract
The present invention provides the method, apparatus and system of a kind of protection of chip electrostatic, by the way that single trigger circuit is arranged in the chip, and monitor the working condition of chip, detecting chip by ESD impact, after causing the working condition of chip exception occur, working condition abnormal signal is sent to the signal processing apparatus that chip exterior is arranged in.Signal processing apparatus can be according to the working condition abnormal signal received, interrupt trigger signal is sent to the single trigger circuit in the portion in the chip that is arranged, so that single trigger circuit can control the dump preset time of chip, eliminate the ESD problem of the electronic component in chip, avoid further damage of the latch-up to chip, it is ensured that the safety and reliability of chip.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of the method, apparatus and system of chip electrostatic protection.
Background technique
Chip is referred to as integrated circuit, with the continuous development of integrated circuit fabrication process, chip package density and
Integrated level is higher and higher, and chip size is smaller and smaller, and the interference between circuit module is also more and more obvious, and generates latch-up
Probability is higher and higher.Electrostatic is a kind of invisible destructive power, can be had an impact to electronic component, ESD (Electro-
Static discharge, Electro-static Driven Comb) and relevant voltage transient can all cause latch-up.ESD problem will lead to chip
Electric current constantly increases, and will finally burn chip.Latch-up refers to CMOS (Complementary Metal Oxide
Semiconductor, complementary metal oxide semiconductor refer to a kind of technology or use of manufacture large scale integrated chip
The chip that this technology manufactures) the intrinsic parasitic bipolar transistor of device is triggered conducting, deposits between power supply and ground
A low impedance path, high current access.The presence of latch-up will lead to circuit and can not work normally, or even burn circuit.
In the prior art, it prevents latch-up measure to be generally divided into technique, domain, circuit etc., in technique level, leads to
It crosses and changes the doping concentration of metal in substrate, reduce BJT (Bipolar Junction Transistor, bipolar junction transistor)
Gain to prevent the generation of latch-up.In terms of domain, weakened by addition guard ring (protection ring) etc. parasitic
Coupling between transistor.In terms of circuit, design power clamp circuitry measures guarantee PN junction is reverse-biased etc..Although taking
Face measure can avoid the generation of latch-up as far as possible, but due to various limitations in practical manufacturing process, latch effect
It can not should be eliminated completely.
The electrostatic problem in chip circuit how is eliminated, solves the problems, such as latch-up, it is ensured that the stability and peace of chip
The technical issues of Quan Xing is this field urgent need to resolve.
Summary of the invention
The embodiment of the invention provides the method, apparatus and system of a kind of protection of chip electrostatic, eliminate the electricity in chip
The ESD problem of subcomponent avoids further damage of the latch-up to chip.
On the one hand, a kind of method of chip electrostatic protection is provided, single trigger circuit is set in the chip, it is described
Method, comprising:
Monitor the working condition of chip；
When the working condition for detecting the chip occurs abnormal, working condition is sent to signal processing apparatus and is believed extremely
Number, so that the signal processing apparatus sends interrupt trigger signal to the single trigger circuit；
Using the single trigger circuit according to the interrupt trigger signal, when controlling the power supply of the chip and disconnecting default
Between.
In one embodiment, the method also includes:
When detecting that the working condition of the chip occurs abnormal, controls the chip and resetted.
In one embodiment, the method also includes:
After the preset time, the single trigger circuit restores stable state, controls the power supply conducting of the chip.
On the other hand, this specification embodiment provides a kind of device of chip electrostatic protection, and single is arranged in the chip
Trigger circuit, described device include:
Working state monitoring module, for monitoring the working condition of chip；
Abnormal signal sending module, for when the working condition for detecting the chip occurs abnormal, to signal processing
Device sends working condition abnormal signal, so that the signal processing apparatus sends down trigger to the single trigger circuit
Signal；
Dump module, for, according to the interrupt trigger signal, controlling the core using the single trigger circuit
The power supply of piece disconnects preset time.
In one embodiment, described device further include:
Reseting module controls the chip and is resetted for detecting that it is abnormal that the working condition of the chip occurs.
In one embodiment, described device further include:
Module is replied in work, is used for after the preset time, the single trigger circuit recovery stable state, described in control
The power supply of chip is connected.
Another aspect, provides a kind of chip electrostatic protection terminal device, including processor and is used for storage processor
The memory of executable instruction, the processor realize the chip electrostatic protection side in above-described embodiment when executing described instruction
Method.
Another aspect provides a kind of computer readable storage medium, is stored thereon with computer instruction, described instruction quilt
The chip electrostatic means of defence in above-described embodiment is realized when execution.
Another aspect provides a kind of system of chip electrostatic protection, comprising: chip, signal processing apparatus, setting are in core
Single pulse circuit and register in piece, the signal processing apparatus are connect with the single pulse circuit, the register；
The single pulse circuit is connect with the power input of the chip, and the single pulse circuit connection has power supply
Control switch, the single pulse circuit are used to control the power control switch and are turned on or off the power supply of the chip；
The register is used to monitor the working condition of the chip, and in the chip operation abnormal state, to institute
It states signal processing apparatus and sends working condition abnormal signal；
The signal processing apparatus is used to receive the working condition abnormal signal that the register is sent, and according to the work
Make abnormal state signal and sends interrupt trigger signal to the single trigger circuit.
In one embodiment, pressure unit is provided in the single pulse circuit.
The method, apparatus and system of a kind of chip electrostatic protection are provided in embodiments of the present invention, by the chip
Single trigger circuit is set, and monitors the working condition of chip, is detecting that chip by ESD impact, leads to the work of chip
After exception occurs in state, working condition abnormal signal is sent to the signal processing apparatus that chip exterior is arranged in.Signal processing device
Down trigger can be sent to the single trigger circuit in the portion in the chip that is arranged according to the working condition abnormal signal received by setting
Signal eliminates the electronic component in chip so that single trigger circuit can control the dump preset time of chip
ESD problem, avoid further damage of the latch-up to chip, it is ensured that the safety and reliability of chip.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, not
Constitute limitation of the invention.In the accompanying drawings:
Fig. 1 is the flow diagram of the method for chip electrostatic protection in this specification one embodiment；
Fig. 2 is the flow diagram of the method for chip electrostatic protection in another embodiment of this specification；
Fig. 3 is the time diagram that single trigger circuit controls in this specification embodiment；
Fig. 4 is the structural schematic diagram of the device of chip electrostatic protection in this specification one embodiment；
Fig. 5 is the structural schematic diagram of the system of chip electrostatic protection in this specification one embodiment.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, right below with reference to embodiment and attached drawing
The present invention is described in further details.Here, exemplary embodiment and its explanation of the invention is used to explain the present invention, but simultaneously
It is not as a limitation of the invention.
It is using certain technique, the elements such as transistor, resistance, capacitor and inductance needed for a circuit and wiring are mutual
With together, be produced on a fritter or a few fritter semiconductor wafers or dielectric substrate, be then encapsulated in a shell, become tool
There is the microstructure of required circuit function, is properly termed as chip or integrated circuit.Wherein, all elements have formed one in structure
A entirety, electronic component develop towards microminaturization, low-power consumption, intelligent direction.
Electro-static Driven Comb (ESD, Electro-Static discharge), electrostatic may occur for the electronic device in chip
Usual transient voltage is very high (> several kilovolts), thus this damage be it is crushing and permanent, it is direct to be likely to result in chip
It burns.The volume of chip is smaller and smaller, and the interference between circuit module is also more and more obvious, under the impact of ESD, power supply or electricity
Biggish fluctuation may occur for pressure, and chip induction region causes the circuit in chip can not be normal it is possible that latch-up
Work, or even burn circuit.
Some embodiments provide a kind of methods that chip electrostatic protects for this specification, by the work shape for monitoring chip
State is detecting chip by ESD impact, after causing the working condition of chip exception occur, to the letter that chip exterior is arranged in
Number processing unit sends working condition abnormal signal.Signal processing apparatus can according to the working condition abnormal signal received,
Interrupt trigger signal is sent to the single trigger circuit in the portion in the chip that is arranged, so that single trigger circuit can control chip
Dump preset time, eliminate the ESD of the electronic component in chip, avoid latch-up to the further damage of chip
It is bad.
Specifically, Fig. 1 is the flow diagram of the method for chip electrostatic protection in this specification one embodiment, such as Fig. 1
Shown, the method for the chip electrostatic protection provided in this specification one embodiment may comprise steps of:
Step 102, the working condition for monitoring chip.
In specific implementation process, when interference of the chip by external environment, such as: ESD impact, when chip is rushed by ESD
When hitting, the power supply or internal signal voltage of chip can generate bigger fluctuation, can pass through the power supply or voltage of monitoring chip
Fluctuation situation, i.e. whether registers state value deviates, to monitor the working condition of chip.Power supply, inside when chip
Signal voltage is in normal range (NR), and all register values can then indicate that chip is in and work normally shape in normal condition
State, if the power supply of chip or internal signal voltage are in unusual fluctuations range, there is exception, then can indicate in certain register values
Chip is in abnormal operation.In this specification one embodiment, the working condition of chip can pass through signal condition mark
Position Flag is indicated, and when chip is in normal operating conditions, can be set 0 for signal condition flag bit Flag, be worked as chip
Working condition when being in abnormal operation, 1 can be set by the signal condition flag bit Flag of chip.Certainly, according to
Other working state signals can be set also to characterize the working condition of chip in actual needs, and this specification embodiment is not made to have
Body limits.
It should be noted that the variation of chip working condition can be because external environment interference is led in this specification embodiment
The power supply or voltage of cause generate bigger fluctuation, wherein the interference of external environment is not limited to can also be by ESD impact
Others interference, this specification embodiment are not especially limited.The method provided in this specification embodiment can be used in core
Piece is in the interference by external environment, and while generating latch-up protects the safety of chip, and chip is avoided to burn.
Step 104, when the working condition for detecting the chip occurs abnormal, send work shape to signal processing apparatus
State abnormal signal, so that the signal processing apparatus sends interrupt trigger signal to the single trigger circuit.
In the specific implementation process, in this specification embodiment, single trigger circuit can be set in the chip i.e.
One-shot circuit, single trigger circuit can be made of logic gates, and usually there are two working conditions for one-shot circuit:
Stable state and temporary stable state.When normal work, one-shot circuit is typically in stable state, after receiving trigger signal, one-shot
Circuit can enter temporary stable state, then return to stable state after a certain period of time.Single trigger circuit can be understood as monostable trigger electricity
Road specifically can be derivative-type single-shot trigger circuit, integral form single-shot trigger circuit or integrated single-shot trigger circuit, tool
Body can be selected according to actual needs, and this specification embodiment is not especially limited.
In this specification embodiment, can also specifically may be used in chip exterior setting signal processing unit, signal processing apparatus
To be central processing unit or other can receive, handle and send the device of instruction, this specification embodiment is not especially limited.
In this specification embodiment, when the working condition for detecting chip occurs abnormal, work can be sent to signal processing apparatus
Abnormal state signal, such as: the signal condition flag bit Flag signal of chip can be sent to signal processing apparatus.Signal processing
After device receives the working condition abnormal signal of chip, interrupt trigger signal can be sent to single trigger circuit.Interrupt touching
It signals that the trigger signal of input single trigger circuit can be characterized, so that single trigger circuit enters temporary lower state.
Such as: detecting that chip is likely to occur larger fluctuation, chip interior by ESD impact, power supply or signal voltage
Register value deviates predetermined value, judges chip operation abnormal state at this time., working state signal Flag can be set to 1, and will
Signal condition flag bit Flag=1 is sent to signal processing apparatus.It, can after signal processing apparatus receives the signal of Flag=1
To judge chip by ESD impact, Xiang Danci trigger circuit sends interrupt trigger signal.
Step 106, using the single trigger circuit according to the interrupt trigger signal, the power supply for controlling the chip is disconnected
Open preset time.
In the specific implementation process, single trigger circuit can be logic control and delay circuit, single trigger circuit
After receiving interrupt trigger signal, temporary stable state can be entered, the power supply of chip is cut off, so that chip breaks within a preset time
Electricity, to eliminate ESD problem.Specifically, the power control switch of single trigger circuit and chip can be connected, when single triggers
After circuit receives interrupt trigger signal, control power control switch disconnects preset time, is realized using single trigger circuit
When chip is by ESD impact, preset time is powered off, chip caused by latch-up is avoided and burns.
It should be noted that time, that is, preset time the value for being disconnected the power supply of chip by single trigger circuit,
It can be realized according to actual needs by the design of single trigger circuit, this specification embodiment is not especially limited.
On the basis of the above embodiments, in some embodiments of this specification, after the preset lime, single trigger circuit
Restore stable state, can control the power supply conducting of chip, so that chip is resumed work.
On the basis of the above embodiments, in some embodiments of this specification, detecting chip by ESD impact, work
Make state and exception occur, when sending working condition abnormal signal to signal processing apparatus, can control chip and resetted.Chip
The initialization that can be understood as chip is resetted, so that chip reopens work.After exception occurs in chip operation state, in time
Chip reset is carried out, one-shot circuitry cuts chip power is recycled, it can be to avoid repeatedly by the abnormal operation of chip
Signal is sent to signal processing apparatus, reduces the process of signal processing.
The method for the chip electrostatic protection that this specification embodiment provides, by the way that single trigger circuit is arranged in the chip,
And the working condition of chip is monitored, and detecting chip by ESD impact, after causing the working condition of chip exception occur, to
The signal processing apparatus that chip exterior is arranged in sends working condition abnormal signal.Signal processing apparatus can be according to receiving
Working condition abnormal signal sends interrupt trigger signal to the single trigger circuit in the portion in the chip that is arranged, so that single touches
Power Generation Road can control the dump preset time of chip, eliminates the ESD problem of the electronic component in chip, avoids door bolt
Lock further damage of the effect to chip, it is ensured that the safety and reliability of chip.
Fig. 2 is the flow diagram of the method for chip electrostatic protection in another embodiment of this specification, as shown in Fig. 2,
The control method of chip electrostatic protection may include following procedure in this specification embodiment:
After chip powers on, the working condition of chip is IDEL (free time) mode, and working condition flag bit Flag is set to state
1, Flag=1 can indicate that chip is in abnormal operation.Signal processing apparatus receives working condition abnormal signal and to core
Piece is resetted, and chip enters working condition after initialization, and working condition flag bit Flag is set to state 0.Monitor the work of chip
Make state, judge whether ESD (i.e. Electro-static Driven Comb) impact leads to chip operation abnormal state, when ESD impact causes chip to incude
Region generates latch-up, and chip can not work normally, and the working condition of the register in chip changes at this time, resets work
Making state flag bit Flag state is 1.Register is very important a kind of storage unit in integrated circuit, usually by trigger
Composition judges that chip is abnormal and issues working condition abnormal signal to signal processing apparatus, which makes core
Piece resets.Signal processing apparatus can send interrupt trigger signal to one-shot circuit, and one-shot circuit receives interruption
After trigger signal, can of short duration disconnection power supply, avoid further damage of the latch-up to chip.Chip restores normal work later
Operation mode, signal condition flag bit Flag are set to 0.
Fig. 3 is the time diagram that single trigger circuit controls in this specification embodiment, and the first row can indicate in Fig. 3
The timing diagram of interrupt trigger signal, the second row indicate the timing diagram of single trigger circuit.As shown in figure 3, interrupt trigger signal is
Gao Shi, the register value in all chips will be set to initial value, and chip is completed to reset.There is no direct for one-shot circuit at this time
Into high level, the switch for controlling power supply is not disconnected, but is triggered when interrupt trigger signal is failing edge, is passed through at this time
Of short duration turn-off time disconnects the power supply of chip and eliminates latch-up with this.
The method for the chip electrostatic protection that this specification embodiment provides, can only need a switching tube and some controls
Logic unit circuit is realized and eliminates chip ESD problem, can not only save circuit area, but also can be to avoid using other ESD
Eliminate the introduced new ESD problem of circuit.
Various embodiments are described in a progressive manner for the above method in this specification, identical between each embodiment
Similar part may refer to each other, and each embodiment focuses on the differences from other embodiments.Correlation
Place illustrates referring to the part of embodiment of the method.
Based on the method that chip electrostatic described above protects, this specification one or more embodiment also provides a kind of core
The square law device of piece electrostatic protection.The device may include the system (packet for having used this specification embodiment the method
Include distributed system), software (application), module, component, server, client etc. and combine the necessary device for implementing hardware.
Device such as the following examples institute based on same innovation thinking, in one or more embodiments of this specification embodiment offer
It states.Since the implementation that device solves the problems, such as is similar to method, the implementation of the specific device of this specification embodiment can
With referring to the implementation of preceding method, overlaps will not be repeated.Used below, term " unit " or " module " can be real
The combination of the software and/or hardware of existing predetermined function.Although device described in following embodiment is preferably realized with software,
But the realization of the combination of hardware or software and hardware is also that may and be contemplated.
Specifically, Fig. 4 is the structural schematic diagram of the device of chip electrostatic protection in this specification one embodiment, this explanation
The device of chip electrostatic protection in book embodiment can be the register being arranged in the chip or the dress that can be realized its function
It sets, this specification embodiment is not especially limited.As shown in figure 4, register in the chip is arranged in this specification embodiment
Or the device of other chip electrostatic protection may include: working state monitoring module 41, abnormal signal sending module 42, power supply
Cut off module 43, in which:
Working state monitoring module 41 can be used for monitoring the working condition of chip；
Abnormal signal sending module 42 can be used for when the working condition for detecting the chip occurs abnormal, Xiang Xin
Number processing unit sends working condition abnormal signal, so that during the signal processing apparatus sends to the single trigger circuit
Disconnected trigger signal；
Dump module 43 can be used for using the single trigger circuit according to the interrupt trigger signal, control
The power supply of the chip disconnects preset time.
The device for the chip electrostatic protection that this specification embodiment provides, by the way that single trigger circuit is arranged in the chip,
And the working condition of chip is monitored, and detecting chip by ESD impact, after causing the working condition of chip exception occur, to
The signal processing apparatus that chip exterior is arranged in sends working condition abnormal signal.Signal processing apparatus can be according to receiving
Working condition abnormal signal sends interrupt trigger signal to the single trigger circuit in the portion in the chip that is arranged, so that single touches
Power Generation Road can control the dump preset time of chip, eliminates the ESD problem of the electronic component in chip, avoids door bolt
Lock further damage of the effect to chip, it is ensured that the safety and reliability of chip.
On the basis of the above embodiments, in some embodiments of this specification, described device can also include:
Reseting module controls the chip and is resetted for detecting that it is abnormal that the working condition of the chip occurs.
The device for the chip electrostatic protection that this specification embodiment provides eliminates in chip after the preset lime
The ESD problem of electronic component avoids further damage of the latch-up to chip, the power supply conducting of chip is controlled, so that core
Piece is resumed work.
On the basis of the above embodiments, in some embodiments of this specification, described device further include:
Module is replied in work, is used for after the preset time, the single trigger circuit recovery stable state, described in control
The power supply of chip is connected.
The device for the chip electrostatic protection that this specification embodiment provides, after exception occurs in chip operation state, in time
Chip reset is carried out, one-shot circuitry cuts chip power is recycled, it can be to avoid repeatedly by the abnormal operation of chip
Signal is sent to signal processing apparatus, reduces the process of signal processing.
Embodiment of the method provided by this specification embodiment can mobile terminal, terminal, server or
It is executed in similar arithmetic unit.
It should be noted that device described above can also include other embodiment party according to the description of embodiment of the method
Formula.Concrete implementation mode is referred to the description of related method embodiment, does not repeat one by one herein.
This specification embodiment also provides a kind of chip electrostatic protection terminal device terminal device, comprising: at least one
Device and the memory for storage processor executable instruction are managed, the processor realizes above-mentioned implementation when executing described instruction
The method of the chip electrostatic protection of example, such as:
Monitor the working condition of chip；
When the working condition for detecting the chip occurs abnormal, working condition is sent to signal processing apparatus and is believed extremely
Number, so that the signal processing apparatus sends interrupt trigger signal to the single trigger circuit；
Using the single trigger circuit according to the interrupt trigger signal, when controlling the power supply of the chip and disconnecting default
Between.
It should be noted that terminal device described above can also include other implement according to the description of embodiment of the method
Mode.Concrete implementation mode is referred to the description of related method embodiment, does not repeat one by one herein.
On the basis of the above embodiments, a kind of computer-readable storage can also be provided in this specification one embodiment
Medium is stored thereon with computer instruction, and described instruction is performed the method for realizing chip electrostatic protection in above-described embodiment,
Such as:
Monitor the working condition of chip；
When the working condition for detecting the chip occurs abnormal, working condition is sent to signal processing apparatus and is believed extremely
Number, so that the signal processing apparatus sends interrupt trigger signal to the single trigger circuit；
Using the single trigger circuit according to the interrupt trigger signal, when controlling the power supply of the chip and disconnecting default
Between.
The storage medium may include the physical unit for storing information, usually by after information digitalization again with benefit
The media of the modes such as electricity consumption, magnetic or optics are stored.It may include: that letter is stored in the way of electric energy that the storage medium, which has,
The device of breath such as, various memory, such as RAM, ROM；The device of information is stored in the way of magnetic energy such as, hard disk, floppy disk, magnetic
Band, core memory, magnetic bubble memory, USB flash disk；Using optical mode storage information device such as, CD or DVD.Certainly, there are also it
Readable storage medium storing program for executing of his mode, such as quantum memory, graphene memory etc..
It should be noted that computer readable storage medium described above can also include according to the description of embodiment of the method
Other embodiments.Concrete implementation mode is referred to the description of related method embodiment, does not repeat one by one herein.
Fig. 5 is the structural schematic diagram of the system of chip electrostatic protection in this specification one embodiment, as shown in figure 5, this
A kind of system of chip electrostatic protection is additionally provided in some embodiments of specification, may include:
Chip 01, signal processing apparatus 02, the single pulse circuit 03 and register 04 of setting in the chip, the signal
Processing unit 02 is connect with the single pulse circuit 03, the register 04, can specifically be communicated to connect, with receiving register
04 signal sent, and signal etc. is sent to single pulse circuit 03.
In Fig. 5, left side A can indicate the partial enlargement diagram of intermediate part A, and left side B can indicate that chip generates door bolt
When locking effect, the circuit connecting relation schematic diagram of chip, i.e. the circuit connection situation of the centre Fig. 5 part B.In figure, Rw can be with table
Show be Nwell (N well layer can mainly be used to do substrate and isolation) dead resistance, RS can indicate it is Substrate (base
Bottom) resistance, T1 can indicate NPN type BJT (Bipolar Junction Transistor, bipolar junction transistor), and T2 can be with
Indicate that positive-negative-positive BJT, Vss can indicate ground potential.
As shown in figure 5, single pulse circuit 03 can be arranged inside chip 01.In Fig. 5, Vddio, Vdd can be indicated
Power supply, wherein Vddio can indicate the power supply of chip exterior, can be used for being powered for single pulse circuit 03, when
After power control switch S1 conducting, Vddio can power for chip internal circuits, i.e. Vdd voltage.S1 can indicate power supply control
Switch, single pulse circuit 03 can control the power input in chip, and specific connection type can be with reference to shown in Fig. 5.Single
Impulse circuit 03 is connect with power control switch S1, be can control power control switch S1 and is turned on or off the electricity of the chip
Source.
Portion in the chip is arranged in register 04, can be used for monitoring the working condition of the chip, when ESD impact leads to core
Piece induction region generates latch-up, and chip can not work normally, and registers state changes at this time, resets work shape
State position Flag state is 1.In the chip operation abnormal state, register 04 can be sent to the signal processing apparatus 02
Working condition abnormal signal.As shown in figure 5, working condition marker signal, that is, Flag signal of chip can be sent to signal
Processing unit 02.
Signal processing apparatus 02 can be used for receiving the working condition abnormal signal that the register 04 is sent, and according to institute
It states working condition abnormal signal and sends interrupt trigger signal to the single trigger circuit 03, single trigger circuit 03 can connect
After receiving interrupt trigger signal, control power control switch S1 cutting chip power supply, and at the appointed time after, control power supply lead
It is logical, the state so that chip is resumed work.
In some embodiments of this specification, single pulse circuit can also be provided with pressure unit, pressure unit can be with
For reducing the supply voltage of single pulse circuit, prevent single pulse circuit from generating latch-up.Wherein pressure unit can be with
It is the circuit element that can reduce the supply voltage of single pulse circuit, as shown in figure 5, in some embodiments of this specification, drop
Pressure unit can be resistance R1, according to actual needs can also be using other circuit elements as pressure unit, or increase
The quantity etc. of resistance R1 reduces the supply voltage of single pulse circuit to increase the resistance of single pulse circuit, and this specification is real
Example is applied to be not especially limited.
This specification embodiment by the way that single trigger circuit is arranged in the chip, and monitors the working condition of chip, is examining
Chip is measured by ESD impact, after causing the working condition of chip exception occur, to the signal processing device that chip exterior is arranged in
It sets and sends working condition abnormal signal.Signal processing apparatus can exist according to the working condition abnormal signal received to setting
The single trigger circuit of chip interior sends interrupt trigger signal, so that the power supply that single trigger circuit can control chip is cut
Disconnected preset time.A switching tube and some control logic units are only needed, can not only save circuit area, but also can keep away
Exempt to eliminate the introduced new ESD problem of circuit using other ESD, eliminates the ESD problem of the electronic component in chip, avoid
Further damage of the latch-up to chip, it is ensured that the safety and reliability of chip.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for hardware+
For program class embodiment, since it is substantially similar to the method embodiment, so being described relatively simple, related place is referring to side
The part of method embodiment illustrates.
It is above-mentioned that this specification specific embodiment is described.Other embodiments are in the scope of the appended claims
It is interior.In some cases, the movement recorded in detail in the claims or step can be come according to the sequence being different from embodiment
It executes and desired result still may be implemented.In addition, process depicted in the drawing not necessarily require show it is specific suitable
Sequence or consecutive order are just able to achieve desired result.In some embodiments, multitasking and parallel processing be also can
With or may be advantageous.
Although this application provides the method operating procedure as described in embodiment or flow chart, based on conventional or noninvasive
The labour for the property made may include more or less operating procedure.The step of enumerating in embodiment sequence is only numerous steps
One of execution sequence mode, does not represent and unique executes sequence.It, can when device or client production in practice executes
To execute or parallel execute (such as at parallel processor or multithreading according to embodiment or method shown in the drawings sequence
The environment of reason).
System, device, module or the unit that above-described embodiment illustrates can specifically realize by computer chip or entity,
Or it is realized by the product with certain function.It is a kind of typically to realize that equipment is computer.Specifically, computer for example may be used
Think personal computer, laptop computer, vehicle-mounted human-computer interaction device, cellular phone, camera phone, smart phone, individual
Digital assistants, media player, navigation equipment, electronic mail equipment, game console, tablet computer, wearable device or
The combination of any equipment in these equipment of person.
Although this specification embodiment provides the method operating procedure as described in embodiment or flow chart, based on conventional
It may include either more or less operating procedure without creative means.The step of being enumerated in embodiment sequence be only
One of numerous step execution sequence mode does not represent and unique executes sequence.Device or end product in practice is held
When row, can be executed according to embodiment or method shown in the drawings sequence or it is parallel execute (such as parallel processor or
The environment of multiple threads, even distributed data processing environment).The terms "include", "comprise" or its any other change
Body is intended to non-exclusive inclusion, so that process, method, product or equipment including a series of elements are not only wrapped
Those elements are included, but also including other elements that are not explicitly listed, or further includes for this process, method, product
Or the element that equipment is intrinsic.In the absence of more restrictions, being not precluded is including process, the side of the element
There is also other identical or equivalent elements in method, product or equipment.
For convenience of description, it is divided into various modules when description apparatus above with function to describe respectively.Certainly, implementing this
The function of each module can be realized in the same or multiple software and or hardware when specification embodiment, it can also be by reality
Show the module of same function by the combination realization etc. of multiple submodule or subelement.Installation practice described above is only
Schematically, for example, the division of the unit, only a kind of logical function partition, can there is other draw in actual implementation
The mode of dividing, such as multiple units or components can be combined or can be integrated into another system, or some features can be ignored,
Or it does not execute.Another point, shown or discussed mutual coupling, direct-coupling or communication connection can be by one
The indirect coupling or communication connection of a little interfaces, device or unit can be electrical property, mechanical or other forms.
It is also known in the art that other than realizing controller in a manner of pure computer readable program code, it is complete
Entirely can by by method and step carry out programming in logic come so that controller with logic gate, switch, specific integrated circuit, programmable
Logic controller realizes identical function with the form for being embedded in microcontroller etc..Therefore this controller is considered one kind
Hardware component, and the structure that the device for realizing various functions that its inside includes can also be considered as in hardware component.Or
Person even, can will be considered as realizing the device of various functions either the software module of implementation method can be hardware again
Structure in component.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
In a typical configuration, calculating equipment includes one or more processors (CPU), input/output interface, net
Network interface and memory.
Memory may include the non-volatile memory in computer-readable medium, random access memory (RAM) and/or
The forms such as Nonvolatile memory, such as read-only memory (ROM) or flash memory (flash RAM).Memory is computer-readable medium
Example.
Computer-readable medium includes permanent and non-permanent, removable and non-removable media can be by any method
Or technology come realize information store.Information can be computer readable instructions, data structure, the module of program or other data.
The example of the storage medium of computer includes, but are not limited to phase change memory (PRAM), static random access memory (SRAM), moves
State random access memory (DRAM), other kinds of random access memory (RAM), read-only memory (ROM), electric erasable
Programmable read only memory (EEPROM), flash memory or other memory techniques, read-only disc read only memory (CD-ROM) (CD-ROM),
Digital versatile disc (DVD) or other optical storage, magnetic cassettes, tape magnetic disk storage or other magnetic storage devices
Or any other non-transmission medium, can be used for storage can be accessed by a computing device information.As defined in this article, it calculates
Machine readable medium does not include temporary computer readable media (transitory media), such as the data-signal and carrier wave of modulation.
It will be understood by those skilled in the art that the embodiment of this specification can provide as the production of method, system or computer program
Product.Therefore, in terms of this specification embodiment can be used complete hardware embodiment, complete software embodiment or combine software and hardware
Embodiment form.Moreover, it wherein includes computer available programs that this specification embodiment, which can be used in one or more,
Implement in the computer-usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) of code
The form of computer program product.
This specification embodiment can describe in the general context of computer-executable instructions executed by a computer,
Such as program module.Generally, program module includes routines performing specific tasks or implementing specific abstract data types, journey
Sequence, object, component, data structure etc..This specification embodiment can also be practiced in a distributed computing environment, in these points
Cloth calculates in environment, by executing task by the connected remote processing devices of communication network.In distributed computing ring
In border, program module can be located in the local and remote computer storage media including storage equipment.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for system reality
For applying example, since it is substantially similar to the method embodiment, so being described relatively simple, related place is referring to embodiment of the method
Part explanation.In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ",
The description of " specific example " or " some examples " etc. means specific features described in conjunction with this embodiment or example, structure, material
Or feature is contained at least one embodiment or example of this specification embodiment.In the present specification, to above-mentioned term
Schematic representation be necessarily directed to identical embodiment or example.Moreover, description specific features, structure, material or
Person's feature may be combined in any suitable manner in any one or more of the embodiments or examples.In addition, in not conflicting feelings
Under condition, those skilled in the art by different embodiments or examples described in this specification and different embodiment or can show
The feature of example is combined.
The foregoing is merely the embodiments of this specification embodiment, are not limited to this specification embodiment.It is right
For those skilled in the art, this specification embodiment can have various modifications and variations.It is all in this specification embodiment
Any modification, equivalent replacement, improvement and so within spirit and principle, the right that should be included in this specification embodiment are wanted
Within the scope of asking.
Claims (10)
1. a kind of method of chip electrostatic protection, which is characterized in that single trigger circuit, the method, packet are arranged in the chip
It includes:
Monitor the working condition of chip；
When the working condition for detecting the chip occurs abnormal, working condition abnormal signal is sent to signal processing apparatus,
So that the signal processing apparatus sends interrupt trigger signal to the single trigger circuit；
Using the single trigger circuit according to the interrupt trigger signal, the power supply for controlling the chip disconnects preset time.
2. the method according to claim 1, wherein the method also includes:
When detecting that the working condition of the chip occurs abnormal, controls the chip and resetted.
3. the method according to claim 1, wherein the method also includes:
After the preset time, the single trigger circuit restores stable state, controls the power supply conducting of the chip.
4. a kind of device of chip electrostatic protection, which is characterized in that single trigger circuit, described device packet are arranged in the chip
It includes:
Working state monitoring module, for monitoring the working condition of chip；
Abnormal signal sending module, for when the working condition for detecting the chip occurs abnormal, to signal processing apparatus
Working condition abnormal signal is sent, so that the signal processing apparatus sends down trigger letter to the single trigger circuit
Number；
Dump module, for, according to the interrupt trigger signal, controlling the chip using the single trigger circuit
Power supply disconnects preset time.
5. device according to claim 4, which is characterized in that described device further include:
Reseting module controls the chip and is resetted for detecting that it is abnormal that the working condition of the chip occurs.
6. device according to claim 4, which is characterized in that described device further include:
Module is replied in work, for after the preset time, the single trigger circuit recovery stable state to control the chip
Power supply conducting.
7. a kind of chip electrostatic protects terminal device, which is characterized in that can be performed including processor and for storage processor
The step of memory of instruction, the processor realizes any one of claim 1-3 the method when executing described instruction.
8. a kind of computer readable storage medium, which is characterized in that be stored thereon with computer instruction, described instruction is performed
The step of realizing any one of claim 1-3 the method.
9. a kind of system of chip electrostatic protection characterized by comprising
Chip, signal processing apparatus, the single pulse circuit and register of setting in the chip, the signal processing apparatus and institute
State single pulse circuit, register connection；
The single pulse circuit is connect with the power input of the chip, and the single pulse circuit connection has power supply control
Switch, the single pulse circuit are used to control the power control switch and are turned on or off the power supply of the chip；
The register is used to monitor the working condition of the chip, and in the chip operation abnormal state, to the letter
Number processing unit sends working condition abnormal signal；
The signal processing apparatus is used to receive the working condition abnormal signal that the register is sent, and according to the work shape
State abnormal signal sends interrupt trigger signal to the single trigger circuit.
10. system according to claim 9, which is characterized in that be provided with pressure unit in the single pulse circuit.
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| CN201910096324.2A CN109873397A (en) | 2019-01-31 | 2019-01-31 | A kind of method, apparatus and system of chip electrostatic protection |
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| CN201910096324.2A CN109873397A (en) | 2019-01-31 | 2019-01-31 | A kind of method, apparatus and system of chip electrostatic protection |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113723041A (en) * | 2021-09-01 | 2021-11-30 | 联芸科技（杭州）有限公司 | Power supply clamping circuit insertion method and device and storage medium |
| WO2022037495A1 (en) * | 2020-08-18 | 2022-02-24 | 深圳市万普拉斯科技有限公司 | Display screen anomaly recovery method and apparatus, computer device, and storage medium |
| CN116430212A (en) * | 2023-06-13 | 2023-07-14 | 飞腾信息技术有限公司 | Method for monitoring chip latch-up state, microprocessor and related equipment |
| WO2023240503A1 (en) * | 2022-06-15 | 2023-12-21 | 北京小米移动软件有限公司 | Display drive module, display device, anomaly processing method and apparatus, and medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2498637Y (en) * | 2001-07-13 | 2002-07-03 | 福建省轮船总公司通信导航技术服务分公司 | Self set-up voltage stable electric source with overcurrent and overvoltage protector |
| US20040120090A1 (en) * | 2002-10-31 | 2004-06-24 | International Rectifier Corporation | Half-bridge high voltage gate driver providing protectin of a transistor |
| CN101173578A (en) * | 2006-11-01 | 2008-05-07 | 芯微技术（深圳）有限公司 | Fingerprint collecting device and its method for automatically quitting locking mode |
| CN101488665A (en) * | 2008-01-18 | 2009-07-22 | 瑞鼎科技股份有限公司 | Electrostatic discharging protection circuit |
| CN207320829U (en) * | 2017-10-13 | 2018-05-04 | 国民技术股份有限公司 | A kind of electrostatic discharge protective circuit and electronic equipment |
| CN108923376A (en) * | 2018-08-22 | 2018-11-30 | 中国科学院西安光学精密机械研究所 | A kind of overcurrent turn-off function guard method of self recovery and circuit |
-
2019
- 2019-01-31 CN CN201910096324.2A patent/CN109873397A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2498637Y (en) * | 2001-07-13 | 2002-07-03 | 福建省轮船总公司通信导航技术服务分公司 | Self set-up voltage stable electric source with overcurrent and overvoltage protector |
| US20040120090A1 (en) * | 2002-10-31 | 2004-06-24 | International Rectifier Corporation | Half-bridge high voltage gate driver providing protectin of a transistor |
| CN101173578A (en) * | 2006-11-01 | 2008-05-07 | 芯微技术（深圳）有限公司 | Fingerprint collecting device and its method for automatically quitting locking mode |
| CN101488665A (en) * | 2008-01-18 | 2009-07-22 | 瑞鼎科技股份有限公司 | Electrostatic discharging protection circuit |
| CN207320829U (en) * | 2017-10-13 | 2018-05-04 | 国民技术股份有限公司 | A kind of electrostatic discharge protective circuit and electronic equipment |
| CN108923376A (en) * | 2018-08-22 | 2018-11-30 | 中国科学院西安光学精密机械研究所 | A kind of overcurrent turn-off function guard method of self recovery and circuit |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022037495A1 (en) * | 2020-08-18 | 2022-02-24 | 深圳市万普拉斯科技有限公司 | Display screen anomaly recovery method and apparatus, computer device, and storage medium |
| CN113723041A (en) * | 2021-09-01 | 2021-11-30 | 联芸科技（杭州）有限公司 | Power supply clamping circuit insertion method and device and storage medium |
| CN113723041B (en) * | 2021-09-01 | 2024-03-29 | 联芸科技(杭州)股份有限公司 | Insertion method and device of power supply clamping circuit and storage medium |
| WO2023240503A1 (en) * | 2022-06-15 | 2023-12-21 | 北京小米移动软件有限公司 | Display drive module, display device, anomaly processing method and apparatus, and medium |
| CN116430212A (en) * | 2023-06-13 | 2023-07-14 | 飞腾信息技术有限公司 | Method for monitoring chip latch-up state, microprocessor and related equipment |
| CN116430212B (en) * | 2023-06-13 | 2023-08-22 | 飞腾信息技术有限公司 | Method for monitoring chip latch-up state, microprocessor and related equipment |
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Application publication date: 20190611 |