CN109871716A - For the reliability enhancing structure and its Enhancement Method of SC PUF circuit - Google Patents
For the reliability enhancing structure and its Enhancement Method of SC PUF circuit Download PDFInfo
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Abstract
The present invention relates to circuit designs and information security field, disclose a kind of reliability enhancing structure for SC PUF circuit, including switching capacity PUF array, reliability test circuit, PUF output register, reliability marker register and control logic generation module, PUF unit includes that two capacitors sample chain, capacitor sampling chain is connected by sampled point with latch-type sense amplifier, the cathode of testing capacitor is connect by the sampled point that the first variable connector samples chain with the Article 2 capacitor in each PUF unit respectively, anode is connect with first port and second port respectively by the second variable connector, first port is connect by selection signal with ground wire or power supply, second port is connect with ground wire.The invention also discloses the Enhancement Methods of the reliability enhancing structure for SC PUF circuit.The present invention is directed to the reliability enhancing structure and its Enhancement Method of SC PUF circuit, improves the reliability of switching capacity PUF output, can directly apply to key and generate and avoid using any mechanism for correcting errors.
Description
Technical field
The present invention relates to circuit designs and information security field, and in particular to a kind of reliability increasing for SC PUF circuit
Strong structure and its Enhancement Method.
Background technique
Switching capacity (switched-capacitor circuit, SC) PUF circuit be a kind of physics of new type of safe not
Circuit (PUF) can be cloned.SC PUF realizes physics unclonable function by sampling the manufacture deviation of metal capacitance, pass through by
The key position of metallic transmission gauze covering chip after being connected with SC sample circuit, can be effective against non-destructive detection
Attack and Rebuilding Attack.Therefore, the key that SC PUF can be used for constructing high security generates and storage circuit, to protect insertion
The safety of formula system.
The basic structure of switching capacity PUF as shown in fig. 7, it by switched-capacitor circuit (SC circuit), latch-type is sensitive puts
Big device (Latch-style Sense Amplifier, LSSA), register (Register, REG) and control logic (Control
Logic, CTL) four modules are constituted.When enable signal EN is effective, and selection signal SEL is logic low, capacitor C1P、 C2P、
C1NAnd C2NUpper bottom crown be connected to ground wire GND, SC circuit work is in discharge condition, not stored charge.When SEL becomes patrolling
When collecting high, sampling capacitance C1PAnd C1NTop crown be connected to power supply potential VDD, SC circuit would operate in charge redistribution shape
State, at this time sampling capacitance C1N、C2N、C1PAnd C2PRatio deviation in the fabrication process can be converted into voltage deviation.LSSA pairs
The voltage difference amplifies, and is converted to numeral output.REG stores the numeral output of all PUF units, control logic CTL
Then it is used to generate the orderly work of control signal CLK_REG, EN and SEL driving modules.
In order to resist intrusive physical attacks, SC PUF circuit has carried out anti-invasion formula attack design, by certain length
Unidirectional metal transmission line covers the key position of chip after being connected with sample circuit, be used as the protective net of capacitive sensitivity.
When attacker attempts the key message using probe attack detection chip, certainly will need to destroy or touch metal protection
Net, parasitic capacitance entrained by probe can change the capacitance of sampling capacitance at this time, so as to cause the change of PUF output response.
But since PUF output is inevitably effected by environmental factors (temperature, voltage etc.), reliability is not high,
Mainly stablize key using various mechanisms for correcting errors at present to extract from PUF noise data, and one can be brought using mechanism for correcting errors
A little obvious problems:
1) error correction procedure needs very big executive overhead, brings very big burden to resource-constrained embedded system；
2) error correcting technique needs to generate a kind of disclosed auxiliary information Helper data to restore primary key, can reveal
The partial information of key；
3) output response of PUF needs to be directly inputted to correction module, since correction module and PUF module are often divided
From, this provides possibility for physical detecting attack.
Summary of the invention
The purpose of the present invention is to the deficiencies of above-mentioned technology, provide a kind of reliability increasing for SC PUF circuit
Strong structure and its Enhancement Method effectively increase the reliability of PUF output, enable to directly apply to key generate without
Any mechanism for correcting errors is used again.
To achieve the above object, the reliability enhancing structure for SC PUF circuit designed by the present invention, including be equipped with
The switching capacity PUF array of several PUF units further includes the reliability test electricity connecting with the switching capacity PUF array
Road, the PUF output register for storing the PUF unit numeral output, the reliability for storing the PUF unit reliability ident value
Marker register and the control logic generation module for generating control signal, each PUF unit include two capacitor samplings
Chain, every capacitor sampling chain include concatenated two sampling capacitances, and every capacitor sampling chain passes through sampled point and lock
It deposits type sense amplifier to be connected, between two sampling capacitances, the reliability test circuit includes the sample
The cathode of testing capacitor, the testing capacitor is electric with the Article 2 in each PUF unit respectively by the first variable connector
Hold the sampled point connection of sampling chain, the anode of the testing capacitor by the second variable connector respectively with first port and second end
Mouth connection, wherein the first port is connect by selection signal with ground wire or power supply, and the second port is connect with ground wire.
Preferably, the anode of the cathode ground connection of the capacitor sampling chain, the capacitor sampling chain passes through selection signal and ground
The sampled point of line or power supply connection, the capacitor sampling chain is connect by selection signal with ground wire.
A kind of Enhancement Method of the reliability enhancing structure for SC PUF circuit, including registration phase and working stage,
Before registration phase, the switching capacity PUF array use, to each of the switching capacity PUF array PUF unit
Reliability test is carried out, the reliability ident value of all PUF units is generated, generate the switching capacity PUF array can
It by property identity map, and is stored in the reliability marker register, in working stage, extracts each PUF unit
Numeral output is simultaneously stored in the PUF output register, by numeral output in the PUF output register and described reliable
Reliability identity map in property marker register is exported together to outer treatment circuit, and the outer treatment circuit is according to
Reliability identity map extracts reliable numeral output and constructs key.
Preferably, in the registration phase the following steps are included:
A) make external enable signal and test control signal effective simultaneously, registration phase starts to carry out, the control logic
Generation module is connected to first variable connector, and the testing capacitor accesses in the switching capacity PUF array, into reliable
Property test pattern, with the switching capacity PUF array in the sampled point of Article 2 capacitor sampling chain in a PUF unit connect
It connects；
B second variable connector) is connected to the first port, meanwhile, control logic generation module generates control
Signal drives the PUF cell operation, reads the first numeral output of the PUF unit and is stored in the PUF output deposit
In device；
C second variable connector) is connected to the second port, reads the second numeral output of the PUF unit
And with the first numeral output in the PUF output register with or calculate the reliability ident value of the PUF unit；
D) repeating said steps A)~step C), the reliability ident value of all PUF units is generated, is opened described in generation
The powered-down reliability identity map for holding PUF array, the Helper Data data as chip are stored in the reliability mark and post
In storage.
Preferably, in the working stage the following steps are included:
A) keep test control signal invalid, first variable connector is opened, and the testing capacitor is bypassed；
B) make external enable signal effective, the control logic generation module generates selection signal according to timing requirements and makes
Energy signal, successively extracts the numeral output of each PUF unit and is stored in the PUF output register；
C) reliability in the numeral output and the reliability marker register in the PUF output register is identified
Mapping is exported together to outer treatment circuit, and the outer treatment circuit extracts reliable number according to the reliability identity map
Word output building key.
The principle of the present invention is as follows:
SC PUF circuit mainly realizes physics unclonable function, capacity ratio by acquiring the process deviation of metal capacitance
The mismatch of example is converted into voltage difference Δ VPNAfterwards, latched type sense amplifier is converted to numeral output after amplifying, and examines
Offset voltage Δ V can be generated because of the adaptation of metal-oxide-semiconductor in the fabrication process by considering latch-type sense amplifierOFFSET, therefore it is final
Determine effective deviation voltage Δ V=Δ V of latch-type sense amplifier outputPN+ΔVOFFSET, the polarity of Δ V determines latch-type
Sense amplifier is output number 0 or number 1.Also, the order of magnitude of PUF unit large deviations voltage Δ V determines this
The output reliability of PUF unit, | Δ V | bigger representative means that deviation voltage Δ V is influenced to change polar probability more by V&T
It is low, therefore its reliability is higher.Since Δ V is mainly determined by the process deviation that chip is difficult to avoid that in the fabrication process, nothing
Method is determined in design, but if each PUF unit can be tested automatically after SC PUF circuit manufactures completion | Δ V |,
Then select | Δ V | biggish PUF unit is exported as key, is abandoned | Δ V | it is worth lesser PUF unit, so that it may mention significantly
The reliability of high PUF circuit.
Compared with prior art, the present invention having the advantage that
1, the reliability of SC PUF circuit output is improved, key generation can be directly applied to, generating has pole
The key of high stability, to avoid using any mechanism for correcting errors；
2, due to not having to use mechanism for correcting errors, it is excessive and bring peace to avoid the expense caused by the introducing because of mechanism for correcting errors
The problem of full hidden danger.
Detailed description of the invention
Fig. 1 is overall architecture schematic diagram of the present invention for the reliability enhancing structure of SC PUF circuit；
Fig. 2 is the basic structure schematic diagram of reliability test circuit；
Fig. 3 is the first variable connector K1Equivalent circuit diagram when disconnection；
Fig. 4 is the second variable connector K2It is connected to equivalent circuit diagram when first port；
Fig. 5 is the second variable connector K2It is connected to equivalent circuit diagram when second port；
Fig. 6 is reliable key extraction process schematic diagram；
Fig. 7 is the basic structure schematic diagram of tradition SC PUF unit.
Each part numbers are as follows in figure:
PUF unit 1, switching capacity PUF array 2, reliability test circuit 3, control logic generation module 4, capacitor sampling
Chain 5, first port 6, second port 7, PUF output register REG1, reliability marker register REG2, the sensitive amplification of latch-type
Device LSSA, the first variable connector K1, the second variable connector K2。
Specific embodiment
The following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments.
As shown in Figures 1 and 2, the present invention is directed to the reliability enhancing structure of SC PUF circuit, including is equipped with several PUF
The switching capacity PUF array 2 of unit 1 further includes the reliability test circuit 3 connecting with switching capacity PUF array 2, storage PUF
The PUF output register REG1 of 1 numeral output of unit, the reliability marker register for storing 1 reliability ident value of PUF unit
REG2 and the control logic generation module 4 for generating control signal, each PUF unit 1 include that two capacitors sample chain 5, every electricity
Holding sampling chain 5 includes concatenated two sampling capacitances, and in the present embodiment, first capacitor sampling chain 5 includes that concatenated sampling is electric
Hold C1NWith sampling capacitance C2N, it includes concatenated sampling capacitance C that Article 2 capacitor, which samples chain 5,1PWith sampling capacitance C2P, every capacitor
Sampling chain 5 is connected by sampled point with latch-type sense amplifier LSSA, and sample is between two sampling capacitances, reliably
Property test circuit 3 include testing capacitor CT, testing capacitor CTCathode pass through the first variable connector K1Respectively with each PUF unit
The sampled point connection of Article 2 capacitor sampling chain 5 in 1, testing capacitor CTAnode pass through the second variable connector K2Respectively with
Single port 6 and second port 7 connect, wherein and first port 6 is connect by selection signal SEL with ground wire GND or power vd D, the
Two-port netwerk 7 is connect with ground wire GND, in addition, the cathode ground connection of capacitor sampling chain 5, the anode of capacitor sampling chain 5 passes through selection signal
SEL is connect with ground wire GND or power vd D, and the sampled point of capacitor sampling chain 5 is connect by selection signal SEL with ground wire GND.
A kind of Enhancement Method of the reliability enhancing structure for SC PUF circuit, including registration phase and working stage,
In registration phase the following steps are included:
A) make external enable signal RSTN and test control signal TEST effective simultaneously, registration phase starts to carry out, control
Logic generation module 4 makes the first variable connector K1Connection, into reliability test mode, testing capacitor CTAccess switching capacity PUF
In array 2, it is connect with the sampled point of the Article 2 capacitor sampling chain 5 in a PUF unit 1 in switching capacity PUF array 2；
B) by the second variable connector K2It is connected to first port 6, meanwhile, control logic generation module 4 generates control signal
SEL and EN driving PUF unit 1 works, at this point, testing capacitor CTWith sampling capacitance C1PParallel connection, the simplification etc. of capacitance mismatch acquisition
Circuit is imitated as shown in figure 4, reading the first numeral output, that is, deviation voltage Δ V of PUF unit 11And it is stored in PUF output deposit
In device REG1, at this point, P1, voltage difference between N are as follows:
Due to the voltage difference under 1 normal operating conditions of PUF unit between P, N are as follows:
Total deviation voltageWith the deviation voltage Δ under PUF unit normal operating conditions
The difference of V are as follows:
If C1P=C2P, due to CT< < C1P+C2P, therefore
C) by the second variable connector K2It is connected to second port 7, reads the second numeral output, that is, potential difference of PUF unit 1
ΔV2And in PUF output register REG1 the first numeral output with or calculate PUF unit 1 reliability ident value, at this time
Testing capacitor CTWith sampling capacitance C2PParallel connection, capacitance mismatch acquisition simple equivalent circuit as shown in figure 5,
Deviation voltage Δ V2With the difference of the deviation voltage Δ V under 1 normal operating conditions of PUF unit are as follows:
According to formula (1) and formula (2), enable
As the second variable connector K2When being connected to first port 6, deviation voltage Δ V1=Δ V+VT, when the second variable connector
K2When being connected to second port 7, deviation voltage Δ V2=Δ V-VT, in both cases, when the latch of the connection of PUF unit 1
No change has taken place for the output of type sense amplifier LSSA, that is, Δ V1With Δ V2Polarity it is identical, at this time just meet:
ΔV1> 0 and Δ V2> 0 or Δ V1< 0 and Δ V2<0。
Due to VTIt for positive value, can obtain: Δ V1>VTOr Δ V1<-VT, it may be assumed that | Δ V | > VT。
That is, the absolute value of effective deviation voltage Δ V of the PUF unit 1 is greater than test voltage V at this timeT.If VTCompared with
Greatly, then the PUF unit 1 is just not readily susceptible to the influence of environment temperature or supply voltage, reliability is very high.
On the contrary, as the second variable connector K2When being connected respectively to first port 6 and second port 7, latch-type is sensitive to be put
The output of big device LSSA changes, then meets:
ΔV1> 0 and Δ V2< 0 or Δ V1< 0 and Δ V2>0, it may be assumed that | Δ V |<VT。
The absolute value of effective deviation voltage Δ V of PUF unit 1 is smaller at this time, exports unstable.
Therefore, we can identify this according to whether the numeral output of PUF unit 1 in above-mentioned two situations changes
Whether PUF unit 1 is reliable.Assuming that Oi1And Oi2Respectively the second variable connector K2When being connected to first port 6 and second port 7
The output of i PUF unit 1, enables RiFor the reliability ident value of the PUF unit, can obtain
Ri=Oi1⊙Oi2
Work as RiWhen=1, O is indicatedi1And Oi2Identical, reliably, otherwise, it was demonstrated that the PUF unit 1 representing the PUF unit 1 is
Output is insecure；
D step A) is repeated)~step C), the reliability ident value of all PUF units 1 is generated, generates switching capacity PUF gusts
The reliability identity map RB=[R of column 21,R2,…RN], the Helper Data data as chip are stored in reliability mark
In register REG2.
In working stage the following steps are included:
A) make test control signal TEST invalid, the first variable connector K1It opens, testing capacitor CTIt is bypassed；
B) make external enable signal RSTN effective, control logic generation module 4 generates selection signal SEL according to timing requirements
With enable signal EN, successively extracts the numeral output of each PUF unit 1 and be stored in PUF output register REG1；
C) reliability in the numeral output and reliability marker register REG2 in PUF output register REG1 is identified
Mapping is exported together to outer treatment circuit, and outer treatment circuit extracts reliable numeral output structure according to reliability identity map
Key is built, as shown in Figure 6.
The present invention improves the reliability of SC PUF circuit output for the reliability enhancing structure of SC PUF circuit, makes it
Key generation can be directly applied to, the key with superregulated property is generated, to avoid using any mechanism for correcting errors；Simultaneously
Due to not having to use mechanism for correcting errors, it is excessive and bring asking for security risk to avoid the expense caused by the introducing because of mechanism for correcting errors
Topic.
Claims (5)
1. a kind of reliability enhancing structure for SC PUF circuit, the switching capacity including being equipped with several PUF units (1)
PUF array (2), it is characterised in that: further include the reliability test circuit (3) being connect with the switching capacity PUF array (2),
Store PUF output register (REG1), storage PUF unit (1) the reliability mark of PUF unit (1) numeral output
The reliability marker register (REG2) of value and the control logic generation module (4) for generating control signal, each PUF unit
It (1) include that two capacitors sample chain (5), every capacitor sampling chain (5) includes concatenated two sampling capacitances, described in every
Capacitor sampling chain (5) is connected by sampled point with latch-type sense amplifier (LSSA), and the sample is adopted described in two
Between sample capacitor, the reliability test circuit (3) includes testing capacitor, and the cathode of the testing capacitor is opened by the first multichannel
Close (K1) connect respectively with the sampled point of Article 2 capacitor sampling chain (5) in each PUF unit (1), the test electricity
The anode of appearance passes through the second variable connector (K2) connect respectively with first port (6) and second port (7), wherein described first
Port (6) is connect by selection signal with ground wire or power supply, and the second port (7) connect with ground wire.
2. being directed to the reliability enhancing structure of SC PUF circuit according to claim 1, it is characterised in that: the capacitor sampling
The cathode of chain (5) is grounded, and the anode of capacitor sampling chain (5) is connect by selection signal with ground wire or power supply, the capacitor
The sampled point of sampling chain (5) is connect by selection signal with ground wire.
3. special for the Enhancement Method of the reliability enhancing structure of SC PUF circuit described in a kind of any one of claims 1 or 2
Sign is: the Enhancement Method includes registration phase and working stage, and in registration phase, the switching capacity PUF array (2) makes
With before, reliability test is carried out to each of the switching capacity PUF array (2) the PUF unit (1), generates all institutes
The reliability ident value for stating PUF unit (1), generates the reliability identity map of the switching capacity PUF array (2), and stores
In the reliability marker register (REG2), in working stage, the numeral output of each PUF unit (1) is extracted simultaneously
Be stored in the PUF output register (REG1), by the PUF output register (REG1) numeral output and it is described can
Reliability identity map in property marker register (REG2) is exported together to outer treatment circuit, the outer treatment circuit
Reliable numeral output, which is extracted, according to the reliability identity map constructs key.
4. according to claim 3 for the Enhancement Method of the reliability enhancing structure of SC PUF circuit, it is characterised in that:
The registration phase the following steps are included:
A) make external enable signal and test control signal effective simultaneously, registration phase starts to carry out, and the control logic generates
Module (4) makes the first variable connector (K1) be connected to, the testing capacitor accesses in the switching capacity PUF array (2), into
Enter reliability test mode, is sampled with the wherein capacitor in a PUF unit (1) in the switching capacity PUF array (2)
The sampled point of chain (5) connects；
B) by the second variable connector (K2) be connected to the first port (6), meanwhile, control logic generation module (4) generates
It controls signal and drives PUF unit (1) work, read the first numeral output of the PUF unit (1) and be stored in described
In PUF output register (REG1)；
C) by the second variable connector (K2) second port (7) are connected to, read the second number of the PUF unit (1)
Export and with the first numeral output in the PUF output register (REG1) with or calculate the reliability of the PUF unit (1)
Ident value；
D) repeating said steps A)~step C), the reliability ident value of all PUF units (1) is generated, is opened described in generation
The powered-down reliability identity map for holding PUF array (2), the Helper Data data as chip are stored in the reliability mark
Know in register (REG2).
5. according to claim 3 for the Enhancement Method of the reliability enhancing structure of SC PUF circuit, it is characterised in that:
The working stage the following steps are included:
A) keep test control signal invalid, the first variable connector (K1) open, the testing capacitor is bypassed；
B) make external enable signal effective, the control logic generation module (4) generates selection signal according to timing requirements and makes
Energy signal, successively extracts the numeral output of each PUF unit (1) and is stored in the PUF output register (REG1)；
C) by the numeral output and the reliability marker register (REG2) in the PUF output register (REG1) can
It is exported together by property identity map to outer treatment circuit, the outer treatment circuit is extracted according to the reliability identity map
Reliable numeral output constructs key.
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|---|---|---|---|
| CN201910137560.4A CN109871716A (en) | 2019-02-25 | 2019-02-25 | For the reliability enhancing structure and its Enhancement Method of SC PUF circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910137560.4A CN109871716A (en) | 2019-02-25 | 2019-02-25 | For the reliability enhancing structure and its Enhancement Method of SC PUF circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112364391A (en) * | 2020-11-17 | 2021-02-12 | 湖北大学 | Arbiter PUF reliable response screening system and bias control and response screening method thereof |
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| CN104052604A (en) * | 2014-05-23 | 2014-09-17 | 戴葵 | Novel anti-cracking PUF structure |
| CN107292200A (en) * | 2017-05-02 | 2017-10-24 | 湖北工业大学 | Strong PUF circuit structures based on switching capacity |
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2019
- 2019-02-25 CN CN201910137560.4A patent/CN109871716A/en active Pending
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| CN104052604A (en) * | 2014-05-23 | 2014-09-17 | 戴葵 | Novel anti-cracking PUF structure |
| CN108694335A (en) * | 2017-04-12 | 2018-10-23 | 恩智浦美国有限公司 | The method of physics unclonable function and generation PUF responses based on SRAM |
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| Title |
|---|
| ZHANGQING HE: "A Reliable Strong PUF Based on Switched-Capacitor Circuit", 《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS》 * |
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| CN112364391A (en) * | 2020-11-17 | 2021-02-12 | 湖北大学 | Arbiter PUF reliable response screening system and bias control and response screening method thereof |
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Application publication date: 20190611 |