CN109860154A - Electric resistance structure and forming method thereof - Google Patents
Electric resistance structure and forming method thereof Download PDFInfo
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- CN109860154A CN109860154A CN201910156415.0A CN201910156415A CN109860154A CN 109860154 A CN109860154 A CN 109860154A CN 201910156415 A CN201910156415 A CN 201910156415A CN 109860154 A CN109860154 A CN 109860154A
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Abstract
A kind of electric resistance structure and forming method thereof, wherein electric resistance structure includes: substrate, and the substrate includes the firstth area；First resistor floor positioned at firstth area of substrate surface, the first resistor floor include first end area；The first plug positioned at first end area surface, first plug are contacted with first end area；Positioned at the second resistance layer of the first resistor layer surface, the second resistance floor includes the second end area, and the second resistance layer exposes the first plug of part；Positioned at the second plug of first plug surface, second plug is contacted with the first plug, and second plug is contacted with the second end area.The resistance of the electric resistance structure is larger, and manufactures area and do not increase additionally.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of electric resistance structure and forming method thereof.
Background technique
In the semiconductor device, polysilicon resistance can largely be used.Undoped polysilicon resistivity with higher,
The prior art is generally by being doped polysilicon resistance, to change the resistivity of polysilicon, doping concentration is higher, polycrystalline
The resistivity of silicon resistor is lower, and the Doped ions include N-type ion or P-type ion.The resistivity of polysilicon resistance can be with
Size by controlling doping concentration controls, and the polysilicon resistance can be formed in oxidization isolation layer, can be with
Save chip area.
However, the prior art, which manufactures high-resistance polysilicon resistance, needs biggish manufacture area.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of electric resistance structures and forming method thereof, to form high-resistance resistance
Structure, and do not increase manufacture area additionally.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of electric resistance structure, comprising: substrate, the substrate packet
Include the firstth area；First resistor floor positioned at firstth area of substrate surface, the first resistor floor include first end area；It is located at
First plug on first end area surface, first plug are contacted with first end area；Positioned at the first resistor layer
The second resistance layer on surface, the second resistance floor include the second end area, and the second resistance layer exposes part first and inserts
Plug；Positioned at the second plug of first plug surface, second plug is contacted with the first plug, and second plug with
The contact of the second end area.
Optionally, be projected as first bar shaped of the first resistor layer in substrate surface, the shape packet of first bar shaped
Include S-shaped, rectangle or spiral shape.
Optionally, be projected as second bar shaped of the second resistance layer in substrate surface, the shape packet of second bar shaped
Include S-shaped, rectangle or spiral shape.
Optionally, the material of first plug includes metal；The material of second plug includes metal.
Optionally, further includes: positioned at the first medium layer of substrate and first resistor layer surface, first plug is located at the
In one dielectric layer, and the first medium layer exposes the top surface of the first plug；Positioned at first medium layer, the first plug and
The second dielectric layer of second resistance layer surface, second plug are located in second dielectric layer, and second dielectric layer exposure
The top surface of second plug out.
Optionally, the first resistor floor further includes the third end region opposite with first end area；Electric resistance structure also wraps
Include: the third plug in first medium layer, the third plug are contacted with third end region, and the first medium layer is sudden and violent
Expose the top surface of third plug；The 4th plug in second dielectric layer, the 4th plug are contacted with third plug；
The second resistance floor further includes fourth end region opposite with the second end area；The electric resistance structure further include: be located at described
The 5th plug in second dielectric layer, the 5th plug are contacted with the 4th end region of second resistance layer, and described second is situated between
Matter layer exposes the top surface of the 5th plug.
Optionally, further includes: positioned at the 3rd resistor layer of second medium layer surface, the 3rd resistor layer includes the 5th end
Area, portion, the 3rd resistor layer expose the 5th plug of part；Positioned at the 6th plug of the 5th plug surface, the described 6th
Plug is contacted with the 5th plug, and the 6th plug is contacted with the fifth end area of 3rd resistor floor.
Optionally, the material of the first resistor layer includes polysilicon, have in the first resistor layer first adulterate from
Son；First Doped ions include N-type ion or P-type ion.
Optionally, the material of the second resistance layer includes polysilicon, have in the second resistance layer second adulterate from
Son；Second Doped ions include N-type ion or P-type ion.
Correspondingly, the present invention also provides a kind of forming methods of electric resistance structure, comprising: provide substrate, the substrate includes
Firstth area；First resistor floor is formed on the first area surface of the substrate, the first resistor floor includes first end area；Institute
It states first end area surface and forms the first plug, first plug is contacted with first end area；In the first resistor layer table
Face forms second resistance layer, and the second resistance floor includes the second end area, and the second resistance layer exposes part first and inserts
Plug；Form the second plug in first plug surface, second plug contacts with the first plug, and second plug and
The contact of the second end area.
Compared with prior art, technical solution of the present invention has the advantages that
In the electric resistance structure that technical solution of the present invention provides, due to the first end of first plug and first resistor layer
Area's contact, and second plug is contacted with the first plug, and the second end area of second plug and second resistance floor connects
Touching, therefore, the first resistor layer is linked together with second resistance layer by the first plug and the second plug.It can be seen that
Not only there is first resistor floor in firstth area of the substrate, also there is second resistance layer, so that the resistance in the firstth area of substrate
It is larger.And the first resistor floor and second resistance floor are respectively positioned in the firstth area of substrate, so that the face that the electric resistance structure occupies
Product increases without additional.To sum up, the resistance of the electric resistance structure is larger, and footprint area increases without additional.
Further, further includes: positioned at the 3rd resistor layer of second resistance layer surface.Since the second resistance layer further includes
Fourth end region opposite with the second end area, the 4th end region are contacted with the 5th plug, the 5th plug and the 6th
Plug contact, and the 6th plug is also contacted with the fifth end area of 3rd resistor floor, therefore, the 3rd resistor layer and the
Two resistive layers are linked together by the 5th plug and the 6th plug.To sum up, not only there is the first electricity in firstth area of substrate
Resistance layer and second resistance layer also have 3rd resistor layer, and therefore, the resistance of the electric resistance structure is larger, also, first resistor
Floor, second resistance floor and 3rd resistor floor are respectively positioned on the firstth area of substrate, it is therefore not necessary to additionally increase manufacture area.To sum up, described
The resistance of electric resistance structure is higher, and manufactures area and increase without additional.
Detailed description of the invention
Fig. 1 and Fig. 2 is a kind of structural schematic diagram of electric resistance structure；
Fig. 3 to Figure 11 is the structural schematic diagram of each step of one embodiment of forming method of electric resistance structure of the present invention.
Specific embodiment
As described in background, the manufacture area of high-resistance electric resistance structure is larger.
Fig. 1 and Fig. 2 is a kind of structural schematic diagram of electric resistance structure.
Fig. 1 and Fig. 2 are please referred to, Fig. 1 is top view of the Fig. 2 along the direction X1, and Fig. 2 is side view of the Fig. 1 along the direction X2 surface,
Substrate 100；Resistive layer 101 positioned at 100 surface of substrate；Positioned at the medium of resistive layer 101 side wall and top surface
Layer 102, the dielectric layer 102 is interior to have the opening (not marking in figure) for exposing 101 atop part surface of resistive layer；Positioned at institute
State the plug 103 in opening.
In above-mentioned electric resistance structure, the material of the resistive layer 101 is polysilicon, have in the resistive layer 101 doping from
Son, the Doped ions are used to improve the conductive capability of resistive layer 101.When the doping concentration of Doped ions in resistive layer 101 is protected
When holding constant, the resistance sizes and length of the resistive layer 101 on current path of the electric resistance structure are closely related.Specifically,
Length of the resistive layer 101 on current path is longer, and the resistance of electric resistance structure is bigger, therefore, high-resistance in order to be formed
Electric resistance structure may extend away length of the resistive layer 101 on current path.
However, needing biggish manufacture area when length of the resistive layer 101 on current path is longer, it may be assumed that high electricity
The electric resistance structure of resistance needs additional increase to manufacture area.
To solve the technical problem, the present invention provides a kind of electric resistance structures, comprising: the substrate includes the firstth area；
First resistor floor positioned at firstth area of substrate surface, the first resistor floor include first end area；Positioned at described first
First plug on end region surface, first plug are contacted with first end area；Positioned at the of the first resistor layer surface
Two resistive layers, the second resistance floor include the second end area, and the second resistance layer exposes the first plug of part；Positioned at institute
The second plug of the first plug surface is stated, second plug is contacted with the first plug, and second plug and the second end
Area's contact.The resistance of the electric resistance structure is higher, and manufactures area without additional increase.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 3 to Figure 11 is the structural schematic diagram of each step of one embodiment of forming method of electric resistance structure of the present invention.
Fig. 3 and Fig. 4 are please referred to, Fig. 3 is top view of the Fig. 4 on the direction Y1, and Fig. 4 is side view of the Fig. 3 on the direction Y2,
Substrate 200 is provided, the substrate 200 includes the first area A；First resistor floor is formed on the first area surface A of the substrate 200
201, the first resistor floor 201 includes first end area C1.
It should be noted that Fig. 4 is side view.
The material of the substrate 200 includes semiconductor material or insulating materials, when the material of the substrate 200 is partly to lead
When body material, the material of the substrate 200 includes: body silicon, body germanium, SiGe, silicon carbide, silicon-on-insulator or germanium on insulator；
When the material of the substrate 200 is insulating materials, the material of the substrate 200 includes: ruby, sapphire or glass.
In the present embodiment, the first area A of the substrate 200 is for being subsequently formed first resistor floor 201 and second resistance
Layer.
In the present embodiment, the substrate 200 further includes the second area B, and the secondth area B is adjacent with the first area A.
In the present embodiment, the material of the substrate 200 be body silicon, due in body silicon doped with foreign ion so that base
Bottom 200 is conductive, therefore, is formed before first resistor layer 201, further includes: in the surface shape of the first resistor layer 201
At separation layer 230, the separation layer 230 is for avoiding first resistor layer 201 that short circuit occurs.
The material of the separation layer 230 includes silica.
In other embodiments, when the material of the substrate is insulating materials, separation layer is not formed.
At work, electric current flows through the electric resistance structure that the method is formed in first resistor layer 201, specifically, described
First resistor floor 201 includes that opposite first end area C1 and third end region C3, electric current flow to third by first end area C1
End region C3, alternatively, electric current flow to first end area C1 by third end region C3.
The first end area C1 is contacted for subsequent with the first plug, and the third end region C3 is used for subsequent and third
Plug contact.
The forming method of the first resistor layer 201 includes: to form first resistor material membrane on 200 surface of substrate；
In part, first resistor material film surface forms the first mask layer；Using first mask layer as exposure mask, first electricity is etched
Material membrane is hindered, the first resistor layer 201 is formed.
The material of the first resistor material membrane includes polysilicon, and the formation process of the first resistor material membrane includes low
Pressure chemical vapor deposition technique.
Doped with the first Doped ions in the first resistor material membrane, first Doped ions include N-type ion or
Person's P-type ion；The N-type impurity ion includes phosphonium ion or arsenic ion；The P-type ion includes boron ion.Described first
Doped ions are for keeping first resistor layer 201 conductive.
In the present embodiment, the technique of the first Doped ions is mixed in the first resistor material membrane as doping work in situ
Skill mixes N-type impurity ion or p type impurity ion while forming first resistor material membrane.In other embodiments, shape
After first resistor material membrane, the first Doped ions are mixed in the first resistor material membrane using ion implantation technology.
Since the resistance value of polysilicon resistance is directly proportional to the resistivity of polycrystalline silicon material, resistance length, with polysilicon resistance
Area of section be in inverse ratio, and the resistivity of the polycrystalline silicon material is related to the doping concentration of the first Doped ions, therefore, logical
Cross the section face of the doping concentration, polysilicon resistance length and polysilicon resistance of the first Doped ions in control polysilicon membrane
Product, can control the resistance value of polysilicon resistance.
The material of first mask layer includes silicon nitride or titanium nitride, and first mask layer is used to form the first electricity
The exposure mask of resistance layer 201.
Using first mask layer as exposure mask, etch the first resistor material membrane technique include dry etch process and
One of wet-etching technology or two kinds of combinations.
The first resistor layer 201 is projected as the first bar shaped 200 surface of substrate.In the present embodiment, described first
The shape of bar shaped is S-shaped (see Fig. 3).In other embodiments, the shape of first bar shaped includes rectangle or spiral shape.
In the present embodiment, the projected image due to the first resistor layer 201 on 200 surface of substrate is S,
It is longer in length of the first resistor floor 201 that 200 first area A of substrate is formed on current path, and the first resistor
Length of the layer 201 on current path is positively correlated with resistance sizes, and therefore, the resistance of the first resistor layer 201 is larger.
In other embodiments, the forming method of the first resistor layer includes: in the substrate and insulation surface shape
At the 4th dielectric layer；First groove is formed in the 4th dielectric layer, and the first groove bottom-exposed goes out separation layer
Top surface；In the first groove and the 4th dielectric layer surface forms first resistor material membrane, the first resistor material
Film is full of first groove；The first resistor material membrane is planarized, until the top surface of the 4th dielectric layer is exposed, described
First resistor layer is formed in first groove.
Fig. 5 and Fig. 6 are please referred to, Fig. 5 is consistent with the view direction of Fig. 3, and Fig. 6 is consistent with the view direction of Fig. 4, described
The surface of one end area C1 forms the first plug 203, and first plug 203 is contacted with first end area C1.
The forming method of first plug 203 includes: the surface and separation layer 230 in the first resistor layer 201
Surface forms first medium layer 202, has the first opening (not marking in figure) in the first medium layer 202, described first opens
Mouth exposes the first end area C1 of first resistor floor 201；The first plug 203 of formation in first opening, described first
Plug 203 is contacted with first end area C1.
The forming method of the first medium layer 202 includes: on the surface of the first resistor layer 201 and separation layer 230
Form first medium film；Part first medium film is removed, first medium layer 202 is formed, has the in the first medium layer 202
One opening, first open bottom expose the first end area C1 of first resistor floor 201.
The material of the first medium film includes silica or silicon oxynitride.The formation process packet of the first medium film
Include chemical vapor deposition process or physical gas-phase deposition.
The first opening in the first medium floor 202 exposes 201 first end area C1 of first resistor floor, so that subsequent
The first plug 203 in the first opening can be contacted with first resistor layer 201.
The forming method of first plug 203 includes: to be formed in first opening with 202 surface of first medium layer
First plug material film, the first plug material film is full of the first opening；The first plug material film is planarized, until sudden and violent
The surface for exposing first medium layer 202 forms the first plug 203 in first opening.
The material of the first plug material film includes metal, and the formation process of the first plug material film includes chemistry
Gas-phase deposition or physical gas-phase deposition.
The technique for planarizing the first plug material film includes chemical mechanical milling tech.
In the present embodiment, further includes: third opening (not marking in figure), institute are formed in the first medium layer 202
State the top surface that third open bottom exposes 201 third end region C3 of first resistor layer；It is formed in the third is open
Third plug 230.
The material of the third plug 230 includes metal, and the third plug 230 with subsequent 4th plug for contacting.
Referring to FIG. 7, Fig. 7 is structural schematic diagram on the basis of Fig. 6, the is formed on 202 surface of first medium layer
Two resistive layers 204, the second resistance floor 204 include the second end area C2, and the second resistance layer 204 exposes part first
Plug 203；It is formed on the surface of the second resistance layer 204, the first plug 203, third plug 230 and first medium layer 202
Second medium film 205.
In the present embodiment, the second resistance layer 204 exposes all surfaces of the first plug 203；Second electricity
The forming method of resistance layer 204 includes: to form second resistance material membrane on 202 surface of first medium layer；In the second electricity of part
It hinders material film surface and forms the second mask layer；Using second mask layer as exposure mask, the second resistance material membrane is etched, is formed
The second resistance layer 204.
The material of the second resistance material membrane includes polysilicon, and the formation process of the second resistance material membrane includes low
Pressure chemical vapor deposition technique.Doped with the second Doped ions, the second Doped ions packet in the second resistance material membrane
Include N-type ion or P-type ion；The N-type impurity ion includes phosphonium ion or arsenic ion；The P-type ion include boron from
Son.Second Doped ions are for keeping second resistance layer 204 conductive.
In the present embodiment, the technique of the second Doped ions is mixed in the second resistance material membrane as doping work in situ
Skill mixes N-type impurity ion or p type impurity ion while forming second resistance material membrane.In other embodiments, shape
After second resistance material membrane, the second Doped ions are mixed in the second resistance material membrane using ion implantation technology.
There are the second Doped ions in the second resistance layer 204, second Doped ions include N-type ion or P
Type ion；The N-type impurity ion includes phosphonium ion or arsenic ion；The P-type ion includes boron ion.
The second resistance layer 204 exposes the first plug of part 203, is conducive to the second plug and first being subsequently formed
Plug 203 contacts.
The second resistance floor 204 includes the second end area C2, and subsequent second plug is contacted with the second end area C2, and institute
The second plug to be stated also to contact with the first plug 203, first plug 203 is contacted with first resistor layer 201, therefore, described
Two resistive layers 204 are contacted with first resistor layer 201.
The second resistance floor 204 further includes the fourth end region C4 opposite with the second end area C2, the 4th end
The area C4, area is electrically connected with subsequent 5th plug.
The material of the second medium film 205 includes silica, and the formation process of the second medium film 205 includes chemistry
Gas-phase deposition or physical gas-phase deposition.
The second medium film 205 has for being subsequently formed second dielectric layer, in the second dielectric layer exposes the
The second opening of two end region C2 and the 4th opening for exposing the 4th end region C4.The forming method of the second dielectric layer has
Body please refers to Fig. 8 to Fig. 9.
Referring to FIG. 8, removal part second medium film 205, until part the second end area C2 is exposed, described first
The second initial openings 240 are formed in second medium film 205 on plug 203.
The forming method of second initial openings 240 include one of dry etch process and wet-etching technology or
Two kinds of person combinations.
Second initial openings 240 are for being subsequently formed the second opening.
Referring to FIG. 9, the second medium film 205 (see Fig. 8) of removal 240 bottom part of the second initial openings, until
The top surface of the first plug 203 is exposed, second dielectric layer 225 is formed, there is the second opening in the second dielectric layer 225
250, second opening 250 exposes part the second end area C2 and the first plug 203.
The technique for removing the second medium film 205 of 240 bottom part of the second initial openings includes dry etch process
With one of wet-etching technology or two kinds of combinations.
Second opening 250 is used for the second plug of subsequent receiving.
In the present embodiment, further includes: the second medium film 205 on the 4th end region surface C4 of removal forms the 5th opening
260,260 bottom-exposeds of the 5th opening go out the top surface of the 4th end region C4 of 204 part of second resistance layer；Remove part
Second medium film 205, forms the 4th opening 270, and 270 bottom-exposeds of the 4th opening go out third plug 230.
Figure 10 and Figure 11 are please referred to, Figure 10 is consistent with the view direction of Fig. 4, and Figure 11 is consistent with the view direction of Fig. 3, in institute
It states in the second opening 250 and forms the second plug 280.
The material of second plug 280 is metal.Since second opening 250 exposes the second end area C2 and the
One plug 203, then the second plug 280 being located in the second opening 250 contact with second resistance layer 204 and the first plug 201, make
It obtains the first resistor layer 201 and is contacted with second resistance layer 204 by the first plug 203 and the second plug 280.Due to the base
Not only there is first resistor floor 201 in the first area A at bottom 200, also there is second resistance layer 204 to be therefore formed by resistance junction
The resistance of structure is larger.Also, the first resistor floor 201 and second resistance floor 204 are respectively positioned in the first area A, it is therefore not necessary to volume
Outer increase manufactures area.To sum up, the resistance for the electric resistance structure that the method is formed is larger, and manufactures area without additional increase.
In the present embodiment, further includes: form the 5th plug 281 in the 5th opening 260；In the 4th opening 270
The 4th plug 282 of interior formation.
4th plug 282 is contacted with third plug 230, the 4th plug 282 and the 5th plug 281 be used for it is outer
Boundary's electrical contact.
In other embodiments, it is formed after second plug 280, the 4th plug 282 and the 5th plug 281, is also wrapped
Include: the 3rd resistor layer positioned at 225 surface of second dielectric layer, the 3rd resistor floor include fifth end area, the third electricity
Resistance layer exposes the 5th plug 281 of part；The 6th plug positioned at 281 surface of the 5th plug, the 6th plug and
The contact of five plugs 281, and the 6th plug is contacted with the fifth end area of 3rd resistor floor.
In the present embodiment, first resistor layer 201 and second resistance layer 204 are only formed.
Correspondingly, please referring to Figure 11 the present invention also provides a kind of electric resistance structure, comprising:
Substrate 200, the substrate 200 include the first area A；
First resistor floor 201 positioned at the 200 first area surface A of substrate, the first resistor layer 201 include first end
Area, portion C1；
The first plug 203 (see Figure 10) positioned at the first end area surface C1, first plug 203 and first end
Area, portion C1 contact；
Second resistance layer 204 positioned at 201 surface of first resistor layer, the second resistance layer 204 include second end
Area, portion C2, the second resistance layer 204 expose the first plug 203；
The second plug 280 positioned at 203 surface of the first plug, second plug 280 connect with the first plug 203
Touching, and second plug 280 is contacted with the second end area C2.
It is described in detail below in conjunction with attached drawing.
In first bar shaped that is projected as on 200 surface of substrate, the shape of first bar shaped includes the first resistor layer 201
S-shaped, rectangle or spiral shape.
In second bar shaped that is projected as on 200 surface of substrate, the shape of second bar shaped includes the second resistance layer 204
S-shaped, rectangle or spiral shape.
The material of first plug 203 includes metal；The material of second plug 280 includes metal.
Further include: the first medium layer 202 positioned at 201 surface of substrate 200 and first resistor layer, first plug 203
In first medium layer 202, and the first medium layer 202 exposes the top surface of the first plug 203；It is situated between positioned at first
The second dielectric layer 225 on 201 surface of matter layer 202 and second resistance layer, second plug 280 are located in second dielectric layer 225,
And the second dielectric layer 225 exposes the top surface of the second plug 280.
The first resistor floor 201 further includes the third end region C3 opposite with first end area C1；Electric resistance structure also wraps
Include: the third plug 230 in first medium layer 202, the third plug 230 are contacted with third end region C3, and described
One dielectric layer 202 exposes the top surface of third plug 230；The 4th plug 282 in second dielectric layer 225, it is described
4th plug 282 is contacted with third plug 230；The second resistance floor 204 further includes the opposite with the second end area C2 the 4th
End region C4；The electric resistance structure further include: the 5th plug 281 in the second dielectric layer 225, the 5th plug
281 contact with the 4th end region C4 of second resistance layer 204, and the second dielectric layer 225 exposes the top of the 5th plug 281
Portion surface.
Further include: the 3rd resistor layer positioned at 225 surface of second dielectric layer, the 3rd resistor layer includes fifth end
Area, the 3rd resistor layer expose the 5th plug 281 of part；The 6th plug positioned at 281 surface of the 5th plug, it is described
6th plug is contacted with the 5th plug 281, and the 6th plug is contacted with the fifth end area of 3rd resistor floor.
The material of the first resistor layer 201 includes polysilicon, have in the first resistor layer 201 first adulterate from
Son；First Doped ions include N-type ion or P-type ion.
The material of the second resistance layer 204 includes polysilicon, have in the second resistance layer 204 second adulterate from
Son；Second Doped ions include N-type ion or P-type ion.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of electric resistance structure characterized by comprising
Substrate, the substrate include the firstth area；
First resistor floor positioned at firstth area of substrate surface, the first resistor floor include first end area；
The first plug positioned at first end area surface, first plug are contacted with first end area；
Positioned at the second resistance layer of the first resistor layer surface, the second resistance floor includes the second end area, and described second
Resistive layer exposes the first plug of part；
Positioned at the second plug of first plug surface, second plug is contacted with the first plug, and second plug
It is contacted with the second end area.
2. electric resistance structure as described in claim 1, which is characterized in that the first resistor layer is projected as substrate surface
One bar shaped, the shape of first bar shaped include S-shaped, rectangle or spiral shape.
3. electric resistance structure as described in claim 1, which is characterized in that the second resistance layer is projected as substrate surface
Two bar shapeds, the shape of second bar shaped include S-shaped, rectangle or spiral shape.
4. electric resistance structure as described in claim 1, which is characterized in that the material of first plug includes metal；Described
The material of two plugs includes metal.
5. electric resistance structure as described in claim 1, which is characterized in that further include: positioned at substrate and first resistor layer surface
First medium layer, first plug are located in first medium layer, and the first medium layer exposes the top of the first plug
Surface；Positioned at the second dielectric layer of first medium layer, the first plug and second resistance layer surface, second plug is located at second
In dielectric layer, and the second dielectric layer exposes the top surface of the second plug.
6. electric resistance structure as claimed in claim 5, which is characterized in that the first resistor floor further includes and first end area phase
Pair third end region；Electric resistance structure further include: the third plug in first medium layer, the third plug and third end
The contact of area, portion, and the first medium layer exposes the top surface of third plug；The 4th plug in second dielectric layer,
4th plug is contacted with third plug；The second resistance floor further includes fourth end region opposite with the second end area；
The electric resistance structure further include: the 5th plug in the second dielectric layer, the 5th plug connect with the 4th end region
Touching, and the second dielectric layer exposes the top surface of the 5th plug.
7. electric resistance structure as claimed in claim 6, which is characterized in that further include: positioned at the third electricity of second medium layer surface
Resistance layer, the 3rd resistor floor include fifth end area, and the 3rd resistor layer exposes the 5th plug of part；Positioned at described
6th plug of five plug surfaces, the 6th plug are contacted with the 5th plug, and the 6th plug and 3rd resistor layer
The contact of fifth end area.
8. electric resistance structure as described in claim 1, which is characterized in that the material of the first resistor layer includes polysilicon, institute
Stating has the first Doped ions in first resistor layer；First Doped ions include N-type ion or P-type ion.
9. electric resistance structure as described in claim 1, which is characterized in that the material of the second resistance layer includes polysilicon, institute
Stating has the second Doped ions in second resistance layer；Second Doped ions include N-type ion or P-type ion.
10. a kind of forming method of the electric resistance structure as described in any one of claim 1 to 9 characterized by comprising
Substrate is provided, the substrate includes the firstth area；
First resistor floor is formed on the first area surface of the substrate, the first resistor floor includes first end area；
The first plug is formed on first end area surface, first plug is contacted with first end area；
Second resistance layer is formed in the first resistor layer surface, the second resistance floor includes the second end area, and described second
Resistive layer exposes the first plug of part；
The second plug is formed in first plug surface, second plug is contacted with the first plug, and second plug
It is contacted with the second end area.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1125899A (en) * | 1994-08-19 | 1996-07-03 | 精工电子工业株式会社 | Semiconductor intergrated circuit |
| CN1841742A (en) * | 2005-02-28 | 2006-10-04 | 三星电子株式会社 | Semiconductor device including resistor and method of fabricating the same |
| CN103021816A (en) * | 2012-12-26 | 2013-04-03 | 上海宏力半导体制造有限公司 | Polyresistor structure, method for manufacturing same and polyresistor |
| CN104900629A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Testing structure for detecting deviation |
| CN105720001A (en) * | 2014-12-02 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN109148423A (en) * | 2017-06-27 | 2019-01-04 | 瑞萨电子株式会社 | Semiconductor device |
-
2019
- 2019-03-01 CN CN201910156415.0A patent/CN109860154A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1125899A (en) * | 1994-08-19 | 1996-07-03 | 精工电子工业株式会社 | Semiconductor intergrated circuit |
| CN1841742A (en) * | 2005-02-28 | 2006-10-04 | 三星电子株式会社 | Semiconductor device including resistor and method of fabricating the same |
| CN103021816A (en) * | 2012-12-26 | 2013-04-03 | 上海宏力半导体制造有限公司 | Polyresistor structure, method for manufacturing same and polyresistor |
| CN104900629A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Testing structure for detecting deviation |
| CN105720001A (en) * | 2014-12-02 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN109148423A (en) * | 2017-06-27 | 2019-01-04 | 瑞萨电子株式会社 | Semiconductor device |
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