CN109860106B - Preparation method of display substrate - Google Patents
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- CN109860106B CN109860106B CN201910150600.9A CN201910150600A CN109860106B CN 109860106 B CN109860106 B CN 109860106B CN 201910150600 A CN201910150600 A CN 201910150600A CN 109860106 B CN109860106 B CN 109860106B
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Abstract
The invention discloses a preparation method of a display substrate. The preparation method comprises the following steps: forming a metal layer on a substrate; forming a first insulating film on the substrate on which the metal layer is formed; and forming a first transparent electrode layer on the first insulating film and processing the first transparent electrode layer by adopting a high-temperature annealing process. By using the preparation method, in the process of cooling the first transparent electrode layer in a high-temperature annealing process and an atmospheric environment, the upper surface of the metal layer is still covered with the first insulating film for protection and is not exposed in a high-temperature aerobic environment, so that the metal layer is prevented from being oxidized and corroded, the preparation quality of a subsequent film layer is ensured, and the display quality of the display substrate is ensured.
Description
Technical Field
The invention relates to the technical field of display, in particular to a preparation method of a display substrate.
Background
With the development of technology, flat panel display devices have replaced bulky Cathode Ray Tube (CRT) display devices. Currently, commonly used flat panel Display devices include Liquid Crystal Display (LCD) devices and Organic Light-Emitting Diode (OLED) Display devices.
In both LCD and OLED display devices, the display area is composed of a plurality of pixel units, and the plurality of pixel units are formed by dividing a plurality of metal wires arranged in a periodic and longitudinal manner. The resistance of these metal lines directly affects the speed of response of the scan or data signals. In order to increase the speed of scanning or data signal response, copper metal with lower resistivity is gradually replacing aluminum metal and aluminum alloy and is applied to display products with low power consumption and high resolution. However, copper metal is easily oxidized and corroded, and when the copper metal is exposed in a high-temperature aerobic environment in a large area, the copper metal is more easily oxidized and corroded. The film layer on the copper metal is prone to tilting or falling off due to the oxidized and corroded copper metal, and the film layer electrically connected with the copper metal is unreliable in connection with the copper metal, so that the display quality of the display device is affected.
Disclosure of Invention
An object of an embodiment of the present invention is to provide a method for manufacturing a display substrate, so as to prevent a metal layer from being oxidized and corroded.
In order to solve the above technical problem, an embodiment of the present invention provides a method for manufacturing a display substrate, including:
forming a metal layer on a substrate;
forming a first insulating film on the substrate on which the metal layer is formed;
and forming a first transparent electrode layer on the first insulating film and processing the first transparent electrode layer by adopting a high-temperature annealing process.
Optionally, the preparation method further comprises:
and forming a second insulating film on the substrate on which the first transparent electrode layer is formed, and patterning the second insulating film and the first insulating film simultaneously to form a second insulating layer and a first insulating layer, wherein second through holes for exposing the metal layer are formed in the second insulating layer and the first insulating layer.
Optionally, the simultaneously patterning the second insulating film and the first insulating film includes:
coating a layer of photoresist on the second insulating film;
exposing and developing the photoresist by using a mask plate, forming a complete exposure area at the second via hole position, having no photoresist, forming an unexposed area at other positions, and keeping the photoresist;
etching the second insulating film and the first insulating film in the complete exposure area by adopting a first isotropic etching process;
and etching the second insulating film and the first insulating film in the complete exposure area by adopting an anisotropic second etching process.
Optionally, before the forming of the first transparent electrode layer on the first insulating film, the method further includes:
and forming a resin layer on the first insulating film, wherein a first through hole corresponding to the metal layer is formed in the resin layer.
Optionally, there is an overlapping portion between an orthographic projection of the first via on the substrate and an orthographic projection of the metal layer on the substrate.
Optionally, before or after the forming of the first transparent electrode layer on the first insulating film, the method further includes:
and removing the resin residue at the first through hole.
Optionally, the resin residue at the first via hole is removed by plasma, and the reaction gas includes at least one of an oxidizing gas and an inert gas.
Optionally, the material of the metal layer includes copper.
Optionally, the process conditions of the first etching process include: the pressure of the chamber is 20 mT-220 mT, the flow of sulfur hexafluoride is 1000 sccm-2000 sccm, the flow of oxygen is 1000 sccm-2000 sccm, and the flow of helium is 2000 sccm-4000 sccm.
Optionally, the process conditions of the second etching process include: the pressure of the chamber is 30 mT-230 mT, the flow of sulfur hexafluoride is 1000 sccm-2000 sccm, the flow of oxygen is 1000 sccm-2000 sccm, and the flow of helium is 0-1000 sccm.
According to the preparation method of the display substrate, when the first transparent electrode layer is treated by adopting the high-temperature annealing process, the first insulating film is still covered on the upper surface of the metal layer, so that the first insulating film can well protect the metal layer in the high-temperature annealing and cooling process of the first transparent electrode layer in the atmospheric environment, the metal layer is not exposed in the high-temperature aerobic environment any more, the metal layer is prevented from being oxidized and corroded, the preparation quality of a subsequent film layer is ensured, and the display quality of the display substrate is ensured.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a schematic diagram of a method of fabricating a display substrate;
FIG. 2a is a schematic plan view of a display substrate after a resin layer is formed thereon;
FIG. 2b is a schematic view of the cross-sectional structure A-A of FIG. 2 a;
FIG. 3a is a schematic diagram illustrating a planar structure of a display substrate after a second insulating layer is formed thereon;
FIG. 3B is a schematic cross-sectional view B-B of FIG. 3 a;
FIG. 4a is a schematic plane view of the display substrate after the second transparent electrode layer is formed;
FIG. 4b is a schematic cross-sectional view of C-C of FIG. 4 a;
FIG. 5 is a schematic view of a method of manufacturing a display substrate according to a first embodiment of the present invention;
FIG. 6a is a schematic plan view illustrating a resin layer formed according to the first embodiment of the present invention;
FIG. 6b is a schematic cross-sectional view of D-D of FIG. 6 a;
FIG. 7a is a schematic plan view illustrating a second insulating layer and a first insulating layer after forming a first insulating layer according to the first embodiment of the present invention;
FIG. 7b is a schematic view of the cross-sectional structure E-E of FIG. 7 a;
FIG. 8 is an image of an "undercut" structure resulting from the simultaneous patterning of a second insulating layer and a first insulating layer using a single etch process;
FIG. 9a is a schematic view showing the structure of the second insulating layer after the photoresist is exposed and developed;
FIG. 9b is a schematic structural diagram of the structure of FIG. 9a after a first etching process;
FIG. 9c is a schematic structural diagram of the structure of FIG. 9b after a second etching process;
FIG. 9d is an image corresponding to FIG. 9 c;
FIG. 10a is a schematic plan view illustrating a second transparent electrode layer according to the first embodiment of the present invention;
fig. 10b is a schematic view of the cross-sectional structure F-F in fig. 10 a.
Description of reference numerals:
1-a metal layer; 2 — a first insulating layer; 2' -a first insulating film;
3-a resin layer; 4-a second insulating layer; 5-a second transparent electrode layer;
6-residue; 7, photoresist; 91-third via hole;
92-a fourth via; 93 — a first via; 94 — second via.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The term "patterning" as used herein, including processes of coating with photoresist, mask exposure, development, stripping of photoresist, etc., for the organic film layer, and processes of coating with photoresist, mask exposure, development, etching, stripping of photoresist, etc., for the inorganic film layer, are well-established processes. The deposition may be performed by a known process such as sputtering, evaporation, chemical vapor deposition, etc., the coating may be performed by a known coating process, and the etching may be performed by a known method, which is not particularly limited herein.
Fig. 1 is a schematic diagram of a method for manufacturing a display substrate. Fig. 2a is a schematic plan view showing a structure of a substrate after a resin layer is formed thereon, and fig. 2b is a schematic sectional view taken along line a-a in fig. 2 a. FIG. 3a is a schematic plane view showing the substrate after a second insulating layer is formed, and FIG. 3B is a schematic cross-sectional view of B-B in FIG. 3 a. Fig. 4a is a schematic plane structure diagram of the display substrate after the second transparent electrode layer is formed, and fig. 4b is a schematic cross-sectional structure diagram of C-C in fig. 4 a. The method for manufacturing the display substrate will be described in detail with reference to fig. 1 to 4 b.
S101: a metal layer 1 is formed on the substrate (substrate not shown). Referring to fig. 2a and 2b, the metal layer 1 may include a metal wire and a metal terminal disposed at one end of the metal wire.
S102: a first insulating layer 2 and a resin layer 3 are formed on the metal layer 1. Specifically, a first insulating film and a resin film are sequentially formed on a substrate on which a metal layer 1 is formed; the first insulating film and the resin film are simultaneously patterned to simultaneously form the first insulating layer 2 and the resin layer 3, the pattern of the resin layer 3 is the same as that of the first insulating layer 2, and third via holes 91 for exposing the metal layer 1 are provided on the first insulating layer 2 and the resin layer 3, as shown in fig. 2a and 2 b. The resin film is thick, and in order to prevent the resin film from affecting the electrical connection between the metal layer 1 and the integrated circuit chip or the flexible circuit board, the resin film covering the metal layer 1 needs to be removed in a large area, so the size d of the third via hole 91 is greater than the width of the metal layer 1, and the size d of the third via hole 91 is 100 um-30 mm. The third via hole 91 with the size d of 100um to 30mm can expose a large area of the metal layer 1.
S103: a first transparent electrode layer located in the display region is formed on the resin layer 3. The method specifically comprises the following steps:
a first transparent electrode film is formed on the substrate on which the resin layer 3 is formed.
And patterning the first transparent electrode film to form a first transparent electrode layer in the display area. Fig. 2a to 4b show a structural film layer (not shown in the first transparent electrode layer) of the display substrate. In fig. 2a to 4b, the first transparent electrode layer is not disposed above the metal layer 1, and thus, after the first transparent electrode layer is formed, the metal layer 1 is still exposed through the third via hole 91.
And processing the first transparent electrode layer by adopting a high-temperature annealing process to obtain the first transparent electrode layer. The high temperature annealing process can reduce the resistance and stress of the first transparent electrode layer, the temperature of the high temperature annealing process can be 200-250 ℃, and inert gas such as argon or helium is adopted.
S104: a second insulating layer 4 is formed on the first transparent electrode layer. The method specifically comprises the following steps: forming a second insulating film on the substrate on which the first transparent electrode layer is formed; and patterning the second insulating film to form a second insulating layer 4, wherein a fourth via 92 for exposing the metal layer 1 is disposed on the second insulating layer 4, and the fourth via 92 is located on the third via 91, as shown in fig. 3a and 3 b.
In fig. 3a and 3b, the second insulating layer 4, which is located at the region where the third via 91 is located, is disposed on the upper surface of the metal layer 1. In actual production, the metal layer 1 in the region where the third via hole 91 is located is easily oxidized and corroded, so that the second insulating layer 4 on the upper surface of the metal layer 1 is tilted and even falls off, and the subsequent film layer is affected.
S105: a second transparent electrode layer 5 is formed on the second insulating layer 4. The method specifically comprises the following steps: forming a second transparent electrode film on the substrate on which the second insulating layer 4 is formed; and patterning the second transparent electrode film to form a second transparent electrode layer 5, wherein the second transparent electrode layer 5 is electrically connected with the metal layer 1 through a fourth via 92, as shown in fig. 4a and 4 b. If the metal layer 1 is oxidized and corroded, the second transparent electrode layer 5 may be in unreliable electrical contact with the metal layer 1 or fall off, which may affect the display quality of the display substrate.
It is easily understood that one of the first transparent electrode layer and the second transparent electrode layer 5 is a pixel electrode, and the other is a common electrode.
As a result of research by the present inventors, the root cause of the oxidation corrosion of the metal layer 1 including copper or other active metals is that, before the high temperature annealing process is performed on the first transparent electrode layer, the first insulating film on the upper surface of the metal layer 1 has been patterned, so that the metal layer 1 is exposed through the third via hole 91, and thus the first insulating film cannot protect the metal layer 1 at the third via hole 91. Therefore, when the first transparent electrode layer is subjected to a high-temperature annealing process and is subjected to cooling treatment in an atmospheric environment, the metal layer 1 is oxidized and corroded due to exposure to a high-temperature aerobic environment, and the subsequent film layer is affected.
In order to avoid the metal layer 1 from being oxidized and corroded, the following schemes can be adopted:
(1) in the high-temperature annealing process of the first transparent electrode layer, the temperature is reduced to normal temperature in an independently closed inert atmosphere to prevent the metal layer from being exposed in an aerobic environment, but such a scheme needs additional equipment, and the manufacturing cost of the display substrate is increased;
(2) in the high-temperature annealing process of the first transparent electrode layer, the temperature of the high-temperature annealing process is reduced (the high-temperature annealing temperature is generally reduced to 60-70 ℃) so as to reduce the risk of oxidation corrosion of the metal layer, but the annealing crystallization of the first transparent electrode layer is insufficient, so that the electrical and optical properties of the first transparent electrode layer are reduced, and the display quality is influenced;
(3) when the first transparent electrode layer is formed, the first transparent electrode layer is also formed as a protective layer on the metal layer 1 shown in fig. 2a and 2 b. The first transparent electrode film is usually made of ito, which has poor water-oxygen resistance, so that the first transparent electrode layer is retained on the metal layer 1 as a protection layer to reduce the oxidation corrosion of the metal layer 1, but the oxidation corrosion of the metal layer 1 cannot be completely avoided. If the scheme is adopted, a transparent electrode material with better waterproof and oxygen-proof effects is also needed to be adopted;
(4) in step S102, "patterning the first insulating film and the resin film simultaneously" is divided into patterning the first insulating film alone to form a first insulating layer, and the first insulating layer is provided with micropores (having a pore size of 3 to 100um) for exposing the metal layer 1. Because the size of micropore is 3um ~ 100um, consequently, can effectively avoid metal level 1 oxidation corrosion. Such a solution requires an additional mask for patterning the first insulating layer, which increases the manufacturing cost of the display substrate.
In order to effectively prevent the metal layer from being oxidized and corroded, the embodiment of the invention provides a preparation method of a display substrate. The preparation method of the display substrate comprises the following steps:
forming a metal layer on a substrate;
forming a first insulating film on the substrate on which the metal layer is formed;
and forming a first transparent electrode layer on the first insulating film and processing the first transparent electrode layer by adopting a high-temperature annealing process.
According to the preparation method of the display substrate, in the process of carrying out the high-temperature annealing process on the first transparent electrode layer and carrying out the cooling treatment in the atmospheric environment, the first insulating film still covers the upper surface of the metal layer instead of being exposed in the high-temperature aerobic environment, so that the first insulating film can well protect the metal layer, the metal layer is prevented from being oxidized and corroded, the preparation quality of a subsequent film layer is guaranteed, and the display quality of the display substrate is guaranteed. Moreover, the first transparent electrode layer can be cooled in the atmospheric environment due to the protection of the metal layer by the first insulating film, so that the cost of the high-temperature annealing process is reduced.
The technical contents of the present invention will be described in detail through specific implementation procedures.
FIG. 5 is a schematic view of a method for manufacturing a display substrate according to a first embodiment of the present invention. The following describes the technical solution of the embodiment of the present invention in detail with reference to fig. 5.
The preparation method of the display substrate comprises the following steps:
s21: a metal layer 1 is formed on the substrate (substrate not shown). Specifically, a metal film is formed on a substrate; the metal thin film is patterned to form a metal layer 1. The metal layer 1 may include a metal wire and a metal terminal disposed at one end of the metal wire. The material of the metal layer 1 may include copper metal or other active metal. The material of the metal layer 1 may include at least one of metals such as potassium, calcium, sodium, magnesium, aluminum, zinc, iron, tin, lead, copper, and alloys thereof.
S22: a first insulating film is formed on the substrate on which the metal layer 1 is formed. The method specifically comprises the following steps: a first insulating film 2' is formed on the substrate on which the metal layer 1 is formed by a deposition method, as shown in fig. 6a and 6b, fig. 6a is a schematic plane structure after a resin layer is formed according to the first embodiment of the present invention, and fig. 6b is a schematic cross-sectional structure of D-D in fig. 6 a.
In order to make the transparent electrode layer located in the display region have a flat surface, in this embodiment, the method for preparing the display substrate may further include:
s221: a resin layer is formed on the first insulating film 2', and first via holes corresponding to the metal layers are provided on the resin layer. Specifically, a resin film is formed on the first insulating film 2' by a coating method; the resin film is patterned to form a resin layer 3, as shown in fig. 6a and 6 b. The resin layer 3 is provided with a first via 93 corresponding to the metal layer 1, and the first via 93 is located above the metal layer 1. There is an overlapping portion between the orthographic projection of the first via 93 on the substrate and the orthographic projection of the metal layer 1 on the substrate. The size d' of the first via hole 93 is 100um to 30 mm. Since only the resin film is patterned when the resin layer 3 is formed, the upper surface of the metal layer 1 at the area where the first via 93 is located is still covered with the first insulating film 2'.
S23: a first transparent electrode layer is formed on the resin layer 3 and is treated by a high temperature annealing process. The method specifically comprises the following steps:
a first transparent electrode film is formed on the substrate on which the resin layer 3 is formed.
And patterning the first transparent electrode film to form a first transparent electrode layer in the display area. The pattern of the first transparent electrode is not shown in the related drawings of the present embodiment. In the drawings of the present embodiment, the first transparent electrode layer is not disposed above the metal layer 1, and therefore, after the first transparent electrode layer is formed, the upper surface of the metal layer 1 is still covered with the first insulating film 2'.
And processing the first transparent electrode layer by adopting a high-temperature annealing process. The high temperature annealing process can reduce the resistance and stress of the first transparent electrode layer, the temperature of the high temperature annealing process can be 200-250 ℃, and inert gas such as argon or nitrogen is adopted.
In this embodiment, in the cooling process performed on the first transparent electrode layer in the high temperature annealing process and the atmospheric environment, the first insulating film 2 'is still covered on the upper surface of the metal layer 1 instead of being exposed in the high temperature aerobic environment, so that the first insulating film 2' can well protect the metal layer 1, the metal layer 1 is prevented from being oxidized and corroded, the preparation quality of the subsequent film layer is ensured, and the display quality of the display substrate is ensured. Moreover, the first transparent electrode layer can be cooled in the atmospheric environment due to the protection of the metal layer by the first insulating film, so that the cost of the high-temperature annealing process is reduced.
After the first transparent electrode layer is formed, it is necessary to form the second insulating layer 4 on the substrate on which the first transparent electrode layer is formed. In actual production, if the second insulating film is formed directly on the substrate on which the first transparent electrode layer is formed after the first transparent electrode layer is annealed at a high temperature, a bulge is liable to occur on a portion of the second insulating film which is in contact with the first insulating film 2' through the first via hole 93. The inventors have found that the main cause of the bulge is that the first insulating film is located below the resin layer, and after the resin film is patterned to form the resin layer 3, the resin residue 6 adheres to the first insulating film 2' at the first via 93 position, as shown in fig. 6a and 6 b. The residue 6 adheres to the first insulating film 2 'and forms bubbles in a subsequent process, so that the second insulating layer 4 on the upper surface of the first insulating film 2' bulges.
In order to eliminate the swelling problem of the second insulating layer 4, before or after S23, that is, before or after forming the first transparent electrode layer, the method for manufacturing a display substrate may further include:
s222: and removing the resin residue at the position of the first via hole. The process of removing the residue at the location of the first via is characterized by using a gaseous species to react with the resin residue 6 for the purpose of removing the tree residue. Specifically, the first via hole may be treated by plasma to remove a resin residue remaining at the first via hole 93 during the formation of the resin layer. The reactive gas used for plasma etching may include an oxidizing gasAnd an inert gas. The oxidizing gas may comprise sulfur hexafluoride (SF)6) Chlorine (Cl)2) Oxygen (O)2) The inert gas may include helium (He), nitrogen (N)2) At least one of (1). In this embodiment, the plasma is composed of SF6、O2And He. Wherein, SF6The flow rate is 750sccm to 3000sccm, O2The flow rate is 750 sccm-3000 sccm, and the He flow rate is 1500 sccm-6000 sccm. The pressure of the cavity is 60 mT-240 mT (8 kPa-32 kPa), the equipment power is 2000W-8000W, and the processing time is 5-20 s.
It is actually proved that, after the second insulating layer 4 is formed again after the step S222 is adopted, the bulge does not occur on the portion of the second insulating layer 4 contacting the first insulating layer 2 through the first via 93.
It is easily understood that, in other embodiments, the resin layer 3 may not be provided, and the first transparent electrode layer may be formed directly on the first insulating film 2'. And processing the first transparent electrode layer by adopting a high-temperature annealing process.
S24: forming a second insulating film on the first transparent electrode layer, simultaneously patterning the second insulating film and the first insulating film to form a second insulating layer 4 and a first insulating layer 2, and providing a second via hole 94 for exposing the metal layer 1 on the second insulating layer 4 and the first insulating layer 2. Specifically, a second insulating film may be formed on the substrate on which the first transparent electrode layer is formed, and the second insulating film may be in contact with the first insulating film 2' through the first via hole 93; the second insulating film and the first insulating film 2' are simultaneously patterned to form the second insulating layer 4 and the first insulating layer 2. The second insulating layer 4 and the first insulating layer 2 are provided with second through holes 94 extending therethrough, and the metal layer 1 is exposed through the second through holes 94, as shown in fig. 7a and 7 b. Fig. 7a is a schematic plan view illustrating a first embodiment of the present invention after forming a second insulating layer and a first insulating layer, and fig. 7b is a schematic cross-sectional view illustrating a cross-sectional view of a cross-section E-E shown in fig. 7 a. The size of the second via 94 may be 3um to 100 um. The time for simultaneously patterning the second insulating film and the first insulating film 2 'may be specifically set according to the thickness of the first insulating film 2'.
It is easily understood that, in other embodiments, after the first transparent electrode layer is formed, the first insulating film 2' may be patterned to form a first insulating layer on which the first sub-via hole for exposing the metal layer 1 is disposed. Then, a second insulating film is formed on the first transparent electrode layer, the second insulating film is patterned to form a second insulating layer, a second sub-via hole corresponding to the first sub-via hole is formed in the second insulating layer, and the metal layer 1 is exposed through the first sub-via hole and the second sub-via hole.
In order to reduce the number of patterning, in the present embodiment, the second insulating film and the first insulating film 2' are simultaneously patterned using one mask to form the second insulating layer 4 and the first insulating layer 2. The second insulating layer 4 and the first insulating layer 2 have the same pattern. The second insulating layer 4 and the first insulating layer 2 are provided with second through holes 94, and the metal layer 1 is exposed through the second through holes 94. In such a way, the number of masks in the manufacturing process of the display substrate can be reduced, the patterning times can be reduced, and the manufacturing time and the cost of the display substrate can be reduced.
The inventors have found that, in the process of patterning the second insulating film and the first insulating film simultaneously, if the second via hole 94 is formed by etching from top to bottom by using one etching process, the first formed second insulating layer 4 is in an etching environment for a long time. Typically, the second insulating layer 4 is a composite layer including two or more sub-film layers. The sub-film layer close to the first insulating layer 2 has the fastest etching rate due to the softest texture. Therefore, during a long etching process, the sub-film layer close to the first insulating layer 2 may be significantly etched and shrunk to form an "undercut" structure similar to an eave shape, as shown in fig. 8, where fig. 8 is an image of the "undercut" structure caused when the second insulating layer and the first insulating layer are formed by a single etching process and patterned synchronously. The "undercut" structure can cause an open circuit in the electrode trace bridged by the second via, resulting in a display anomaly.
The conventional method for improving or preventing the undercut structure is to adjust the film forming process conditions of each sub-film layer of the second insulating layer 4 to meet the gradual change of the hardness of each sub-film layer from top to bottom, thereby eliminating the drilling. However, the film texture adjustment needs to consider the matching with other related film layers, which not only complicates the process, but also seriously affects the product characteristics. Other prior art methods of repairing "undercut" structures require additional process steps and equipment and are not currently available in mass production.
In this embodiment, in order to improve or prevent the "undercut" structure, the patterning of the second insulating film and the first insulating film simultaneously may include:
coating a layer of photoresist on the second insulating film;
exposing and developing the photoresist by using a mask plate, forming a complete exposure area at the second via hole position without the photoresist, forming an unexposed area at other positions, and keeping the photoresist, as shown in fig. 9a, wherein fig. 9a is a structural schematic diagram of the photoresist after exposure and development in the process of forming the second insulating layer according to the first embodiment of the invention;
and etching the second insulating film and the first insulating film in the complete exposure area by using an isotropic first etching process to form a fourth transition via 94 ', as shown in fig. 9b, where fig. 9b is a schematic structural diagram of the structure of fig. 9a after the first etching process is performed, and fig. 9b only shows one side edge of the fourth transition via 94'. As shown in fig. 9b, the second insulating layer is a composite layer formed by the first sub-film layer 41 and the second sub-film layer 42, and the first sub-film layer 41 is adjacent to the first insulating layer 2. Typically, the film layer texture of the first sub-film layer 41 is softer than the second sub-film layer 42. When the first etching process is used to etch the insulating film, the fourth transition via 94' is over-etched at a position close to the photoresist 7 because the first etching process is isotropic. Meanwhile, since the first sub-film layer 41 has a softer film texture than the second sub-film layer 42, the fourth transitional via 94' is formed on the first sub-film layer 41 by drilling and recessing. It is easily understood that the dry etching process includes a chemical reaction process and a physical bombardment process. Wherein, the chemical reaction process is isotropic etching, and an over-etching area can be formed; the physical bombardment process is anisotropic etching, and no over-etched region is formed. The dominant positions of the chemical reaction process and the physical bombardment process in the etching process can be changed by adjusting the process parameters. Therefore, the second insulating film and the first insulating film are etched by the isotropic first etching process, that is, the second insulating film and the first insulating film in the complete exposure area are etched by the isotropic first etching process.
And etching the second insulating film and the first insulating film in the complete exposure area by adopting a second anisotropic etching process, namely etching the second insulating film and the first insulating film in the complete exposure area by adopting a second anisotropic etching process which is dominant. The dry etching process comprises a chemical reaction process and a physical bombardment process. Wherein, the chemical reaction process is isotropic etching, and an over-etching area can be formed; the physical bombardment process is anisotropic etching, and no over-etched region is formed. The dominant positions of the chemical reaction process and the physical bombardment process in the etching process can be changed by adjusting the process parameters. In the second etching process, the anisotropy is dominant, that is, in the second etching process, the physical bombardment process is dominant. When the physical bombardment is used to bombard the insulating film, the insulating layer blocked by the photoresist 7 remains, and the insulating layer not blocked by the photoresist 7 is etched away, so as to form the second via hole 94 as shown in fig. 9c, and the second via hole 94 is not retracted on the first sub-film layer 41 close to the first insulating layer 2, i.e. the second via hole 94 no longer has an "undercut" structure. Fig. 9c is a schematic structural diagram of the structure of fig. 9b after a second etching process is performed on the structure.
And stripping the residual photoresist.
Fig. 9d is an image corresponding to fig. 9 c. After the first etching process and the second etching process are sequentially performed as shown in fig. 9d, the second via hole 94 no longer has an "undercut" structure as shown in the square frame of fig. 9 d.
The first etch process includes, but is not limited to, a plasma etch mode. In this embodiment, the process conditions of the first etching process may include: the power (source power) is 6kW to 10kW, the bias power (bias power) is 1kW to 3kW, the chamber pressure is 20mT to 220mT (2.67kPa to 29.3kPa), the chamber temperature is 40 ℃ to 50 ℃, the sulfur hexafluoride flow is 1000sccm to 2000sccm, the oxygen flow is 1000sccm to 2000sccm, the helium flow is 2000sccm to 4000sccm, and the etching time is 10s to 25 s. It is easily understood that the etching time of the first etching process may be set according to the actual thickness and process of the first insulating film and the second insulating film.
The second etch process includes, but is not limited to, a reactive ion assisted etch mode. In this embodiment, the process conditions of the second etching process may include: the power (source power) is 6kW to 10kW, the bias power (bias power) is 6kW to 10kW, the chamber pressure is 30mT to 230mT (4kPa to 30.7kPa), the chamber temperature is 40 ℃ to 50 ℃, the sulfur hexafluoride flow is 1000sccm to 2000sccm, the oxygen flow is 1000sccm to 2000sccm, the helium flow is 0sccm to 1000sccm, and the etching time is 10s to 20 s. It is easily understood that the etching time of the second etching process may be set according to the actual thickness and process of the first insulating film and the second insulating film.
In specific implementation, the first etching process and the second etching process may be performed sequentially using different devices or chambers, or may be performed continuously using the same device or chamber.
S25: a second transparent electrode layer 5 is formed on the second insulating layer 4, and the second transparent electrode layer 5 is electrically connected to the metal layer 1 through a second via hole 94. The method specifically comprises the following steps: forming a second transparent electrode film on the substrate on which the second insulating layer 4 is formed; and patterning the second transparent electrode film to form a second transparent electrode layer 5, wherein the second transparent electrode layer 5 is in contact with and electrically connected with the metal layer 1 through a second via hole 94. Fig. 10a and 10b show a schematic plan view of the second transparent electrode layer formed in the first embodiment of the present invention in fig. 10a, and fig. 10b shows a schematic sectional view of F-F in fig. 10 a. Practice proves that the metal layer 1 is not oxidized and corroded, so that the second transparent electrode layer 5 which is in contact with and electrically connected with the metal layer 1 falls off, and the second transparent electrode layer 5 is in good electric contact with the metal layer 1.
In this embodiment, after the first transparent electrode layer is formed, the second insulating layer and the first insulating layer are simultaneously formed by a single patterning process, so that the first insulating film still covers the upper surface of the metal layer during the high temperature annealing process for forming the first transparent electrode layer. Therefore, in the process of carrying out high-temperature annealing cooling on the first transparent electrode layer in the atmospheric environment, the first insulating film can well protect the metal layer, so that the metal layer is not exposed in a high-temperature aerobic environment any more, the metal layer is prevented from being oxidized and corroded, the preparation quality of a subsequent film layer is ensured, and the display quality of the display substrate is ensured.
It is easy to understand that the purpose of avoiding the metal layer from being oxidized and corroded can be achieved as long as it is ensured that the first insulating film still covers the upper surface of the metal layer when the first transparent electrode layer is formed, i.e. the patterning process of the first insulating film is located after the first transparent electrode layer process. In other embodiments, the via hole on the first insulating layer may not be formed at the same time as the via hole on the second insulating layer, and after the high temperature annealing process is performed on the first transparent electrode layer, the via hole on the first insulating layer and the via hole on the second insulating layer may be respectively formed by two patterning processes as long as the metal layer is exposed through the via hole.
In the description of the embodiments of the present invention, it should be understood that the terms "upper", "lower", "front", "rear", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
In the description of the embodiments of the present invention, it should be noted that the term "connected" is to be understood broadly and may be directly connected or indirectly connected through an intermediate, unless otherwise explicitly specified or limited. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A method for preparing a display substrate is characterized by comprising the following steps:
forming a metal layer on a substrate, wherein the metal layer comprises a metal lead and a metal terminal arranged at one end of the metal lead, and the metal layer is used for electrically connecting with an integrated circuit chip or a flexible circuit board;
forming a first insulating film on the substrate on which the metal layer is formed;
forming a first transparent electrode layer on the first insulating film and processing the first transparent electrode layer by adopting a high-temperature annealing process;
forming a second insulating film on the substrate on which the first transparent electrode layer is formed;
simultaneously patterning the second insulating film and the first insulating film to form a second insulating layer and a first insulating layer, wherein second through holes for exposing the metal layer are formed in the second insulating layer and the first insulating layer;
wherein the simultaneously patterning the second insulating film and the first insulating film includes:
coating a layer of photoresist on the second insulating film;
exposing and developing the photoresist by using a mask plate, forming a complete exposure area at the second via hole position, having no photoresist, forming an unexposed area at other positions, and keeping the photoresist;
etching the second insulating film and the first insulating film in the complete exposure area by adopting a first isotropic etching process;
and etching the second insulating film and the first insulating film in the complete exposure area by adopting an anisotropic second etching process.
2. The production method according to claim 1, wherein before forming the first transparent electrode layer on the first insulating film, the method further comprises:
and forming a resin layer on the first insulating film, wherein a first through hole is formed in the resin layer, an overlapping part exists between an orthographic projection of the first through hole on the substrate and an orthographic projection of the metal layer on the substrate, and an orthographic projection of the second through hole on the substrate is located in the range of the orthographic projection of the first through hole on the substrate.
3. The production method according to claim 2, wherein before or after the forming of the first transparent electrode layer on the first insulating film, the method further comprises:
and removing the resin residue at the first through hole.
4. The method of claim 3, wherein the resin residue at the first via hole is removed using plasma, and the reaction gas includes at least one of an oxidizing gas and an inert gas.
5. The method as claimed in claim 1, wherein the metal layer comprises copper.
6. The manufacturing method according to claim 1, wherein the process conditions of the first etching process include: the pressure of the chamber is 20 mT-220 mT, the flow of sulfur hexafluoride is 1000 sccm-2000 sccm, the flow of oxygen is 1000 sccm-2000 sccm, and the flow of helium is 2000 sccm-4000 sccm.
7. The manufacturing method according to claim 1, wherein the process conditions of the second etching process include: the pressure of the chamber is 30 mT-230 mT, the flow of sulfur hexafluoride is 1000 sccm-2000 sccm, the flow of oxygen is 1000 sccm-2000 sccm, and the flow of helium is 0-1000 sccm.
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