CN109859714A - A kind of shifting deposit unit, shift register, display device and detection method - Google Patents
A kind of shifting deposit unit, shift register, display device and detection method Download PDFInfo
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Abstract
The present invention provides a kind of shifting deposit unit, the shifting deposit unit includes shifting deposit unit main body and scanning signal output end, the shifting deposit unit further includes test output module, the test output module includes the first test input, test control end, second test input and test signal output end, first test input is electrically connected with the scanning signal output end, the test signal output end of first test input of the test output module and the test output module can receive effective test control signal in the test control end, and second test input conducting when receiving effective clock signal.Shifting deposit unit of the invention can export the scanning signal exported by scanning signal output end by test signal output end, avoid the risk for causing display panel to destroy when removal sealing, while improving the efficiency of fault detection.
Description
Technical field
The present invention relates to field of display technology, and in particular, to a kind of shifting deposit unit, it is a kind of include the shift LD
The shift register of unit, a kind of display device and one kind including the shift register are defeated for detecting the shift register
The detection method of signal out.
Background technique
With the development of display technology, shift-register circuit has become common circuit in liquid crystal display panel.Displacement
Register refers to the circuit formed after the non-display area that the gate driving circuit of display panel is directly integrated in array substrate,
The driving chip that array substrate can be replaced external, has many advantages, such as that at low cost, process is few, production capacity is high, and can effectively reduce aobvious
Show the width of panel border.
However, the scanning signal for working as existing shift register output is when the error occurs, shifting is detected after needing to remove sealing
Whether the corresponding scanning signal of each grid line is abnormal in bit register, and this test method has the risk for destroying display panel, is easy
The waste of goods, materials and equipments is caused, and time-consuming and laborious.
Therefore, how a kind of shift register that can easily detect scanning signal is provided, becomes this field and urgently solves
Certainly the technical issues of.
Summary of the invention
The present invention provides a kind of shifting deposit unit, and the scanning signal of shift register cell output can not remove
It is conveniently detected in the case where sealing.
To achieve the goals above, as one aspect of the present invention, a kind of shifting deposit unit is provided, the displacement is posted
Memory cell includes shifting deposit unit main body and scanning signal output end, wherein the shifting deposit unit further includes that test is defeated
Module out, the test output module include the first test input, test control end, the second test input and test signal
Output end, first test input are electrically connected with the scanning signal output end, and the first of the test output module is surveyed
The test signal output end of examination input terminal and the test output module can receive effective survey in the test control end
Conducting when examination control signal and second test input receive effective clock signal.
Preferably, the test output module includes testing and control submodule, test switch submodule and test output
Module,
The first end of the testing and control submodule is formed as second test input, the testing and control submodule
Second end be formed as the test control end, the third end of the testing and control submodule and the test switch submodule
Control terminal electrical connection, when the second end of the testing and control submodule receives the effective test control signal, the survey
Try the first end of control submodule and the third end conducting of the testing and control submodule；
The first end of the test switch submodule is formed as first test input, and the test switchs submodule
Second end with it is described test output sub-module first end be electrically connected, it is described test switch submodule first end and the survey
The second end of runin sub-module can receive defeated by second test in the control terminal of the test switch submodule
Conducting when entering the effective clock signal of end input；
The first end of the test output sub-module is electrically connected with the second end of the test switch submodule, the test
The second end of output sub-module is formed as the test signal output end, the first end and the survey of the test output sub-module
The second end of examination output sub-module can receive defeated from first test in the first end of the test output sub-module
Conducting when entering the useful signal at end.
Preferably, the testing and control submodule includes testing and control transistor, and the first of the testing and control transistor
Pole is formed as the first end of the testing and control submodule；The grid of the testing and control transistor is formed as the testing and control
The second end of submodule；Second pole of the testing and control transistor is formed as the third end of the testing and control submodule.
Preferably, the test switch submodule includes test switching transistor, and the first of the test switching transistor
Pole is formed as the first end of the test switch submodule；Second pole of the test switching transistor is formed as the test and opens
The second end of sub-module；The grid of the test switching transistor is formed as the control terminal of the test switch submodule.
Preferably, the test output sub-module includes test output transistor, and the first of the test output transistor
Pole is formed as the first end of the test output sub-module；It is defeated that second pole of the test output transistor is formed as the test
The second end of submodule out；The grid of the test output transistor is electrically connected with the first pole of the test output transistor.
Preferably, the shifting deposit unit main body include input module, reseting module, pull-up module, pull-down module and
Pull-down control module；
Wherein, the output end of the input module is electrically connected with the control terminal of the pull-up module；
The input terminal of the pull-up module is electrically connected with the first clock signal terminal, the output end of the pull-up module with it is described
The electrical connection of scanning signal output end, the control for the signal that the pull-up module is used to receive in the control terminal of the pull-up module
Under, control the on state between the input terminal of the pull-up module and the output end of the pull-up module；
The control terminal of the reseting module is electrically connected with reset signal input terminal, the input terminal of the reseting module be used for
The electrical connection of reference level signal line, the output end of the reseting module are connect with the control terminal of the pull-up module, the reset
Module is used under the control of signal that the control terminal of the reseting module receives, control the input terminal of the reseting module with
On state between the output end of the reseting module；
The first input end of the pull-down control module is electrically connected with second clock signal end, the pull-down control module
Second input terminal with the reference level signal line for being electrically connected, the control terminal of the pull-down control module and the lower drawing-die
The control terminal of block is electrically connected, and the output end of the pull-down control module is electrically connected with the control terminal of the pull-up module, under described
The signal that drawing control module is received for the control terminal in the first input end signal received and pull-down control module
Conducting shape between second input terminal of the control lower control pull-down control module and the output end of the pull-down control module
State；
The input terminal of the pull-down module is electrically connected with the reference level signal line, the first output of the pull-down module
End is electrically connected with the control terminal of the pull-up module, the second output terminal of the pull-down module and scanning signal output end electricity
Connection, the pull-down module are used to control the input of the pull-down module in the signal that the control terminal of the pull-down module receives
The input terminal of on state and the pull-down module between end and the first output end of the pull-down module and the drop-down
On state between the second output terminal of module.
As the second aspect of the invention, a kind of shift register is provided, the shift register includes cascade more
Grade shifting deposit unit, wherein the shifting deposit unit is the above-mentioned shifting deposit unit that present specification provides, the shifting
Bit register further includes p-wire and control line, the test signal output end of all shifting deposit units with the test
Line electrical connection, the test control end of all shifting deposit units are electrically connected with the control line；
The shift register further includes the identical clock cable of a plurality of clock signal period, the shifting deposit unit
It further include the first clock signal terminal, the scanning signal output end only can be when first clock signal terminal exports effective
Effective scanning signal is exported when clock signal, stages shift deposit unit is divided into a group, N grades of shifting deposit units and N+
Ka grades of shifting deposit units are same group, and shifting deposit unit in the same set successively cascades, in the same set adjacent two-stage
First clock signal terminal of shifting deposit unit differs the clock cable phase of 1/2 clock signal period with two bars respectively
Even；
Than N grades shifting deposit units of clock signal of the first clock signal terminal input of N+1 grades of shifting deposit units
The clock signal of the first clock signal terminal input lag 1/2a clock signal period, the survey in N grades of shifting deposit units
Second test input of examination output module is electrically connected with the scanning signal output end of N+a-1 grades of shifting deposit units,
Wherein, a, k, N are positive integer.
Preferably, stages shift deposit unit is divided into 3 groups, N grades of shifting deposit units and N+3k grades of shift LDs
Unit is same group, than N grades shift LDs of clock signal of the first clock signal terminal input of N+1 grades of shifting deposit units
The clock signal of the first clock signal terminal input of unit lags 1/6 clock signal period, in N grades of shifting deposit units
Second test input of test output module is electrically connected with the scanning signal output end of N+2 grades of shifting deposit units.
As the third aspect of the invention, a kind of display device, including shift register and display panel are provided, it is described
Display panel includes a plurality of grid line, and a plurality of grid line is electrically connected with multiple scanning signal output ends of displacement shift register respectively,
Wherein, the shift register is above-mentioned shift register provided by the present invention.
As the fourth aspect of the invention, a kind of detection method of shift register is provided, wherein the detection method
For detecting the scanning signal of above-mentioned shift register output provided by the present invention, the detection method includes:
Effective test control signal is provided to the control line；
Receive the test signal that the p-wire receives；
Successively judge whether the test signal in every 1/2a clock signal period exception occurs, if there is exception, sentences
The fixed corresponding shifting deposit unit failure of the 1/2a clock signal period.
Detailed description of the invention
The drawings are intended to provide a further understanding of the invention, and constitutes part of specification, with following tool
Body embodiment is used to explain the present invention together, but is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the structural schematic diagram of shifting deposit unit provided by the invention；
Fig. 2 is each module connection relationship diagram of the test output module of the shifting deposit unit in Fig. 1；
Fig. 3 is a kind of schematic diagram of physical circuit of each module in Fig. 2；
Fig. 4 is a kind of schematic diagram of physical circuit of the shifting deposit unit in Fig. 1；
Fig. 5 is a kind of embodiment schematic diagram of shift register provided by the invention；
Fig. 6 is the timing diagram of each port of shift register in Fig. 5；
Fig. 7 is the timing diagram of each port in the embodiment of second of shift register provided by the invention；
Fig. 8 is the timing diagram of each port in the embodiment of the third shift register provided by the invention；
Fig. 9 is the program chart of shift register detection method provided by the invention.
Description of symbols
100: shifting deposit unit 110: shifting deposit unit main body
111: input module 112: reseting module
113: pull-up module 114: pull-down module
115: pull-down control module 116: shutdown module
120: test output module 121: test switch submodule
122: testing and control submodule 123: test output sub-module
GOUT: scanning signal output end EN: test control end
RESET1: the second test input TEST: test signal output end
INPUT: the CLK: the first clock signal terminal of input terminal
CLKB: second clock signal end RESET: reset signal input terminal
GCL: cut-off signals end VSS: reference level signal line
STV: initial signal line PU: the control terminal of pull-up module
PD: the control terminal M1 of pull-down module: test switching transistor
M2: testing and control transistor M3: test output transistor
M4: input transistors M5: reset transistor
M6: pull up transistor the M7: the first drop-down control transistor
M8: the second drop-down control transistor M9: third drop-down control transistor
M10: the four drop-down control the M11: the first pull-down transistor of transistor
M12: the second pull-down transistor C1: storage capacitance
PD_CN: drop-down the CLK1: the first clock cable of control node
CLK2: second clock signal wire CLK3: third clock cable
CLK4: the four the CLK5: the five clock cable of clock cable
CLK6: the six clock cable
Specific embodiment
Below in conjunction with attached drawing, detailed description of the preferred embodiments.It should be understood that this place is retouched
The specific embodiment stated is merely to illustrate and explain the present invention, and is not intended to restrict the invention.
In the prior art, the scanning signal of shift register output when the error occurs, detects shifting after needing to remove sealing
Whether the corresponding scanning signal of each grid line is abnormal in bit register, and this test method has the risk for destroying display panel, is easy
Cause the waste of goods, materials and equipments, and inefficiency.
In order to solve the above technical problems, the present invention provides a kind of shifting deposit unit 100, as shown in Figure 1, shift LD list
Member 100 includes shifting deposit unit main body 110, scanning signal output end GOUT and test output module 120.Wherein, it tests defeated
Module 120 includes the first test input, test control end EN, the second test input RESET1 and test signal output end out
TEST.First test input is electrically connected with scanning signal output end GOUT, and the first test of test output module 120 is defeated
The test signal output end TEST for entering end and test output module 120 can receive effective test control in test control end EN
Conducting when signal processed and the second test input RESET1 receive effective clock signal.
In the present invention, the first test input for testing output module 120 is electrically connected with scanning signal output end GOUT,
When test control end EN receives effective test control signal, (in the present invention, useful signal, which refers to, enables to crystal
The signal of the emitter and collector conducting of pipe, for example, useful signal is high level signal when transistor is P-type transistor,
When transistor is N-type transistor, useful signal is low level signal), and the second test input RESET1 has been received
When the clock signal of effect, test signal output end TEST is connected with first test input, so as to pass through test letter
Number output end TEST easily detects the scanning signal of the scanning signal output end GOUT output of shifting deposit unit 100, avoids
The risk for causing display panel to destroy when removal sealing.
Also, it in the present invention, is not only provided with the test control end EN for controlling test mode, is also set up for connecing
Second test input RESET1 of time receiving sequential signal allows test signal output end TEST in the second test input
RESET1 input specific clock signal (such as specific clock signal or other shifting deposit units output scanning letter
Number) export the scanning signal of the shifting deposit unit under control, so as to so that test signal by test signal output end
Signal processing is first carried out before TEST output, makes test signal be easier to analyze, fault detection is more convenient.
It is easily understood that " signal processing " refers to: test signal output end TEST being made only to export detection failure institute
The signal needed.For example, in a shift register, the scanning signal of each shifting deposit unit output is abnormal (for example, film is brilliant
Channel foreign matter, the film thickness that body pipe is destroyed when Electro-static Driven Comb occurs or occurs in the production process are abnormal.These abnormal meetings
Cause gate driving circuit to occur reliability problem after normal use, normal scanning signal can not be exported) when, usually scan
The scanning signal of the significant level of signal output end GOUT output can terminate in advance, and only need to detect the scanning signal at this time defeated
The signal of outlet GOUT final stage time output in the time of predetermined output significant level, it is not necessary to by GOUT predetermined
The whole signals exported in the time of significant level are exported to export as test signal.The present invention utilizes the second test input
RESET1 receives clock signal, to control period (i.e. the second test input that test output sub-module 123 only exports needs
RESET1 is the period of significant level, for example, when only needing to detect that scanning signal output end GOUT in predetermined output effectively electricity
When the signal that the final stage time exports in the flat time, the second test input RESET1 is set only at this " when final stage
Between " be significant level) in scanning signal make to test signal and be easier to analyze so as to complete above-mentioned " signal processing ", failure
It detects more convenient.
The present invention is not especially limited the structure of test output module 120, as a preferred embodiment, as schemed
Shown in 2, test output module 120 includes testing and control submodule 122, test switch submodule 121 and test output sub-module
123, in which:
The first end of testing and control submodule 122 is formed as the second test input RESET1, testing and control submodule 122
Second end be formed as test control end EN, the third end of testing and control submodule 122 and the control of test switch submodule 121
End electrical connection, when the second end of testing and control submodule 122 receives effective test control signal, testing and control submodule
122 first end and the third end conducting of testing and control submodule 122；
The first end of test switch submodule 121 is formed as first test input, test switch submodule 121
Second end is electrically connected with the first end of test output sub-module 123, the first end and test switch of test switch submodule 121
The second end of module 121 can be received in the control terminal of test switch submodule 121 through the second test input RESET1
It is connected when the effective clock signal of input；
The first end for testing output sub-module 123 is electrically connected with the second end of test switch submodule 121, test output
The second end of module 123 is formed as testing signal output end TEST, tests the first end and test output of output sub-module 123
The second end of module 123 can be received in the first end of test output sub-module 123 from first test input
It is connected when useful signal.
In the present invention, it is not only provided with test output sub-module 123 for exporting scanning signal, is additionally provided with by the
The test of two test input RESET1 clock signals control switchs submodule 121, so that test signal output end TEST can be with
In specific clock signal (such as specific clock signal or other shift LD lists of the second test input RESET1 input
The scanning signal of member output) export the scanning signal of the shifting deposit unit under control, so as to so that test signal by surveying
Signal processing is first carried out before trial signal output end TEST output, obtains more efficiently testing signal, holds that test signal more
Easily analysis, fault detection are more convenient.
In addition, the present invention is also provided with the testing and control submodule 122 of tested person control terminal EN control, in test control end
Under the test control signal control of EN input, shifting deposit unit 100 can be convenient ground switch test state.When testing and control is believed
Number be significant level when, by signal processing test signal by test signal output end TEST export；Work as test control signal
When for inactive level, test signal output end TEST can not output signal.
The present invention is not especially limited the structure of testing and control submodule 122, as a preferred embodiment, such as
Shown in Fig. 3, testing and control submodule 122 includes testing and control transistor M2, and the first pole of testing and control transistor M2 is formed as
The first end of testing and control submodule 122；The grid of testing and control transistor M2 is formed as the second of testing and control submodule 122
End；The second pole of testing and control transistor M2 is formed as the third end of testing and control submodule 122.
The present invention, which only passes through a testing and control transistor T2, can be realized the testing and control inputted by test control end EN
The signal processing and output control of signal and the clock signal control test signal of the second test input RESET1 input, simplify
The circuit structure of test output module 120.
The present invention is not especially limited the structure of test switch submodule 121, as a preferred embodiment, such as
Shown in Fig. 3, test switch submodule 121 includes test switching transistor M1, and the first pole of test switching transistor M1 is formed as
The first end of test switch submodule 121；The second pole of test switching transistor M1 is formed as the of test switch submodule 121
Two ends；The grid of test switching transistor M1 is formed as the control terminal of test switch submodule 121.
The present invention is not especially limited the structure of test output sub-module 123, as a preferred embodiment, such as
Shown in Fig. 3, test output sub-module 123 includes test output transistor M3, and the first pole of test output transistor M3 is formed as
Test the first end of output sub-module 123；The second pole of test output transistor M3 is formed as testing the of output sub-module 123
Two ends；The grid for testing output transistor M3 is electrically connected with the first pole of test output transistor M3.
The present invention passes through the test output transistor T3 that grid is electrically connected with itself the first pole, so that test signal is by scanning
Signal output end GOUT avoids test signal output end TEST to scanning signal to test signal output end TEST one-way conduction
Interference.
The present invention is not especially limited the structure of shifting deposit unit main body 110, as an alternative embodiment,
As shown in figure 4, shifting deposit unit main body 110 may include input module 111, reseting module 112, pull-up module 113, drop-down
Module 114 and pull-down control module 115, in which:
The output end of input module 111 is electrically connected with the control terminal PU of pull-up module, for what is inputted in input terminal INPUT
The current potential of the control terminal PU of pull-up module is adjusted to the current potential of the input signal under the control of input signal.
The input terminal of pull-up module 113 is electrically connected with the first clock signal terminal CLK, the output end of pull-up module 113 with sweep
Signal output end GOUT electrical connection is retouched, pull-up module 113 is used for the control in the control terminal PU of the pull-up module signal received
Under, control the on state between the input terminal of pull-up module 113 and the output end of pull-up module 113.
The control terminal of reseting module 112 is electrically connected with reset signal input terminal RESET, and the input terminal of reseting module 112 is used
It is connect in reference level signal line electricity VSS, the output end of reseting module 112 is connect with the control terminal of pull-up module 113, is resetted
Module 112 is used under the control for the signal that the control terminal of reseting module 112 receives, and controls the input terminal of reseting module 112
On state between the output end of reseting module 112.
The first input end of pull-down control module 115 is electrically connected with second clock signal end CLKB, pull-down control module 115
The second input terminal for being electrically connected with reference level signal line VSS, the control terminal of pull-down control module 115 and pull-down module
Control terminal PD electrical connection, the output end of pull-down control module 115 are electrically connected with the control terminal PU of pull-up module.Pull-down control module
115 control terminal for the first input end signal received and pull-down control module 115 in pull-down control module 115
The second input terminal of pull-down control module 115 and the output end of pull-down control module 115 are controlled under the control of the signal received
Between on state.
The input terminal of pull-down module 114 is electrically connected with reference level signal line VSS, the first output end of pull-down module 114
It is electrically connected with the control terminal PU of pull-up module 113, second output terminal and the scanning signal output end GOUT of pull-down module 114 are electrically connected
It connects, pull-down module 114 is used for the input terminal in the control terminal PD of the pull-down module 114 signal control pull-down module 114 received
114 input terminals of on state and pull-down module between the first output end of pull-down module 114 and pull-down module 114
On state between second output terminal.
It should be noted that second clock signal end CLK is exported under normal circumstances the first clock signal and second clock
The second clock signal frequency of signal end CLKB output is identical and differs half period.
For the combination for being easy to implement display function and touch function, avoid the signal between touch panel and display panel dry
It disturbs, it is preferable that as shown in figure 4, shifting deposit unit main body 110 further includes shutdown module 116, the shutdown module and signal are defeated
Outlet GOUT, reference level signal line VSS are connected with cut-off signals end GCL, for providing significant level in cut-off signals end GCL
Control signal output GOUT is connected with reference level signal line VSS when signal.It can be readily appreciated that working as shifting deposit unit master
When body 110 includes shutdown module 116, reference level signal line VSS provides the inactive level for closing thin film transistor (TFT), in touch-control
During scanning, cut-off signals end GCL receives significant level signal, and making the level of all signal output end GOUT is with reference to electricity
The inactive level of flat signal wire VSS interferes so as to avoid scanning signal of the touch panel to display panel.
In the present invention, special restriction is not done to the specific structure of input module 111.In Fig. 4, input module 111
Including input transistors M4, the grid of input transistors M4 is electrically connected with the first pole of input transistors M4, and is formed as defeated
Enter the input terminal of module 111, the second pole of input transistors M4 is formed as the output end of input module 111.Shown in Fig. 4
In embodiment, input transistors M4 is N-type transistor, when the input terminal INPUT input high level signal of input module 111
When, the first pole of input transistors M4 and the second pole of input transistors M4 are connected.
In the present invention, there is no special restriction to the specific structure of reseting module 112, the embodiment party shown in Fig. 4
Formula, reseting module 112 include reset transistor M5, and the grid of reset transistor M5 is formed as the control terminal of reseting module 112, multiple
The first pole of bit transistor M5 is formed as the input terminal of reseting module 112, and the second pole of reset transistor M5 is formed as resetting mould
The output end of block 112.In the embodiment shown in Fig. 4, reset transistor M5 is N-type transistor, when reseting module 112
When control terminal RESET receives high level signal, the first pole of reset transistor M5 and the second pole conducting of reset transistor M5.
In the present invention, there is no special restriction to the specific structure of pull-up module 113, the embodiment party shown in Fig. 4
In formula, pull-up module 113 include pull up transistor M6 and storage capacitance C1, as shown, the grid for the M6 that pulls up transistor with deposit
Storage holds the first end electrical connection of C1, and is formed as the control terminal of pull-up module 113, and the first pole for the M6 that pulls up transistor is formed
For the input terminal of pull-up module 113, the second pole for the M6 that pulls up transistor is electrically connected with the second end of storage capacitance C1, and is formed as
The output end of pull-up module 113.It is easily understood that the output end of pull-up module 113 is electrically connected with signal output end GOUT.?
In embodiment shown in Fig. 4, the M6 that pulls up transistor is N-type transistor, when the grid for the M6 that pulls up transistor receives high electricity
When ordinary mail, the first pole for the M6 that pulls up transistor and the conducting of the second pole.
In the present invention, special restriction is not done to the specific structure of pull-down module 114.The embodiment party shown in Fig. 4
In formula, pull-down module 114 includes the first pull-down transistor M11 and the second pull-down transistor M12, as shown in the figure, the first drop-down
The electrical connection of the grid of transistor M11 and the second pull-down transistor M12, and be formed as the control terminal of pull-down module 114, the first drop-down
The first pole of transistor M11 is electrically connected with the first pole of the second pull-down transistor M12, and is formed as the defeated of pull-down module 114
Enter end, the second pole of the first pull-down transistor M11 is formed as the first output end of pull-down module 114, the first pull-down transistor M12
The second pole be formed as the second output terminal of pull-down module 114.In Fig. 4, the lower crystal pulling of the first pull-down transistor M11 and second
Pipe M12 is N-type transistor.
In the present invention, the specific structure of pull-down control module 115 does not do special restriction, for example, shown in Fig. 4
In embodiment, pull-down control module 115 includes the first drop-down control transistor M7, the second drop-down control transistor M8, third
The drop-down drop-down control of control transistor M9 and the 4th transistor M10.
As shown in the figure, the grid of the first drop-down control transistor M7 and the first drop-down control transistor M7's is first extremely electric
Connection, and be formed as first input end, the grid of the second pole of the first pull-down transistor M7 and the second drop-down control transistor M8
Pole electrical connection is formed as pulling down control node PD_CN, and the first pole of the second drop-down control transistor M8 and the first drop-down control are brilliant
The first pole of body pipe M7 is electrically connected, and the second pole of the second drop-down control transistor M8 is formed as the first of pull-down control module 115
The grid of output end, third drop-down control transistor M9 is electrically connected with the control terminal PU of pull-up module, third drop-down control crystal
The first pole of pipe M9 is electrically connected with drop-down control node PD_CN, and the second pole of third drop-down control transistor M9 is formed as pulling down
Second input terminal of control module 115, the grid of the 4th drop-down control transistor M10 and the control terminal PU of pull-up module are electrically connected
It connects, the first pole of the 4th drop-down control transistor M10 is electrically connected with the control terminal PD of pull-down module, the 4th drop-down control transistor
The second pole for pulling down control transistor M9 with third of M10 is electrically connected.
As the second aspect of the invention, a kind of shift register is also provided, the shift register includes cascade
Stages shift deposit unit, the shifting deposit unit are mentioned-above shifting deposit unit 100, and the shift register is also
Including p-wire and control line, the test signal output end TEST of all shifting deposit units 100 is electrically connected with the p-wire
It connects, the test control end EN of all shifting deposit units 100 is electrically connected with the control line；
The shift register further includes the identical clock cable of a plurality of clock signal period, shifting deposit unit 100
It further include the first clock signal terminal, scanning signal output end GOUT only can export effective clock letter in the first clock signal terminal
Number when export effective scanning signal, stages shift deposit unit 100 is divided into a group, N grades of shifting deposit units 100 and N
+ ka grades of shifting deposit units 100 are same group, and shifting deposit unit 100 in the same set successively cascades, in the same set phase
First clock signal terminal of adjacent two-stage shifting deposit unit 100 differed respectively with two bars 1/2 clock signal period when
Clock signal wire is connected；
Than N grades shift LD lists of clock signal of the first clock signal terminal input of N+1 grades of shifting deposit units 100
The clock signal of the first clock signal terminal input of member 100 lags 1/2a clock signal period, N grades of shifting deposit units
The scanning of second test input RESET1 and N+a-1 grades of shifting deposit units 100 of the test output module 120 in 100
Signal output end GOUT electrical connection, wherein a, k, N are positive integer.
The main part of the shifting deposit unit 100 can be mentioned-above shifting deposit unit main body 110, same
In shifting deposit unit main body 110, the first clock signal and second clock signal differ 1/2 period.Stages shift storage receipt
When member 100 is divided into a group, the clock signal of adjacent two-stage shifting deposit unit differs 1/2a clock signal period.Therefore, only
The clock cable for needing 2a clock signal to differ 1/2a clock signal period can meet the shift register timing control
Normal need.
Shifting deposit unit 100 in same group successively cascades, specific to referring in shifting deposit unit main body 110: N
Reset signal input terminal RESET in the shifting deposit unit main body 110 of grade shifting deposit unit 100 is posted with N+a grades of displacements
The signal output end GOUT of the shifting deposit unit main body 110 of memory cell 100 is connected (hereinafter referred to as " GOUT of N+a is cascaded "),
When N+a grades of shifting deposit units 100 export effective scanning signal, the scanning that N grades of shifting deposit units 100 export is believed
Number it is placed in inactive level.In the case, the scanning signal for adjacent two-stage shifting deposit unit 100 output not being grouped is in timing
On there are overlapped, can not can successively in different times as the adjacent two-stage shifting deposit unit 100 in same group
Section output scanning signal.At this point, if the signal output end GOUT of different shifting deposit units 100 is connected to same test
On line, then what is observed is overlapped scanning signal, can not be used to judge whether scanning signal is wrong.
And the present invention uses the above-mentioned shifting deposit unit 100 including test output module 120 to form shift register, and
And in the GOUT cascade that reset signal input terminal RESET is N+a, make the second test input for testing output module 120
GOUT cascade (the second test input RESET1 of i.e. N grades shifting deposit units and N+a-1 grades that RESET1 is N+a-1
The scanning signal output end GOUT connection of shifting deposit unit), thus only in N+a-1 grades of shifting deposit unit outputs effectively letter
Number when by the scanning signal output end GOUT of N grades of shifting deposit units with test signal output end TEST be connected.Due to N+
The scanning signal of a-1 grades of shifting deposit units output is only significant level in the scanning signal of N grades of shifting deposit units output
Last 1/2a clock signal period in be significant level, therefore, the test signal finally by N grades of shifting deposit units is defeated
The test signal of outlet TEST output will not be the scanning signal of the entire significant level of N grades of shifting deposit units output, and
It is the part in the last 1/2a clock signal period of its significant level scanning signal.
And test output module 120 is arranged in the GOUT cascade that reset signal input terminal RESET is N+a in the present invention
The GOUT that second test input RESET1 is N+a-1 is cascaded, so that every grade of test signal output end TEST be made only to export the grade
Last 1/2a clock signal period of the scanning signal output end GOUT in half of clock cycle of predetermined output significant level
Interior part (completing mentioned-above signal processing).At this point, the test signal of every level-one shifting deposit unit 100 exports
The test signal of end TEST output is respectively positioned in individual 1/2a clock signal period, and there is no overlappings mutually, thus convenient
The analysis of test signal, and then improve fault detection efficiency.Also, due to the survey of adjacent two-stage shifting deposit unit 100
The test signal of trial signal output end TEST output is not present mutually overlapping, it is multistage test signal output end TEST can connect to
Same p-wire exports the test signal by same p-wire, thus route number needed for reducing data output
Amount, and then the border width of the whole display device using the shift register can be reduced.
In order to facilitate the understanding of those skilled in the art, a kind of specific embodiment when present invention offer a=3, such as Fig. 5, Fig. 6 institute
Show, stages shift deposit unit 100 is divided into 3 groups, N grades of shifting deposit units 100 and N+3k grades of shifting deposit units 100
It is same group, than N grades shift LDs of clock signal of the first clock signal terminal input of N+1 grades of shifting deposit units 100
The clock signal of the first clock signal terminal input of unit 100 lags 1/6 clock signal period, N grades of shifting deposit units
The scanning of the second test input RESET1 and N+2 grades of shifting deposit units 100 of test output module 120 in 100 are believed
Number output end GOUT electrical connection.
As shown in figure 5, the scanning signal output end GOUT of the 1st grade of shifting deposit unit 100 connects the 1st article of grid line GOUT1,
The scanning signal output end GOUT of 2nd grade of shifting deposit unit 100 connects N grades of shift LDs of the 2nd article of grid line GOUT2 ... ...
The N articles grid line GOUTN of scanning signal output end GOUT connection of unit 100.Stages shift deposit unit 100 is divided into 3 groups,
In, the 1st grade, the 4th grade, the 7th grade ... N-2 grades of shifting deposit units 100 are first group, the 2nd grade, the 5th grade, the 8th
Grade ... N-1 grade shifting deposit units 100 are second group, 3rd level, the 6th grade, the 9th grade ... N grades of shifting deposit units
100 be third group.The period of clock signal on first clock cable CLK1 to the 6th clock cable CLK6 is identical, and presses
Clock signal ratio according to the sequence of the first clock cable CLK1 to the 6th clock cable CLK6, on latter clock cable
Clock signal on previous clock cable lags 1/6 clock signal period.The first of first group of shifting deposit unit 100
Clock signal terminal CLK is connected with the first clock cable CLK1, the second clock signal end of first group of shifting deposit unit 100
CLKB is connected with the 4th clock cable CLK4；When the first clock signal terminal CLK and second of second group of shifting deposit unit 100
Clock signal wire CLK2 is connected, the second clock signal end CLKB and the 5th clock cable of second group of shifting deposit unit 100
CLK5 is connected；First clock signal terminal CLK of third group shifting deposit unit 100 is connected with third clock cable CLK3, the
The second clock signal end CLKB of three groups of shifting deposit units 100 is connected with the 6th clock cable CLK6.
The present embodiment uses the above-mentioned shifting deposit unit 100 including test output module 120 to form shift register, and
And in the GOUT cascade that reset signal input terminal RESET is N+3, make the second test input for testing output module 120
The GOUT that RESET1 is N+2 is cascaded, thus only in N+2 grades of (by taking GOUT4 in Fig. 6 as an example) shifting deposit unit outputs effectively letter
Number when by the scanning signal output end GOUT of N grades of (by taking GOUT2 in Fig. 6 as an example) shifting deposit units and test signal output end
TEST conducting.
Since the scanning signal of N+2 grades of (GOUT4) shifting deposit units output is only in N grades of (GOUT2) shift LDs
Unit output scanning signal be significant level last 1/6 clock signal period T in be significant level, therefore, finally by
The test signal of the test signal output end TEST output of N grades of (GOUT2) shifting deposit units will not be N grades (GOUT2)
The scanning signal of the entire significant level of shifting deposit unit output, but at last 1/6 of its significant level scanning signal
Part (i.e. second high level period of TEST signal in Fig. 6) in clock signal period T.
In the present embodiment, the test signal of the test signal output end TEST output of every level-one shifting deposit unit 100
It is respectively positioned in individual 1/6 clock signal period T, there is no overlappings mutually, to facilitate the analysis of test signal, in turn
Improve fault detection efficiency.Also, multistage test signal output end TEST can be exported by same p-wire, reduce number
According to number of, lines needed for output, and then the border width of the whole display device using the shift register can be reduced.
It should be pointed out that significant level is high level signal in the specific embodiment shown in Fig. 6.
Meanwhile the present invention also provides the timing of signal end each when a=2, a=4 in order to facilitate the understanding of those skilled in the art,
Figure:
As shown in fig. 7, the GOUT that reset signal input terminal RESET is N+2 is cascaded as a=2, output module 120 is tested
The second test input RESET1 be N+1 GOUT cascade.Being exported due to N+1 grades of (such as GOUT3) shifting deposit units
Scanning signal is only in last 1/4 clock that the scanning signal of N grades of (such as GOUT2) shifting deposit units output is significant level
It is significant level in signal period T, therefore, finally by the test signal output end TEST of N grades of (GOUT2) shifting deposit units
The test signal of output will not be the scanning signal of the entire significant level of N grades of (GOUT2) shifting deposit units output, but
Part (i.e. second height of TEST signal in Fig. 7 in last 1/4 clock signal period T of its significant level scanning signal
Level period)；
As shown in figure 8, the GOUT that reset signal input terminal RESET is N+4 is cascaded as a=4, output module 120 is tested
The second test input RESET1 be N+3 GOUT cascade.Being exported due to N+3 grades of (such as GOUT5) shifting deposit units
Scanning signal is only in last 1/8 clock that the scanning signal of N grades of (such as GOUT2) shifting deposit units output is significant level
It is significant level in signal period T, therefore, finally by the test signal output end TEST of N grades of (GOUT2) shifting deposit units
The test signal of output will not be the scanning signal of the entire significant level of N grades of (GOUT2) shifting deposit units output, but
Part (i.e. second height of TEST signal in Fig. 8 in last 1/8 clock signal period T of its significant level scanning signal
Level period).
It should be pointed out that significant level is high level signal in specific embodiment shown in figures 7 and 8.
It is easily understood that the present invention is to the company between the shifting deposit unit main body 110 of shifting deposit units 100 at different levels
The relationship of connecing is not especially limited, those skilled in the art when the a=3 provided in attached drawing 5 of the invention is provided it is at different levels displacement post
Connection relationship between memory cell 100 voluntarily adjusts.Between the shifting deposit unit main body 110 provided in attached drawing 5 of the invention
Connection relationship only play illustration, the solution of the present invention can not be limited.
The present invention does not make to how the input terminal INPUT of preceding a grades of shifting deposit units 100 of the shift register connects
It is specific to limit, as long as can guarantee the normal scan function of the shift register.For example, as shown in Figure 5, it is preferable that
The shift register further includes initial signal line STV, the input of preceding a grades of shifting deposit units 100 of the shift register
End INPUT is connected with initial signal line STV, and initial signal line STV is used for when the shift register starts progressive scan
The input terminal INPUT of a grades of shifting deposit units 100 provides significant level forward.
As the third aspect of the invention, a kind of display device is also provided, the display device includes shift register
And display panel, the display panel include a plurality of grid line, a plurality of grid line is more with the displacement shift register respectively
A scanning signal output end electrical connection, the shift register are mentioned-above shift register.
It includes the shift register testing the above-mentioned shifting deposit unit 100 of output module 120 and forming that the present invention, which uses,
When the GOUT cascade that reset signal input terminal RESET is N+a, make the second test input RESET1 for testing output module 120
It is cascaded for the GOUT of N+a-1, thus only when N+a-1 grades of shifting deposit units export useful signal by N grades of shift LDs
The scanning signal output end GOUT of unit is connected with test signal output end TEST, to make every grade of test signal output end TEST
When only exporting last 1/2a of this grade of scanning signal output end GOUT in half of clock cycle of predetermined output significant level
Part in the clock signal period.
The test signal of the test signal output end TEST output of every level-one shifting deposit unit 100 is respectively positioned on individual 1/
In 2a clock signal period, there is no overlappings mutually, to facilitate the analysis of test signal, and then improve fault detection
Efficiency.Also, multistage test signal output end TEST can be exported by same p-wire, line needed for reducing data output
Number amount, and then the border width of the display device can be reduced.
As the fourth aspect of the invention, a kind of detection method of shift register is also provided, the detection method is used
In the scanning signal for detecting mentioned-above shift register output, as shown in figure 9, the detection method includes:
In step sl, effective test control signal is provided to control line；
In step s 2, test signal is received by p-wire；
In step s3, successively judge whether the test signal in every 1/2a clock signal period exception occurs, if going out
It is now abnormal, then determine the corresponding shifting deposit unit failure of the 1/2a clock signal period.
It should be pointed out that in the detection method of shift register provided by the invention, " test abnormal signal " can be with
It include: that the peak value of the test signal is not up to predetermined level value and (can make corresponding crystal in corresponding pixel unit
Pipe open level value), it is described test signal the predetermined level duration and proper testing signal predetermined level continue when
Between (for example, in Fig. 6 to 8 test signal output end TEST output test signal be high level duration) inconsistent, institute
The changed timing of level of test signal and the changed timing of level of proper testing signal are stated (for example, Fig. 6 to 8
When the test signal of middle test signal output end TEST output is upgraded to high level by low level or is reduced to low level by high level
Sequence) it is inconsistent situations such as.
It includes the shift register testing the above-mentioned shifting deposit unit 100 of output module 120 and forming that the present invention, which uses,.Often
The test signal of the test signal output end TEST output of level-one shifting deposit unit 100 is respectively positioned on individual 1/2a clock letter
In number period, there is no overlappings mutually, thus when signal is tested in detection, it is only necessary to carry out to the signal on same p-wire
Detection, successively judges whether the test signal in every 1/2a clock signal period exception occurs, if there is exception, can sentence
The fixed corresponding shifting deposit unit failure of the 1/2a clock signal period.Detection method provided by the invention is easy to operate, easy
In realization, the fault detection efficiency of shift register is improved.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, essence of the invention is not being departed from
In the case where mind and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (10)
1. a kind of shifting deposit unit, the shifting deposit unit includes shifting deposit unit main body and scanning signal output end,
It is characterized in that, the shifting deposit unit further includes test output module, the test output module includes that the first test is defeated
Enter end, test control end, the second test input and test signal output end, first test input and the scanning are believed
The test signal of the electrical connection of number output end, the first test input of the test output module and the test output module is defeated
Outlet can receive effective test control signal in the test control end and second test input receives
It is connected when effective clock signal.
2. shifting deposit unit according to claim 1, which is characterized in that the test output module includes testing and control
Submodule, test switch submodule and test output sub-module,
The first end of the testing and control submodule is formed as second test input, and the of the testing and control submodule
Two ends are formed as the test control end, the control at the third end of the testing and control submodule and the test switch submodule
End electrical connection, when the second end of the testing and control submodule receives the effective test control signal, the test control
The conducting of the third end of the first end of system module and the testing and control submodule；
The first end of the test switch submodule is formed as first test input, and the of the test switch submodule
Two ends are electrically connected with the first end of the test output sub-module, and the first end of the test switch submodule and the test are opened
The second end of sub-module can be received in the control terminal of the test switch submodule through second test input
It is connected when the effective clock signal of input；
The first end of the test output sub-module is electrically connected with the second end of the test switch submodule, the test output
The second end of submodule is formed as the test signal output end, and the first end of the test output sub-module and the test are defeated
The second end of submodule can be received in the first end of the test output sub-module from first test input out
Useful signal when be connected.
3. shifting deposit unit according to claim 2, which is characterized in that the testing and control submodule includes test control
Transistor processed, the first pole of the testing and control transistor are formed as the first end of the testing and control submodule；The test
The grid of control transistor is formed as the second end of the testing and control submodule；The diarcs of the testing and control transistor
Third end as the testing and control submodule.
4. shifting deposit unit according to claim 2, which is characterized in that the test switch submodule includes that test is opened
Transistor is closed, the first pole of the test switching transistor is formed as the first end of the test switch submodule；The test
Second pole of switching transistor is formed as the second end of the test switch submodule；The grid shape of the test switching transistor
Control terminal as the test switch submodule.
5. shifting deposit unit according to claim 2, which is characterized in that the test output sub-module includes that test is defeated
Transistor out, the first pole of the test output transistor are formed as the first end of the test output sub-module；The test
Second pole of output transistor is formed as the second end of the test output sub-module；It is described test output transistor grid with
The first pole electrical connection of the test output transistor.
6. shift register cell as claimed in any of claims 1 to 5, which is characterized in that the shift LD
Unit main body includes input module, reseting module, pull-up module, pull-down module and pull-down control module；
Wherein, the output end of the input module is electrically connected with the control terminal of the pull-up module；
The input terminal of the pull-up module is electrically connected with the first clock signal terminal, the output end of the pull-up module and the scanning
Signal output end electrical connection, the pull-up module are used under the control for the signal that the control terminal of the pull-up module receives,
Control the on state between the input terminal of the pull-up module and the output end of the pull-up module；
The control terminal of the reseting module is electrically connected with reset signal input terminal, and the input terminal of the reseting module is used for and reference
The electrical connection of level signal line, the output end of the reseting module are connect with the control terminal of the pull-up module, the reseting module
For under the control for the signal that the control terminal of the reseting module receives, control the input terminal of the reseting module with it is described
On state between the output end of reseting module；
The first input end of the pull-down control module is electrically connected with second clock signal end, and the second of the pull-down control module
Input terminal with the reference level signal line for being electrically connected, the control terminal of the pull-down control module and the pull-down module
Control terminal electrical connection, the output end of the pull-down control module are electrically connected with the control terminal of the pull-up module, the drop-down control
The control for the signal that molding block is used to receive in the control terminal of the first input end signal received and pull-down control module
On state between second input terminal of the lower control pull-down control module and the output end of the pull-down control module；
The input terminal of the pull-down module is electrically connected with the reference level signal line, the first output end of the pull-down module with
The control terminal of the pull-up module is electrically connected, and the second output terminal of the pull-down module is electrically connected with the scanning signal output end
It connects, the pull-down module is used to control the input terminal of the pull-down module in the signal that the control terminal of the pull-down module receives
The input terminal of on state and the pull-down module between the first output end of the pull-down module and the lower drawing-die
On state between the second output terminal of block.
7. a kind of shift register, the shift register includes cascade stages shift deposit unit, which is characterized in that described
Shifting deposit unit is shifting deposit unit described in any one of claim 1 to 6, and the shift register further includes surveying
Examination line and control line, the test signal output end of all shifting deposit units are electrically connected with the p-wire, Suo Yousuo
The test control end for stating shifting deposit unit is electrically connected with the control line；
The shift register further includes the identical clock cable of a plurality of clock signal period, and the shifting deposit unit also wraps
The first clock signal terminal is included, the scanning signal output end only can export effective clock letter in first clock signal terminal
Number when export effective scanning signal, stages shift deposit unit is divided into a group, N grades of shifting deposit units and N+ka grades
Shifting deposit unit is same group, and shifting deposit unit in the same set successively cascades, in the same set adjacent two-stage displacement
The clock cable that first clock signal terminal of deposit unit differs 1/2 clock signal period with two bars respectively is connected；
The of the clock signal of the first clock signal terminal input of N+1 grades of shifting deposit units than N grades of shifting deposit units
The clock signal of one clock signal terminal input lags 1/2a clock signal period, and the test in N grades of shifting deposit units is defeated
The second test input of module is electrically connected with the scanning signal output end of N+a-1 grades of shifting deposit units out,
Wherein, a, k, N are positive integer.
8. shift register according to claim 7, which is characterized in that stages shift deposit unit is divided into 3 groups, N
Grade shifting deposit unit and N+3k grades of shifting deposit units are same group, the first clock letter of N+1 grades of shifting deposit units
Clock signal lag 1/6 of the clock signal of number end input than the first clock signal terminal input of N grade shifting deposit units
Second test input of clock signal period, the test output module in N grades of shifting deposit units is posted with N+2 grades of displacements
The scanning signal output end of memory cell is electrically connected.
9. a kind of display device, including shift register and display panel, the display panel includes a plurality of grid line, a plurality of grid line
It is electrically connected respectively with multiple scanning signal output ends of displacement shift register, which is characterized in that the shift register is power
Benefit require 7 or 8 described in shift register.
10. a kind of detection method of shift register, which is characterized in that the detection method is for detecting claim 7 or 8 institutes
The scanning signal for the shift register output stated, the detection method include:
Effective test control signal is provided to the control line；
Receive the test signal that the p-wire receives；
Successively judge whether the test signal in every 1/2a clock signal period exception occurs, if there is exception, determining should
The corresponding shifting deposit unit failure of 1/2a clock signal period.
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