CN109857242A - A kind of low power processor system - Google Patents
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Abstract
A kind of low power processor system disclosed by the invention, a kind of low power processor system, including reference clock, one output end of reference clock is connected with the input terminal of shift counter, to drive shift counter to run, the another output of reference clock and the input terminal of control module connect, and to clock signal needed for generation system operation, shift counter is realized by dynamic switch unit without flow water treater dynamic switch.A kind of low power processor system of the present invention, enables to the quiescent dissipation of processor to reduce, and reduces plant capacity consumption.
Description
Technical field
The invention belongs to low power processor technical fields, and in particular to a kind of low power processor system.
Background technique
Nowadays embedded technology is widely used in every field, such as Industry Control, people's daily life, military state
Anti-, network communication etc., embedded technology all plays the role to become more and more important in the various aspects that people live.And it is embedded
System in people's daily life application more and more be battery power supply or without battery system, it is this to have sternly with to power supply
The limitation of lattice, also resulting in has stringent limitation to power consumption of processing unit, therefore Low-power Technology has the development of processor
Vital meaning.
At present in Design of Digital Circuit, common Low-power Technology mainly has: multi-Vt technology and power gating skill
Art etc..The multi-Vt cmos circuit (MTCMOS) that multi-Vt technology uses refers to that circuit itself can be in multiple threshold values
It works under voltage condition, for the transistor in critical path, can use high voltage to meet the needs of performance, for non-pass
Transistor on key path, so that it may realize low-power consumption using low threshold voltage.Power gating technology refer to by ground wire and
The technology of an ON-OFF control circuit working condition is inserted among circuit or among power supply line and circuit.Above two technology quilt
It applies in different Design of Digital Circuit, is also employed in low power processor design.But these technologies are not directed to
The operation characteristic of processor optimizes.
The characteristics of low power processor, is, is all according to as far as possible to realize higher performance in its design process
The high speed of service is designed.And in actual working environment, since many tasks are fairly simple, do not need very high
Calculated performance, therefore processor is often run at very low frequencies.In this case, processor calculating logic is soon
When having obtained calculated result, but only waited until that the rising edge of next clock cycle arrives, processor could will be counted
Obtained result saves.In this case, counting circuit is in idle state after obtaining calculated result, this
When the quiescent dissipation due to caused by leakage current, be entirely the energy consumption of no any effect.With semiconductor process technology
It is promoted, circuit computing speed is getting faster, and quiescent dissipation is increasing.In low frequency, circuit is completed after calculating, processor
The time for being in idle state is increasingly longer, and quiescent dissipation is bigger, and the energy of waste is also more and more.
Summary of the invention
The purpose of the present invention is to provide a kind of low power processor systems, and the quiescent dissipation of processor is enabled to drop
It is low, reduce plant capacity consumption.
The first technical solution of the present invention is: a kind of low power processor system, including reference clock, benchmark
One output end of clock is connected with the input terminal of shift counter, to drive shift counter to run, reference clock it is another
One output end and the input terminal of control module connect, the clock signal required to generation system operation, shift counter
Output end includes the 0th output end, the 1st output end, the 2nd output end, the 3rd output end, the 0th output end connection control
The input terminal of module, the output end of control module and the input terminal of OR circuit connect, the output end of OR circuit and no flowing water
Processor connection, shift counter control, 1st output end, 2nd output normally opened without flow water treater by OR circuit
End, the 3rd output end pass through control module respectively and connect with dynamic switch unit, and dynamic switch unit connects with no flow water treater
It connects, shift counter is realized by dynamic switch unit without flow water treater dynamic switch；1st output end, the 2nd output
End, the 3rd output end also pass through control module and directly connect with no flow water treater.
The features of the present invention also characterized in that
Dynamic switch unit includes phase inverter, gate power supply unit, the input terminal of phase inverter and the output end of control module
The output end of connection, phase inverter is connect with gate power supply unit, and gate power supply unit is connect with no flow water treater.
No flow water treater internal logic circuit include first execute phase, second execute phase, third executes phase, the
Four execute phase, and the output end of the first execution phase is connect with the input terminal of the second execution phase, and second executes the output of phase
The input terminal for executing phase with third is held to connect, third executes the output end of phase and first and executes phase, the 4th execution phase
Input terminal connection, the 4th execution phase output end with second execute phase input terminal connect.
The first semi-custom data holding unit, the second execution phase are connected between first execution phase and the second execution phase
Position third execute phase between be connected with the second semi-custom data holding unit, third execute phase with first execute phase,
It is connected between third semi-custom data holding unit, the 4th execution phase and the second execution phase and connects between 4th execution phase
It is connected to the 4th semi-custom data holding unit.
First semi-custom data holding unit, the second semi-custom data holding unit, third semi-custom data holding unit,
4th semi-custom data holding unit includes tri-state gate, and the output end of tri-state gate connects holding unit.
First output end for executing phase connects the input terminal of the tri-state gate of the first semi-custom data holding unit, and the first half
The output end for customizing the tri-state gate of data holding unit is connect with the input terminal of the second execution phase, and second executes the output of phase
The input terminal of the tri-state gate of the second semi-custom data holding unit of end connection, the tri-state gate of the second semi-custom data holding unit
Output end is connect with the input terminal that third executes phase, and the output end connection third semi-custom data that third executes phase keep single
The input terminal of the tri-state gate of member, the output end of the tri-state gate of third semi-custom data holding unit execute phase with first respectively
The input terminal connection of input terminal and the 4th execution phase, the 4th output end for executing phase connect the 4th semi-custom data and keep list
The input terminal of the tri-state gate of member, the input of the output end of the tri-state gate of the 4th semi-custom data holding unit and the second execution phase
End connection.
0th output end is connected by the control terminal on OR circuit and the tri-state gate of the first semi-custom data holding unit
It connects, the 1st output end is connect with the control terminal on the tri-state gate of the second semi-custom data holding unit, the 2nd output end and
Control terminal connection on the tri-state gate of three semi-custom data holding units, the 3rd output end and the 4th semi-custom data keep single
Control terminal connection on the tri-state gate of member.
1st output end passes sequentially through phase inverter and gate power supply unit and connect with the second execution phase, the 2nd output end
It passes sequentially through phase inverter and gate power supply unit to connect with third execution phase, the 3rd output end passes sequentially through phase inverter and door
Control power supply unit is connect with the 4th execution phase.
The beneficial effects of the present invention are: a kind of low power processor system of the present invention, provides one kind in a clock cycle
The interior combinational logic by inside processor carries out the structure that dynamic opens shutdown, and one, which makes processor reach part, can open pass
Effect that is disconnected and will not losing data, can turn off previous module and worked and finish when secondly opening next execution phase circuit
Circuit, thirdly processor to be divided into four execution phases within a clock cycle, dynamically opens pass so that quiescent dissipation is lower
The requirement for reducing quiescent dissipation can be achieved under low frequency state, reduce the energy of processor waste for the partial circuit of disconnected modules
Amount, keeps the device standby time longer.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of low power processor system of the present invention；
Fig. 2 is shift counter and transmits connection figure without enable signal between flow water treater；
Fig. 3 is in a kind of low power processor system of the present invention without flow water treater structural schematic diagram；
Fig. 4 is the present invention a kind of timing and phase controlling figure of low power processor system.
In figure, 1. shift counters, 2. reference clocks, 3. control modules, 4. phase inverters, 5. gate power supply units, 6. the
One executes phase, and 7. second execute phase, and 8. thirds execute phase, and 9. the 4th execute phase, and 10. tri-state gates, 11. keep single
Member, 12. OR circuits, 13. without flow water treater.
Specific embodiment
The following describes the present invention in detail with reference to the accompanying drawings and specific embodiments.
A kind of low power processor system structure of the present invention is as shown in Figure 1, include reference clock 2, and one of reference clock 2
Output end is connected with the input terminal of shift counter 1, to drive shift counter 1 to run, another output of reference clock 2
End is connect with the input terminal of control module 3, the clock signal required to generation system operation,
As shown in Fig. 2, the output end of shift counter 1 include the 0th output end, the 1st output end, the 2nd output end,
3rd output end, the input terminal of the 0th output end link control module 3, output end and the OR circuit 12 of control module 3
Input terminal connection, the output end of OR circuit 12 are connect with no flow water treater 13, and shift counter 1 is controlled by OR circuit 12
System is normally opened without flow water treater 13, is exactly first execution of the 0th output end control of shift counter 1 without flow water treater 13
Phase is normally opened, and the 1st output end, the 2nd output end, the 3rd output end pass through control module 3 respectively and dynamic switch unit connects
It connects, dynamic switch unit is connect with no flow water treater 13, and shift counter 1 is realized by dynamic switch unit without stream treatment
13 dynamic switch of device；1st output end, the 2nd output end, the 3rd output end also pass through control module 3 directly and at no flowing water
Device 13 is managed to connect.
Dynamic switch unit includes phase inverter 4, gate power supply unit 5, and the input terminal of phase inverter 4 is defeated with control module 3
The output end of outlet connection, phase inverter 4 is connect with gate power supply unit 5, and gate power supply unit 4 connects with no flow water treater 13
It connects.
Further, no 13 internal logic circuit of flow water treater includes the first execution phase, the second execution phase, third
Phase, the 4th execution phase are executed, the output end of the first execution phase is connect with the input terminal of the second execution phase, and second executes
The input terminal that the output end of phase and third execute phase connect, and third executes the output end and the first execution phase, the of phase
Four execute the input terminal connection of phase, and the output end of the 4th execution phase is connect with the input terminal of the second execution phase.
Further, first execution phase and second execution phase between be connected with the first semi-custom data holding unit,
Second execution phase and third execute and are connected with the second semi-custom data holding unit between phase, third executes phase and first
It executes and is connected with third semi-custom data holding unit between phase, the 4th execution phase, the 4th execution phase is executed with second
The 4th semi-custom data holding unit is connected between phase.
Further, the first semi-custom data holding unit, the second semi-custom data holding unit, third semi-custom data
Holding unit, the 4th semi-custom data holding unit include tri-state gate 10, and the output end of tri-state gate 10 connects holding unit 11,
First output end for executing phase connects the input terminal of the tri-state gate 10 of the first semi-custom data holding unit, the first semi-custom number
It is connect according to the output end of the tri-state gate 10 of holding unit with the input terminal of the second execution phase, the second output end for executing phase connects
The input terminal of the tri-state gate 10 of the second semi-custom data holding unit is connect, the tri-state gate 10 of the second semi-custom data holding unit
Output end is connect with the input terminal that third executes phase, and the output end connection third semi-custom data that third executes phase keep single
The input terminal of the tri-state gate 10 of member, the output end of the tri-state gate 10 of third semi-custom data holding unit execute phase with first respectively
The input terminal connection of the input terminal of position and the 4th execution phase, the 4th output end for executing phase connect the 4th semi-custom data and protect
The input terminal of the tri-state gate 10 of unit is held, the output end of the tri-state gate 10 of the 4th semi-custom data holding unit executes phase with second
The input terminal connection of position.
Further, the 0th output end passes through the tri-state gate 10 of OR circuit 12 and the first semi-custom data holding unit
On control terminal connection, the 1st output end connect with the control terminal on the tri-state gate 10 of the second semi-custom data holding unit, the
2 output ends are connect with the control terminal on the tri-state gate 10 of third semi-custom data holding unit, the 3rd output end and the 4th half
Customize the control terminal connection on the tri-state gate 10 of data holding unit.
Further, the 1st output end passes sequentially through phase inverter 4 and gate power supply unit 5 and connect with the second execution phase,
2nd output end passes sequentially through phase inverter 4 and gate power supply unit 5 and connect with third execution phase, and the 3rd output end successively leads to
Phase inverter 4 and gate power supply unit 5 is crossed to connect with the 4th execution phase.
Present system principle explanation: shift counter 1 generates En_circle, En_DRAM signal in control module 3,
En_circle signal and reference clock 2 generate CLK_circle signal in control module 3, and CLK_circle signal is with four
Reference clock cycle is as a loop control clock, and loop control clock control is without the 13 four execution phases in inside of flow water treater
Next circulation can be can smoothly enter into after position work is primary, En_DRAM signal and reference clock 2 generate CLK_ in control module 3
DRAM signal, CLK_DRAM signal are data storage clock, and data storage clock is protected without the number in flow water treater 13
According to not being lost.
As shown in figure 3, executing phase 6, second without the inside of flow water treater 13 first and execute phase 7, the in the present invention
Three execution phases the 8, the 4th execute that phases 9 respectively represent fetching, decoding, execution, memory access-write back module.First executes phase 6
Including program counter and command memory, it includes register inside decoding module that second, which executes phase 7, which includes decoding module,
Heap file, it includes execution module that third, which executes phase 8, and the 4th execution phase 9 includes data storage and writes back module.According to holding
Row phase sequence successively carries out fetching to data inside no flow water treater 13, decoding, executes operation, several after executing and operating
Carry out fetching operation or data and enter the 4th executing phase according to jumping to enter first and execute phase, carry out accessing operation or need again into
Enter the second execution phase and carries out written-back operation.
Since fetching module only has program counter circuit and command memory two parts circuit, program counter calculates electricity
Road is very simple, and command memory must maintain a normally open, so addition can open the logical block unit of shutdown to it not
It can achieve the purpose that reduce quiescent dissipation, therefore not need to turn off the first execution phase, therefore design the of shift counter 1
0 output end connects OR circuit 12 by control module 3, and an input of OR circuit 12 is high level, so that connection the
Tri-state gate 10 between one execution phase and the second execution phase is always opening state, and the first execution phase circuit is specifically being transported
Open-minded always during row, the 1st output end, the 2nd output end, the 3rd output end of shift counter 1 pass through gate power supply
Unit 5 connects dynamic switch unit, and executing phase, third controlling open and closes inside no flow water treater 13 second holds
All logic circuits in row phase, the 4th execution phase other than data storage.
Dynamic switch unit realizes that the dynamic without flow water treater 13 is opened using phase inverter 4 and the gate cooperation of power supply unit 5
It closes, specifically, when the control signal that shift counter 1 issues is 1, by phase inverter 4, controlling signal becomes 0, gate power supply
Unit 5 is open-minded, and when the control signal that shift counter 1 issues is 0, by phase inverter 4, controlling signal becomes 1, gate power supply
Unit 5 is closed, and in system operation, gate power supply unit 5 is opened, and makes phase circuit connected to it open-minded, is gated
The closing of power supply unit 5 closes phase circuit connected to it, and control gate power supply unit 5 is opened and closed to real
Dynamic now without flow water treater 13 opens closing, and further, the present invention gates power supply unit 5 and uses Headers
Switching VDD realizes this function of dynamic switch.As shown in figure 4, gate power supply unit 5 is specifically opened and closed process are as follows: work as shifting
When the output of digit counter 1 is 0001, by phase inverter 4, signal becomes 1111, and second executes phase 7, third executes phase 8, the
Four execute phase 9 as off state；When the output of shift counter 1 is 0010, by phase inverter 4, signal becomes 1100, second
Executing 7 phases is opening state, and it is off state that third, which executes phase the 8, the 4th and executes phase 9,；When the output of shift counter 1 is
When 0100, by phase inverter 4, signal becomes 1010, and it is opening state that third, which executes phase 8, and the second execution phase the 7, the 4th is held
Row phase 9 is off state；When the output of shift counter 1 is 1000, by phase inverter 4, signal becomes 0110, and the 4th executes
Phase 9 is opening state, and second executes phase 7, third executes phase 8 as off state, and the first execution phase 6 is always open-minded
State.
In order to avoid no flow water treater 13 is during dynamic switch, there is latter execution phase and open previous execution
The case where phase turns off, so being inserted into semi-custom data holding unit inside no flow water treater 13 to keep previous execution phase
Data before the shutdown of position.Semi-custom data holding unit is made of tri-state gate 10 and holding unit 11.Due to holding unit
11 are generally used on tristate bus line, so a holding unit 11 is arranged after tri-state gate 10.Simultaneously because the original of device technology
Cause, the influence after previous phase circuit shutdown to latter phase circuit not can determine that, therefore the present invention using tri-state gate 10 and is kept
Unit 11 can be turned off at any time by tri-state gate 10, and keep data by holding unit 11, turn off the phase circuit of previous stage
After reduce power consumption while will not have an impact to latter phase circuit.The output end of shift counter 1 passes through control module 3
The state of tri-state gate 10 is controlled, when the enable signal of tri-state gate 10 is 1, so that data is flowed through tri-state gate 10 and reaches holding unit
11；When the enable signal of tri-state gate 10 is 0, the output of tri-state gate 10 is high-impedance state, and holding unit 11 still keeps data, until
10 enable signal of tri-state gate just will be updated the data in holding unit 11 when being again 1.
Advantages of the present invention has:
(1) present invention is realized by Power Gating technology, the connection gate power supply unit 5 of shift counter 1 without flowing water
The dynamic that first execution phase, the second execution phase, third execute phase in processor 13 opens closing, is opening a phase
After circuit, holding unit 11 keeps in this and executes phase circuit data, open-minded to next execution phase circuit, and data will be single from holding
Member 11 flows out, and completes the dynamic without 13 combinational logic of flow water treater in a clock cycle and opens shutdown, so that at without flowing water
It is in an off state that reason 13 part of device executes rest part when phase is in opening state, and will not lose the effect of data, reaches
Processor realizes the requirement for reducing quiescent dissipation under to low frequency state, increases the standby time of equipment.
(2) by Clock Gating technology, reference clock 2 generates in control module 3 present invention with shift counter 1
CLK_circle signal realize as circulation clock to the working cycles for executing phases different in no flow water treater 13, guarantee
The correctness of instruction execution, reference clock 2 connect with shift counter 1 CLK_DRAM generated and execute phase as control the 4th
Data storage in position, ensure that the storage and reading of data.
Claims (8)
1. a kind of low power processor system, which is characterized in that including reference clock (2), one of the reference clock (2) is defeated
Outlet is connected with the input terminal of shift counter (1), to drive shift counter (1) run, the reference clock (2) it is another
One output end is connect with the input terminal of control module (3), to clock signal needed for generation system operation；
The output end of the shift counter (1) include the 0th output end, the 1st output end, the 2nd output end, the 3rd it is defeated
Outlet, the input terminal of the 0th output end link control module (3), the output end connection of the control module (3) or door electricity
The output end of the input terminal on road (12), the OR circuit (12) is connect with no flow water treater (13), the shift counter
(1), 1st output end, 2nd output end, 3rd normally opened without flow water treater (13) are controlled by OR circuit (12)
Output end passes through control module (3) respectively and connect with dynamic switch unit, the dynamic switch unit and no flow water treater
(13) it connects, the shift counter (1) is realized by dynamic switch unit without flow water treater (13) dynamic switch；
1st output end, the 2nd output end, the 3rd output end also pass through control module (3) directly with no stream treatment
Device (13) connection.
2. a kind of low power processor system as described in claim 1, which is characterized in that the dynamic switch unit includes anti-
Phase device (4), gate power supply unit (5), the input terminal of the phase inverter (4) and the output end (3) of control module connect, described anti-
The output end of phase device (4) is connect with gate power supply unit (5), the gate power supply unit (5) and the no flow water treater
(13) it connects.
3. a kind of low power processor system as claimed in claim 2, which is characterized in that in the no flow water treater (13)
Portion's logic circuit includes the first execution phase, the second execution phase, third execution phase, the 4th execution phase, and described first holds
The output end of row phase is connect with the input terminal of the second execution phase, and described second executes the output end of phase and third execution phase
The input terminal connection of position, the third executes the output end of phase and the first execution phase, the 4th input terminal for executing phase connect
It connects, the output end of the 4th execution phase is connect with the input terminal of the second execution phase.
4. a kind of low power processor system as claimed in claim 3, which is characterized in that described first executes phase and second
It executes to be connected between phase between the first semi-custom data holding unit, the second execution phase and third execution phase and be connected with
Second semi-custom data holding unit, third execute and are connected with third between phase and the first execution phase, the 4th execution phase
The 4th semi-custom data, which are connected with, between semi-custom data holding unit, the 4th execution phase and the second execution phase keeps single
Member.
5. a kind of low power processor system as claimed in claim 4, which is characterized in that the first semi-custom data are kept
Unit, the second semi-custom data holding unit, third semi-custom data holding unit, the 4th semi-custom data holding unit are wrapped
It includes tri-state gate (10), the output end of tri-state gate (10) connects holding unit (11).
6. a kind of low power processor system as claimed in claim 5, which is characterized in that described first executes the output of phase
End connects the input terminal of the tri-state gate (10) of the first semi-custom data holding unit, and the first semi-custom data keep single
The output end of the tri-state gate (10) of member is connect with the input terminal of the second execution phase, and described second executes the output end of phase
Connect the input terminal of the tri-state gate (10) of the second semi-custom data holding unit, the second semi-custom data holding unit
Output end and the third of tri-state gate (10) execute the input terminal of phase and connect, the third executes the output end company of phase
The input terminal of the tri-state gate (10) of the third semi-custom data holding unit is connect, the third semi-custom data holding unit
The output end of tri-state gate (10) is connect with the input terminal of the input terminal of the first execution phase and the 4th execution phase respectively, and described the
Four execution phases output ends connect the 4th semi-custom data holding unit tri-state gate (10) input terminal, the described 4th
The output end of the tri-state gate (10) of semi-custom data holding unit is connect with the input terminal of the second execution phase.
7. a kind of low power processor system as claimed in claim 5, which is characterized in that the 0th output end pass through or
Gate circuit (12) is connect with the control terminal on the tri-state gate (10) of the first semi-custom data holding unit, the 1st output end
It is connect with the control terminal on the tri-state gate (10) of the second semi-custom data holding unit, the 2nd output end and third semidefinite
Control terminal connection on the tri-state gate (10) of data holding unit processed, the 3rd output end and the 4th semi-custom data are kept
Control terminal connection on the tri-state gate (10) of unit.
8. a kind of low power processor system as claimed in claim 5, which is characterized in that the 1st output end successively leads to
It crosses phase inverter (4) and gate power supply unit (5) to connect with the second execution phase, the 2nd output end passes sequentially through phase inverter
(4) phase is executed with third and is connect with gate power supply unit (5), the 3rd output end passes sequentially through phase inverter (4) and gate
Power supply unit (5) is connect with the 4th execution phase.
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| JP2007053680A (en) * | 2005-08-19 | 2007-03-01 | Toshiba Corp | Semiconductor integrated circuit device |
| CN101101504A (en) * | 2007-08-16 | 2008-01-09 | 中国科学院计算技术研究所 | Processor and its frequency-reducing device and method |
| US9317639B1 (en) * | 2014-10-27 | 2016-04-19 | Freescale Semiconductor, Inc. | System for reducing power consumption of integrated circuit |
| CN108171304A (en) * | 2017-12-19 | 2018-06-15 | 重庆湃芯微电子有限公司 | A kind of ultra-high frequency RFID label digital baseband low-power dissipation system based on EPC/C-1/G-2 standards |
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2019
- 2019-01-30 CN CN201910091912.7A patent/CN109857242B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007053680A (en) * | 2005-08-19 | 2007-03-01 | Toshiba Corp | Semiconductor integrated circuit device |
| CN101101504A (en) * | 2007-08-16 | 2008-01-09 | 中国科学院计算技术研究所 | Processor and its frequency-reducing device and method |
| US9317639B1 (en) * | 2014-10-27 | 2016-04-19 | Freescale Semiconductor, Inc. | System for reducing power consumption of integrated circuit |
| CN108171304A (en) * | 2017-12-19 | 2018-06-15 | 重庆湃芯微电子有限公司 | A kind of ultra-high frequency RFID label digital baseband low-power dissipation system based on EPC/C-1/G-2 standards |
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