CN109841511B - Insulating layer etchant composition and method of forming pattern using the same - Google Patents
Insulating layer etchant composition and method of forming pattern using the same Download PDFInfo
- Publication number
- CN109841511B CN109841511B CN201811381934.9A CN201811381934A CN109841511B CN 109841511 B CN109841511 B CN 109841511B CN 201811381934 A CN201811381934 A CN 201811381934A CN 109841511 B CN109841511 B CN 109841511B
- Authority
- CN
- China
- Prior art keywords
- insulating layer
- etchant composition
- chemical formulas
- compound
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
- C09K13/00—Etching, surface-brightening or pickling compositions
- C09K13/04—Etching, surface-brightening or pickling compositions containing an inorganic acid
- C09K13/06—Etching, surface-brightening or pickling compositions containing an inorganic acid with organic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Materials Engineering (AREA)
- Organic Chemistry (AREA)
- Weting (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
An insulating layer etchant composition comprising: phosphoric acid; a polypentasilane compound in which a plurality of silane groups are bonded to each other through a linking group containing at least one carbon atom; and the balance water. The oxide layer is protected by the polypodisilane compound, thereby improving etching selectivity.
Description
Cross Reference to Related Applications
The present application claims priority from korean patent application No.10-2017-0158413, which was filed in the Korean Intellectual Property Office (KIPO) at 11/24/2017, and korean patent application No. 10-2018-0134555, which was filed in 11/6/2018, the entire disclosures of which are incorporated herein by reference.
Technical Field
The present application relates to an insulating layer etchant composition and a method of forming a pattern using the same. More particularly, the present application relates to an insulating layer etchant composition including a mineral acid and a method of forming a pattern using the same.
Background
For example, thin Film Transistors (TFTs) and various pixel circuits are disposed on a back substrate of an image display device such as a Liquid Crystal Display (LCD) device or an Organic Light Emitting Display (OLED) device, and an insulating layer such as an insulating interlayer, a gate insulating layer, a via insulating layer, or the like is formed to insulate a conductive structure.
In semiconductor devices such as memory devices, insulating layers such as isolation layers, insulating interlayers, gate insulating layers are also formed on silicon substrates or germanium substrates.
For example, an insulating layer may be deposited to include silicon oxide or silicon nitride, and thus a silicon oxide layer and a silicon nitride layer may be formed.
When etching an insulating layer to form a pattern, a selective etching process for a specific layer may be required. For example, a selective etching process for the silicon nitride layer may be required. In this case, an etchant composition for etching only the silicon nitride layer while sufficiently protecting the silicon oxide layer may be used.
In addition, when the selective etching process is performed at high temperature for a long time, it is necessary to stably and reliably protect the silicon oxide layer.
For example, korean registered patent publication No.10-0823461 discloses a composition for etching both a silicon oxide layer and a silicon nitride layer, however, a selective etching process as described above may not be realized by the composition.
Disclosure of Invention
According to one aspect of the present application, an insulating layer etchant composition having improved etch selectivity and uniformity is provided.
According to one aspect of the present application, a method of forming a pattern using the insulating layer etchant composition is provided.
The above aspects of the inventive concept will be achieved by the following features or structures:
(1) An insulating layer etchant composition comprising phosphoric acid; a polypentasilane compound in which a plurality of silane groups are bonded to each other through a linking group containing at least one carbon atom; and the balance water.
(2) The insulating layer etchant composition according to the above (1), wherein each silane group contained in the polypodisilane compound contains a plurality of passivation groups.
(3) The insulating layer etchant composition according to the above (2), wherein the passivation group comprises an alkoxy group, a halogen group or a phosphate group.
(4) The insulating layer etchant composition according to the above (1), wherein the polypentasilane compound includes a compound represented by the following chemical formula 1:
[ chemical formula 1]
Wherein in the above chemical formula 1, R represents a linking group and is a divalent organic group containing at least one carbon atom, R 1 And R is 2 Each independently is C1 to C12 alkyl or C6 to C12 aryl, X 1 And X 2 Each independently is halogen, -OR 3 A group or phosphate group, R 3 Is a C1 to C10 alkyl group capable of containing an ether linkage, or a C6 to C12 aryl group, L is an integer of 1 or 2, and m and n are each independently an integer of 1 to 3.
(5) The insulating layer etchant composition according to the above (4), wherein the polypentasilane compound comprises at least one selected from the group consisting of bipedal silane compounds represented by the following chemical formulas 2-1 to 2-7:
[ chemical formula 2-1]
[ chemical formula 2-2]
[ chemical formulas 2-3]
[ chemical formulas 2-4]
[ chemical formulas 2-5]
[ chemical formulas 2-6]
[ chemical formulas 2-7]
Wherein, in the above chemical formulas 2-1 to 2-7, et represents ethyl.
(6) The insulating layer etchant composition according to the above (4), wherein the polypodisilane compound comprises at least one selected from the group consisting of tripodisilane compounds represented by the following chemical formulas 3-1 and 3-2:
[ chemical formula 3-1]
[ chemical formula 3-2]
Wherein, in the above chemical formulas 3-1 and 3-2, et represents ethyl.
(7) The insulating layer etchant composition according to the above (1), wherein the amount of the polypentasilane compound is in the range of 0.0001 to 1% by weight based on the total weight of the composition.
(8) The insulating layer etchant composition according to the above (1), wherein a compound containing a siloxane bond (-Si-O-Si-) is excluded from the composition.
(9) A method of forming a pattern, comprising: forming an oxide layer and a nitride layer on a substrate; and selectively etching the nitride layer using the insulating layer etchant composition according to any one of (1) to (8) above.
(10) The method according to the above (9), wherein the oxide layer comprises a silicon oxide layer and the nitride layer comprises a silicon nitride layer.
According to exemplary embodiments as described above, the insulating layer etchant composition may include phosphoric acid and a polypentasilane compound. In the polypodal silane compound, a plurality of passivation groups may be bonded to each silicon atom, so that the passivation effect of, for example, a silicon oxide layer can be promoted.
In addition, the polypentasilane compound may comprise a linking group that may bind a plurality of silane groups and may comprise at least one carbon atom. The chelating effect for sufficiently protecting the silicon oxide layer can be achieved by the linking group, so that the passivation effect on the silicon oxide layer can be additionally increased. In addition, dissociation of silane groups can be suppressed in phosphoric acid at high temperature, so that etching performance can be uniformly maintained for a long period of time.
According to an exemplary embodiment, the insulating layer etchant composition may be effectively used for a selective etching process of a silicon nitride layer while preventing the silicon oxide layer from being etched.
Drawings
Fig. 1 to 3 are schematic cross-sectional views illustrating a method of forming a pattern according to an exemplary embodiment; and is also provided with
Fig. 4 to 6 are schematic cross-sectional views illustrating a method of forming a pattern according to an exemplary embodiment.
Detailed Description
According to an exemplary embodiment, an insulating layer etchant composition is provided that includes phosphoric acid and a polypentasilane compound, and has a high etching selectivity to a nitride layer relative to an oxide layer. A method of forming a pattern using the insulating layer etchant composition is also provided.
Hereinafter, the present application will be described in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that such embodiments described with reference to the drawings are provided for further understanding of the spirit of the application, and are not to limit the claimed subject matter as disclosed in the specific description and appended claims.
< insulating layer etchant composition >
According to an exemplary embodiment, the insulating layer etchant composition may include phosphoric acid, a polypentasilane compound, and the balance water.
An insulating layer etchant composition may be provided on a structure including an oxide layer (e.g., a silicon oxide layer) and a nitride layer (e.g., a silicon nitride layer) to etch the nitride layer with high etch selectivity without damaging the oxide layer.
For example, the insulating layer etchant composition may be used to selectively etch a silicon nitride layer in the manufacture of semiconductor devices.
Phosphoric acid can be represented by, for example, formula H 3 PO 4 Represents, and can be used as, the main etching component for etching the nitride layer. In exemplary embodiments, the amount of phosphoric acid may be in the range of about 80 weight percent (wt%) to about 95 wt%, based on the total weight of the insulating layer etchant composition.
If the amount of phosphoric acid may be less than about 80 wt%, the overall etch rate may be reduced. If the amount of phosphoric acid may exceed about 95 wt%, the etch rate of the oxide layer or the conductive layer (such as a metal layer) may also be increased along with the etch rate of the nitride layer, thereby reducing the etch selectivity to the nitride layer.
Preferably, the amount of phosphoric acid may be controlled in the range of about 80 wt% to about 90 wt% in view of the etching rate and etching selectivity.
A polypentasilane compound may represent a compound in which a plurality of silane groups may be combined in a single molecule. In exemplary embodiments, bipedal compounds in which two silane groups are bound in a single molecule, and/or tripodal silane compounds in which three silane groups are bound in a single molecule may be used.
The silane groups may comprise a silicon atom and, for example, three passivating groups bonded thereto. The passivating groups may include, for example, alkoxy groups, halogen atoms, or phosphate groups (-OPO) 3 H 2 ) And may be adsorbed on or chemically interact with the surface of the silicon oxide layer to form a passivation layer. The polypentasilane compound may contain a plurality of silane groups such that the number of passivating groups may be increased to, for example, 6 or 9Etc. Therefore, the passivation effect with respect to the surface of the oxide layer (such as a silicon oxide layer) can be enhanced.
In an exemplary embodiment, the silane groups included in the polypentasilane compound may be linked to each other through a linking group including at least one carbon atom. For example, in the polysilane compound according to the exemplary embodiment, a structure in which silane groups are directly connected or connected only through oxygen atoms (-si—o—si) may be excluded.
In an exemplary embodiment, the polypentasilane compound may include a compound represented by the following chemical formula 1.
[ chemical formula 1]
In the above chemical formula 1, R represents a linking group, and may be a divalent organic group containing at least one carbon atom. R is R 1 And R is 2 May each independently represent a C1 to C12 alkyl group or a C6 to C12 aryl group.
X 1 And X 2 Can each independently represent halogen, -OR 3 A group or a phosphate group, and R 3 Can represent a C1 to C10 alkyl group capable of containing an ether linkage, or a C6 to C12 aryl group.
L may be an integer of 1 or 2, and m and n may each independently be an integer of 1 to 3.
In some embodiments, the polypodial compound may include at least one of bipedal silane compounds represented by the following chemical formulas 2-1 to 2-7.
[ chemical formula 2-1]
[ chemical formula 2-2]
[ chemical formulas 2-3]
[ chemical formulas 2-4]
[ chemical formulas 2-5]
[ chemical formulas 2-6]
[ chemical formulas 2-7]
The linking group in the tripodal silane compound may comprise a linking center for binding three silane groups. Three bonding sites may be separated from the connection center so that three silane groups may be combined.
In some embodiments, the linking center may include a nitrogen atom. In this case, the solubility or compatibility of the tripodal silane compound with respect to phosphoric acid can be improved.
For example, the polypentasilane compound may include at least one of tripodal silane compounds represented by the following chemical formula 3-1 or chemical formula 3-2.
[ chemical formula 3-1]
[ chemical formula 3-2]
In the insulating layer etchant composition according to the exemplary embodiments as described above, the silane groups including the plurality of passivation groups may be separated from each other in a single molecule by the connection group. Thus, the coverage of silane groups that can be bound to or adsorbed on the oxide layer surface can be increased. In addition, the linking group can provide a chelating effect, so that a passivation effect on the oxide layer can be effectively achieved.
The linking group may have an organic-based structure, and thus may prevent permeation of phosphoric acid as an inorganic acid, thereby additionally protecting the oxide layer.
In the comparative example, a siloxane compound may be used to protect the oxide layer. In the siloxane compound, silicon atoms adjacent to each other may be directly bonded (-Si-O-Si-) through oxygen atoms. Therefore, the distance between adjacent silicon atoms is too small, and thus the chelating effect and coverage increase of the polypentasilane compound according to the exemplary embodiment may not be substantially achieved.
Further, the siloxane compound may have a structure similar to that of silicon oxide, and thus may be dissociated together with the silicon oxide layer by phosphoric acid. For example, the siloxane compound may dissociate in the etching process at a high temperature of 150 ℃ or more, and thus may not constantly maintain the initial etching capability.
However, according to exemplary embodiments, a polypentasilane compound containing a linking group may be used instead of the siloxane compound. Accordingly, the passivation effect on the oxide layer can be enhanced, and uniform etching performance (e.g., etching rate) can be maintained for a long period of time.
In some embodiments, fluoride ion generating species (e.g., fluoride or fluoride ion salts, such as ammonium fluoride) may be excluded from the insulating layer etchant composition. Thus, etching damage to the oxide layer by fluoride ions can be avoided.
In some embodiments, the insulating layer etchant composition may not include components such as oximes, which may generate residues on the etched objects. Accordingly, the silicon oxide layer can be protected by the polypodal silane compound, and the etching efficiency of the silicon nitride layer can be improved by phosphoric acid.
In some embodiments, the insulating layer etchant composition may include the polypentasilane compound in an amount ranging from about 0.0001 wt% to about 1 wt%, based on the total amount of the composition. If the amount of the polypentasilane compound is less than about 0.0001 wt%, passivation of the oxide layer may not be substantially achieved. If the amount of the polypentasilane compound exceeds about 1 wt%, the etching ability of phosphoric acid may be deteriorated.
Preferably, the amount of the polypentasilane compound may be controlled in the range of about 0.001 wt% to about 0.1 wt% based on the total amount of the composition in view of the oxide layer passivation and etching rate.
The insulating layer etchant composition may include the balance water (e.g., deionized water). For example, phosphoric acid may be provided as an aqueous solution (e.g., 85% phosphoric acid), and the polypentasilane compound may be contained in the amount range as described above, based on 100 parts by weight of the phosphoric acid aqueous solution.
In some embodiments, the insulating layer etchant composition may consist essentially of phosphoric acid, a polypentasilane compound, and the balance water. In some embodiments, the insulating layer etchant composition may further include an additive (such as an etch enhancer) without reducing the passivation effect of the polypental silane compound and the etching efficiency of phosphoric acid.
< method of Forming Pattern >
Fig. 1 to 3 are schematic cross-sectional views illustrating a method of forming a pattern according to an exemplary embodiment.
Referring to fig. 1, an oxide layer 110 and a nitride layer 120 may be formed on a substrate 100.
The substrate 100 may comprise a semiconductor material (such as monocrystalline silicon, monocrystalline germanium, etc.), or may comprise polycrystalline silicon.
In an exemplary embodiment, the oxide layer 110 may be formed of silicon oxide. The oxide layer 110 may be formed by a Chemical Vapor Deposition (CVD) process, a sputtering process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, and the like.
A nitride layer 120 may be formed on the oxide layer 110. In an exemplary embodiment, the nitride layer 120 may be formed of silicon nitride by a CVD process, a PVD process, a sputtering process, an ALD process, and the like.
Referring to fig. 2, a photoresist pattern 130 may be formed on the nitride layer 120. For example, a photoresist layer may be formed on the nitride layer 120, and a portion of the photoresist layer may be removed through a selective exposure process and a development process.
Accordingly, a photoresist pattern 130 partially exposing the top surface of the nitride layer 120 may be formed.
Referring to fig. 3, a wet etching process may be performed using the insulating layer etchant composition according to an exemplary embodiment and using the photoresist pattern 130 as an etching mask.
Thus, the exposed portion of the nitride layer 120 may be removed to form the nitride pattern 125. As described above, the insulating layer etchant composition according to exemplary embodiments may provide significantly improved oxide passivation by the polypentasilane compound. Accordingly, the surface of the oxide layer 110 may not be substantially etched or damaged, and the nitride layer 120 may be selectively etched.
For etching efficiency, the insulating etchant composition may be heated to about 150 ℃ or higher. The polypentasilane compound may be stable even at high temperature, and thus the initial etching rate and passivation may be uniformly maintained.
The photoresist pattern 130 may be removed after the etching process through a stripping process and/or an ashing process.
As shown in fig. 1 to 3, the nitride layer 120 may be partially removed. Alternatively, the nitride layer 120 may be completely removed using an etchant composition. In this case, the top surface of the oxide layer 110 may be completely protected by the polypodal silane compound to prevent etching damage.
Fig. 4 to 6 are schematic cross-sectional views illustrating a method of forming a pattern according to an exemplary embodiment.
Referring to fig. 4, a plurality of oxide layers 210 and nitride layers 220 may be alternately and repeatedly stacked on a substrate 200.
Referring to fig. 5, a via pattern 230 penetrating the oxide layer 210 and the nitride layer 220 may be formed. For example, the oxide layer 210 and the nitride layer 220 may be commonly etched by a dry etching process to form an opening, and a filling material may be formed in the opening to form the via pattern 230. The via pattern 230 may be formed of a semiconductor material such as polysilicon or a conductive material such as metal.
Referring to fig. 6, the nitride layer 220 may be selectively removed using an etchant composition according to an exemplary embodiment as described above.
Accordingly, the oxide layer 210 may remain on the sidewalls of the via pattern 230, and the gap 240 may be defined by a space where the nitride layer 220 is removed. A conductive layer (such as a metal layer) may be formed in the gap 240. During the etching process, the oxide layer 210 may be protected from etching damage by the polypodide compound.
The method of forming a pattern as described above is provided as an exemplary embodiment, and the insulating layer etchant composition may also be used to form various insulating structures (e.g., a gate insulating layer, a barrier layer, an isolation layer, etc.) included in a semiconductor device or a display device.
Hereinafter, preferred embodiments will be described with reference to examples to more specifically understand the present application. It will be apparent, however, to one skilled in the art that such embodiments are provided for illustrative purposes and that various modifications and changes can be made without departing from the scope and spirit of the application, and such modifications and changes are properly included in the application as defined by the appended claims
Examples and comparative examples
0.1 parts by weight of a polypentasilane compound as listed below was mixed in 100 parts by weight of an aqueous 85% phosphoric acid solution to form the etchant composition of the example.
In the following chemical formulas, "Et" represents ethyl, and "Me" represents methyl.
1) Example 1
2) Example 2
3) Example 3
4) Example 4
5) Example 5
0.1 parts by weight of a silicon-based compound as listed below was mixed in 100 parts by weight of an aqueous 85% phosphoric acid solution to form an etchant composition of comparative example.
1) Comparative example 1
2) Comparative example 2
3) Comparative example 3
4) Comparative example 4
Experimental examples
(1) Measuring etch rate (E/R) of silicon nitride (SiN) layer
Cutting includes a cutting edge having a thickness thereon ofTo form a wafer having a dimension of 2 x 2cm 2 Is a sample of (a). The samples were immersed in the compositions of examples and comparative examples for 3 minutes at 160 ℃. After impregnation, the samples were washed with deionized water (DIW) and dried. After drying, the thickness of the sample was measured using a Scanning Electron Microscope (SEM) to measure the etching rate +.>
(2) Measurement of Silica (SiO) 2 ) Etch rate of layer
Cutting comprises a thickness ofSilicon oxide (SiO) 2 ) Wafer of layers to form a wafer of dimensions 2 x 2cm 2 Is a sample of (a). The samples were immersed in the compositions of examples and comparative examples for 3 minutes at 160 ℃. After impregnation, the samples were washed with deionized water (DIW) and dried. After drying, the thickness of the sample was measured using an ellipsometer to measure the etch rate +.>
The results are shown in Table 1 below.
TABLE 1
Referring to table 1 above, the composition of the example including the polypentasilane compound showed improved passivation effect on the oxide layer compared to the composition of the comparative example, and an etching selectivity of more than about 1000 to the nitride layer was achieved.
Claims (6)
1. An insulating layer etchant composition comprising:
phosphoric acid;
a polypentasilane compound in which a plurality of silane groups are bonded to each other through a linking group containing at least one carbon atom; and
the balance of water is used for preparing the water,
wherein compounds containing siloxane bonds (-Si-O-Si-) are excluded from the composition,
wherein the multi-foot silane compound includes at least one selected from the group consisting of a bipedal silane compound represented by the following chemical formulas 2-1 to 2-7 and a tripedal silane compound represented by the following chemical formulas 3-1 and 3-2:
[ chemical formula 2-1]
[ chemical formula 2-2]
[ chemical formulas 2-3]
[ chemical formulas 2-4]
[ chemical formulas 2-5]
[ chemical formulas 2-6]
[ chemical formulas 2-7]
[ chemical formula 3-1]
[ chemical formula 3-2]
Wherein, in the above chemical formulas 2-1 to 2-7 and chemical formulas 3-1 and 3-2, et represents ethyl.
2. The insulating layer etchant composition of claim 1 wherein each silane group contained in the polypodal silane compound comprises a plurality of passivating groups.
3. The insulating layer etchant composition of claim 2 wherein the passivating group comprises an alkoxy, halogen, or phosphate group.
4. The insulating layer etchant composition of claim 1, wherein the amount of the polypentasilane compound is in the range of 0.0001 wt% to 1 wt%, based on the total weight of the composition.
5. A method of forming a pattern, comprising:
forming an oxide layer and a nitride layer on a substrate; and is also provided with
The nitride layer is selectively etched using the insulating layer etchant composition according to any one of claims 1 to 4.
6. The method of claim 5, wherein the oxide layer comprises a silicon oxide layer and the nitride layer comprises a silicon nitride layer.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2017-0158413 | 2017-11-24 | ||
| KR20170158413 | 2017-11-24 | ||
| KR10-2018-0134855 | 2018-11-06 | ||
| KR1020180134855A KR102629574B1 (en) | 2017-11-24 | 2018-11-06 | Insulation layer etchant composition and method of forming pattern using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109841511A CN109841511A (en) | 2019-06-04 |
| CN109841511B true CN109841511B (en) | 2023-09-15 |
Family
ID=66849552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811381934.9A Active CN109841511B (en) | 2017-11-24 | 2018-11-20 | Insulating layer etchant composition and method of forming pattern using the same |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR102629574B1 (en) |
| CN (1) | CN109841511B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102346832B1 (en) | 2018-05-23 | 2022-01-03 | 삼성에스디아이 주식회사 | Etching composition for silicon nitride layer and etching process using the same |
| KR102005963B1 (en) * | 2018-05-26 | 2019-07-31 | 에스케이이노베이션 주식회사 | Composition for etching and silane compound |
| KR102258307B1 (en) * | 2018-09-03 | 2021-06-01 | 주식회사 이엔에프테크놀로지 | Silicon nitride layer etching composition and etching method using the same |
| KR20210016656A (en) * | 2019-08-05 | 2021-02-17 | 오씨아이 주식회사 | Etching solution for silicon nitride layer and method for preparing semiconductor device using the same |
| KR20210026307A (en) * | 2019-08-29 | 2021-03-10 | 에스케이이노베이션 주식회사 | Etching composition, method for etching insulating layer of semiconductor devices using the same and method for preparing semiconductor devices |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102449746A (en) * | 2009-05-25 | 2012-05-09 | Az电子材料（日本）株式会社 | Liquid etchant and method for forming trench isolation structure using same |
| JP2016029717A (en) * | 2014-07-17 | 2016-03-03 | ソウルブレイン シーオー．， エルティーディー． | Etching composition and manufacturing method of semiconductor element using the same |
| TW201734181A (en) * | 2015-12-04 | 2017-10-01 | 秀博瑞殷股份有限公司 | Composition for etching and manufacturing method of semiconductor device using the same |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100335488C (en) * | 2002-01-31 | 2007-09-05 | 东粟株式会社 | Insulating film material containing an organic silane compound, its production method and semiconductor device |
| US7265236B2 (en) * | 2004-02-23 | 2007-09-04 | Gelest, Inc. | Polypodal silanes with embedded hydrophilicity |
| KR100823461B1 (en) | 2007-05-11 | 2008-04-21 | 테크노세미켐 주식회사 | Etchant composition for etching sio2 layer and sinx layer |
| CN101792903A (en) * | 2010-01-14 | 2010-08-04 | 马鞍山市千峰金属表面防腐材料科技有限公司 | Non-chrome alkali-resistant and solvent-resistant galvanized steel sheet surface treatment liquid and preparation method thereof |
| KR101809192B1 (en) * | 2011-12-16 | 2017-12-15 | 에스케이하이닉스 주식회사 | Composition for etching and manufacturing method of semoconductor device using the same |
| KR101320416B1 (en) * | 2011-12-29 | 2013-10-22 | 솔브레인 주식회사 | A Composition for wet etching , and method of wet etching with the same |
| US10030193B2 (en) | 2014-06-18 | 2018-07-24 | Halliburton Energy Services, Inc. | Consolidation compositions comprising multipodal silane coupling agents |
| US9868902B2 (en) * | 2014-07-17 | 2018-01-16 | Soulbrain Co., Ltd. | Composition for etching |
| KR20160010267A (en) * | 2014-07-17 | 2016-01-27 | 솔브레인 주식회사 | Composition for etching and manufacturing method of semiconductor device using the same |
| KR20160050536A (en) * | 2014-10-30 | 2016-05-11 | 램테크놀러지 주식회사 | Etchant compositions for nitride layers and methods of manufacturing semiconductor devices using the same |
| US10377946B2 (en) * | 2014-12-05 | 2019-08-13 | Shanghai Jiao Tong University | Self-passivating quantum dot and preparation method thereof |
| JP6536464B2 (en) * | 2016-04-26 | 2019-07-03 | 信越化学工業株式会社 | Cleaner composition and method for manufacturing thin substrate |
| US10167425B2 (en) * | 2016-05-04 | 2019-01-01 | Oci Company Ltd. | Etching solution capable of suppressing particle appearance |
-
2018
- 2018-11-06 KR KR1020180134855A patent/KR102629574B1/en active IP Right Grant
- 2018-11-20 CN CN201811381934.9A patent/CN109841511B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102449746A (en) * | 2009-05-25 | 2012-05-09 | Az电子材料（日本）株式会社 | Liquid etchant and method for forming trench isolation structure using same |
| JP2016029717A (en) * | 2014-07-17 | 2016-03-03 | ソウルブレイン シーオー．， エルティーディー． | Etching composition and manufacturing method of semiconductor element using the same |
| TW201734181A (en) * | 2015-12-04 | 2017-10-01 | 秀博瑞殷股份有限公司 | Composition for etching and manufacturing method of semiconductor device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109841511A (en) | 2019-06-04 |
| KR102629574B1 (en) | 2024-01-26 |
| KR20190060668A (en) | 2019-06-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109841511B (en) | Insulating layer etchant composition and method of forming pattern using the same | |
| CN110157434B (en) | Insulating layer etchant composition and method of forming pattern using the same | |
| KR102470905B1 (en) | Composition for etching and manufacturing method of semiconductor device using the same | |
| US10995268B2 (en) | Etching composition effective to selectively wet etch a silicon nitride film | |
| CN109837089B (en) | Insulating layer etchant composition and method of forming pattern using the same | |
| JP2020533786A (en) | Compositions and Methods for Etching Silicon Nitride-Containing Substrates | |
| KR20230070441A (en) | Composition for etching and manufacturing method of semiconductor device using the same | |
| US20220089951A1 (en) | Silicon nitride film etching composition and etching method using the same | |
| KR102629576B1 (en) | Insulation layer etchant composition and method of forming pattern using the same | |
| KR20180106144A (en) | Etchant composition for etching nitride layer and methods of forming nitride pattern | |
| KR102469799B1 (en) | Insulation layer etchant composition and method of forming pattern using the same | |
| KR102443313B1 (en) | Insulation layer etchant composition comprising the silane compound and method of forming pattern using the same | |
| KR20190099832A (en) | Insulation layer etchant composition and method of forming pattern using the same | |
| KR20190090210A (en) | Insulation layer etchant composition and method of forming pattern using the same | |
| KR102636960B1 (en) | Insulation layer etchant composition and method of forming pattern using the same | |
| KR102629575B1 (en) | Insulation layer etchant composition and method of forming pattern using the same | |
| KR102469797B1 (en) | Insulation layer etchant composition and method of forming pattern using the same | |
| CN112442372B (en) | Etching composition, method of etching insulating film of semiconductor device using the same, and method of manufacturing semiconductor device | |
| KR20200057288A (en) | Etching composition, method for etching insulating layer of semiconductor devices and method for preparing semiconductor devices | |
| KR102378930B1 (en) | Etchant composition for etching nitride layer and method of forming pattern using the same | |
| KR102532774B1 (en) | Insulation layer etchant composition and method of forming pattern using the same | |
| KR20190081344A (en) | Etching compositions and etching method using the same | |
| KR20190098030A (en) | Insulation layer etchant composition and method of forming pattern using the same | |
| US20210062088A1 (en) | Etching composition, method for etching insulating film of semiconductor devices using the same and method for preparing semiconductor devices | |
| KR20190127050A (en) | Silane compound, insulation layer etchant composition comprising the same and method of forming pattern using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |