CN109818603B - Multiplexing method of bit width conversion circuit and bit width conversion circuit - Google Patents
Multiplexing method of bit width conversion circuit and bit width conversion circuit Download PDFInfo
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Abstract
The invention provides a multiplexing method of a bit width conversion circuit and the bit width conversion circuit, which are characterized in that the current input/output bit width conversion type is obtained; selecting an input/output valid bit corresponding to the input/output bit width conversion type from the barrel shifter MUX array of the bit width conversion circuit to perform input/output bit width conversion; the read/write controller controlling the bit width conversion circuit generates an address bus of the barrel shifter MUX array and outputs a valid indication signal based on the input valid indication signal and the input/output bit width conversion type. The MUX of the Gecarbox circuit is configured into a barrel shift structure, and the same barrel shifter MUX array is multiplexed for all input/output bit width conversion, so that the suitability of the Gecarbox circuit is improved, and the circuit area is effectively reduced.
Description
Technical Field
The present invention relates to the field of digital circuit design, and in particular, to a multiplexing method for a bit width conversion circuit and a bit width conversion circuit.
Background
In digital systems, it is often necessary to perform bit width conversion processing on data, where a circuit generally used is a bit width conversion gecarbox circuit, and an existing gecarbox circuit is generally implemented by using a data selector (MUX) array, where the larger the input/output bit width is, the more complex the correspondence is, and the larger the MUX array area is; moreover, as the current digital system is more and more complex, the input/output bit width of the gecarbox circuit is more and more flexible, and the fixed MUX array structure can only handle the fixed input/output bit width, and the MUX array is not reusable for different input/output bit width conversions.
Disclosure of Invention
The invention provides a multiplexing method of a bit width conversion circuit and the bit width conversion circuit, which are used for solving the technical problems that the area of a MUX array of the bit width conversion circuit is large and the MUX array cannot be multiplexed in the prior art.
In order to solve the technical problems, the invention adopts the following technical scheme:
the invention provides a multiplexing method of a bit width conversion circuit, which comprises the following steps:
acquiring the current input/output bit width conversion type;
selecting an input/output valid bit corresponding to an input/output bit width conversion type from a data selector barrel shifter MUX array of a barrel shift structure of a bit width conversion circuit; barrel shifter MUX array is configured based on the input/output bit width conversion type with the largest MUX array area requirement among the supported multiple input/output bit width conversion types;
performing an input/output bit width conversion of an input/output bit width conversion type based on the selected input/output valid bit;
the read/write controller controlling the bit width conversion circuit generates an address bus of the barrel shifter MUX array and outputs a valid indication signal based on the input valid indication signal and the input/output bit width conversion type.
Further, selecting the input/output valid bit corresponding to the input/output bit width conversion type from the data selector barrel shifter MUX array of the barrel shift structure of the bit width conversion circuit includes:
determining an input bit width M, an output bit width N and an address bit width i of an input/output bit width conversion type;
the input/output valid bit corresponding to the input/output bit width conversion type is selected from the array of data selectors barrel shifter MUX of the barrel shift structure of the bit width conversion circuit according to M, N and i.
Further, determining the input bit width M, the output bit width N, and the address bit width i of the input/output bit width conversion type includes:
based on correspondence m=n+2 i -1, determining an input bit width M, an output bit width N and an address bit width i of the input/output bit width conversion type.
Further, address bit addr [ i-1 ] of barrel shifter MUX array]The selection end of the i-1 stage data selector MUX is connected to control the left shift of data by 2 i-1 Bits.
Still further, the method further comprises: selecting an input buffer valid bit corresponding to an input/output bit width conversion type from an input buffer of a bit width conversion circuit; the input buffer is configured based on the largest effective input bit width in the multiple input/output bit width conversion types;
based on the selected input/output valid bits of the barrel shifter MUX array, performing an input/output bitwidth conversion of the input/output bitwidth conversion type includes:
based on the selected input/output valid bit of the barrel shifter MUX array and the input cache valid bit, an input/output bit width conversion of the input/output bit width conversion type is performed.
The invention provides a bit width conversion circuit, which comprises: a data selector barrel shifter MUX array of barrel-type shifting structure and a read-write controller electrically connected with the barrel shifter MUX array; barrel shifter MUX array is configured based on the input/output bit width conversion type with the largest MUX array area requirement among the supported multiple input/output bit width conversion types;
barrel shifter MUX array is used for selecting the input/output valid bit corresponding to the current input/output bit width conversion type and performing the input/output bit width conversion of the input/output bit width conversion type based on the selected input/output valid bit;
the read-write controller is used for generating an address bus of the barrel shifter MUX array and outputting a valid indication signal based on the input valid indication signal and the input/output bit width conversion type.
Further, the barrel shifter MUX array is also used to determine the input bit width M, the output bit width N, and the address bit width i of the input/output bit width conversion type; the input/output valid bit corresponding to the input/output bit width conversion type is selected from the array of data selectors barrel shifter MUX of the barrel shift structure of the bit width conversion circuit according to M, N and i.
Further, the barrel shifter MUX array is also used for the correspondence m=n+2 i -1, determining an input bit width M, an output bit width N and an address bit width i of the input/output bit width conversion type.
Further, address bit addr [ i-1 ] of barrel shifter MUX array]The selection end of the i-1 stage data selector MUX is connected to control the left shift of data by 2 i-1 Bits.
Still further, the method further comprises: an input buffer electrically connected to the barrel shifter MUX array; the input buffer is configured based on the largest effective input bit width in the multiple input/output bit width conversion types;
the input buffer is used for selecting the input buffer valid bit corresponding to the input/output bit width conversion type and carrying out the input/output bit width conversion of the input/output bit width conversion type in cooperation with the barrel shifter MUX array.
The beneficial effects of the invention are as follows:
the invention provides a multiplexing method of a bit width conversion circuit and the bit width conversion circuit, aiming at the defects of large MUX array area and non-multiplexing MUX array of the bit width conversion circuit in the prior art, the multiplexing method of the bit width conversion circuit comprises the following steps: acquiring the current input/output bit width conversion type; selecting an input/output valid bit corresponding to an input/output bit width conversion type from a data selector barrel shifter MUX array of a barrel shift structure of a bit width conversion circuit; barrel shifter MUX array is configured based on the input/output bit width conversion type with the largest MUX array area requirement among the supported multiple input/output bit width conversion types; performing an input/output bit width conversion of an input/output bit width conversion type based on the selected input/output valid bit; the read/write controller controlling the bit width conversion circuit generates an address bus of the barrel shifter MUX array and outputs a valid indication signal based on the input valid indication signal and the input/output bit width conversion type. The MUX of the Gecarbox circuit is configured into a barrel shift structure based on the input/output bit width conversion type with the largest area requirement of the MUX array, and the same barrel shifter MUX array is multiplexed for all the input/output bit width conversions, so that the suitability of the Gecarbox circuit is improved, and the circuit area is effectively reduced.
Drawings
FIG. 1 is a basic flow chart of a multiplexing method of a bit width conversion circuit according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a gecarbox circuit according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram of another Gecarbox circuit according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a barrel shifter MUX array according to a second embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention will now be further explained by means of specific embodiments in connection with the accompanying drawings.
Embodiment one:
in order to solve the defects of large MUX array area and non-reusability of the MUX array of the bit width conversion circuit in the prior art, the embodiment provides a transmission delay test method based on an FPGA, as shown in fig. 1, which is a basic flow chart of the transmission delay test method based on the FPGA provided by the embodiment, and the transmission delay test method specifically includes the following steps:
s101, acquiring the current input/output bit width conversion type.
Specifically, in practical applications, in different application scenarios, there are generally different input/output bit width conversion requirements, and the bit width conversion circuit (gecarbox circuit) provided in this embodiment may support multiple different types of input/output bit width conversion, for example, in a preferred embodiment, may be configured to be compatible with 66bit to 32bit,66bit to 16bit, 40bit to 32bit, 40bit to 16bit, and 20bit to 16bit. Although the same bit width conversion circuit is used in different bit width conversion scenarios in this embodiment, the selection of specific functional modules is still required to be associated with specific input/output bit width conversion types.
S102, selecting an input/output valid bit corresponding to an input/output bit width conversion type from a data selector barrel shifter MUX array of a barrel shift structure of a bit width conversion circuit; barrel shifter MUX arrays are configured based on the supported input/output bitwidth transition type for which the MUX array area requirement is greatest among the plurality of input/output bitwidth transition types.
In particular, it should be noted that, in the process of multiplexing data transmission, a circuit capable of selecting any one of them as required is called a data selector, also called a multiplexer or a multi-way switch, and the barrel shifter is a digital circuit capable of shifting a data word by a specific number of bits in one clock frequency period. The barrel shifter may be implemented as a string of data selectors, the output of one of the data selectors being the input to the other data selector, depending on the number of bits to be shifted. While the MUX array of the gecarbox circuit of the present embodiment adopts the barrel shifter structure, in order to meet the multiple bit width conversion requirements, the barrel shifter MUX array in the present embodiment is configured based on the input/output bit width conversion type with the largest MUX array area requirement, so as to meet all the bit width conversion requirements within the largest input/output bit width conversion type, continuing to accept the foregoing examples, and when the barrel shifter MUX array is configured to be compatible with 66bit to 32bit,66bit to 16bit, 40bit to 32bit, 40bit to 16bit, and 20bit to 16bit simultaneously, the barrel shifter MUX array should be configured based on the 66bit to 32bit with the largest MUX array area requirement. For different input/output bit width conversion requirements, the corresponding input/output valid bit needs to be selected in the barrel shifter MUX array for bit width conversion.
Optionally, selecting the input/output valid bit corresponding to the input/output bit width conversion type from the data selector barrel shifter MUX array of the barrel shift structure of the bit width conversion circuit includes: determining an input bit width M, an output bit width N and an address bit width i of an input/output bit width conversion type; the input/output valid bit corresponding to the input/output bit width conversion type is selected from the array of data selectors barrel shifter MUX of the barrel shift structure of the bit width conversion circuit according to M, N and i to perform the current type of input/output bit width conversion by the appropriate MUX array.
Specifically, in one implementation of the present embodiment, the corresponding input/output valid bit is determined based on the input bit width, the output bit width, and the address bit width of the current input/output bit width conversion type.
Optionally, determiningThe input bit width M, the output bit width N, and the address bit width i of the input/output bit width conversion type include: based on correspondence m=n+2 i -1, determining an input bit width M, an output bit width N and an address bit width i of the input/output bit width conversion type.
Specifically, take the example of 66bit to 32bit, where the barrel shifter MUX array outputs do [ N-1:0]The bit width N is 32; while bit0 of the output 32 bits corresponds to bit64 with the highest bit in the input 66 bits, namely the maximum address 64, so as to calculate barrel shifter MUX array address addr [ i-1:0]Bit width i is 7; then, the input di [ M-1:0 ] is calculated according to the output bit width N=32 and the calculated address bit width i=7]Bit width m=32+2 7 -1=159. Of course, in other embodiments, the correspondence between the input bit width M, the output bit width N, and the address bit width i may be other types, and configuring the MUX array of the barre shift structure based on the correspondence in this embodiment may ensure that the circuit area is reduced to the greatest extent possible.
Optionally, address bit addr [ i-1 ] of barrel shifter MUX array]The selection end of the i-1 stage data selector MUX is connected to control the left shift of data by 2 i-1 Bits.
Specifically, based on the barrel shifter MUX array structure provided in this embodiment, in the input bit width M, the corresponding relationship between the output bit width N and the address bit width i is m=n+2 i At-1, the address bit addr [ 0]]Connecting the selection end of the 0 th level MUX, and controlling the data to shift left by 20 bits; address bit addr [1 ]]The selection end of the 1 st-stage MUX is connected, and the control data is shifted left by 2 1 A bit; with such a push, the address bit addr [ i-1 ]]The selection end of the i-1 stage MUX is connected to control the left shift of data by 2 i-1 Bits.
S103, based on the selected input/output valid bit, performing input/output bit width conversion of the input/output bit width conversion type.
It should be noted that, in one implementation of this embodiment, not only the barrel shifter MUX array in the bit width conversion circuit may be multiplexed, but also the same input buffer may be multiplexed, so that the method of this embodiment further includes: selecting an input buffer valid bit corresponding to an input/output bit width conversion type from an input buffer of a bit width conversion circuit; the input buffer is configured based on the largest effective input bit width in the multiple input/output bit width conversion types; based on the selected input/output valid bits of the barrel shifter MUX array, performing an input/output bitwidth conversion of the input/output bitwidth conversion type includes: based on the selected input/output valid bit of the barrel shifter MUX array and the input cache valid bit, an input/output bit width conversion of the input/output bit width conversion type is performed.
Continuing with the foregoing example, in the case where the gecarbox circuit provided in this embodiment is configured to be compatible with 66bit to 32bit,66bit to 16bit, 40bit to 32bit, 40bit to 16bit, and 20bit to 16bit simultaneously, the input buffer din_buf is used to store one beat of 66bit valid input data for the 66bit to 32bit of the largest MUX array area requirement, so din_buf is composed of 66bit registers. It should be appreciated that a beat of valid input data is selectively stored with din_buf, i.e., the input cache valid bits din_buf [65:0] = gbox_di_vldbox_di [65:0]: din_buf [65:0]; the input valid bits of the barrel shifter MUX array select {61'd0, gbox_di [31:0], din_buf [65:0] }; the valid bit of output 32 bits selects do [31:0] of the barrel shifter MUX array. In addition, in all types of bit width conversion of the gecarbox circuit configuration in this embodiment, the input di, the output do and the din_buf valid bit are selected according to the configuration, and the specific reference may be made to table 1:
TABLE 1
| Gecarbox bit width | din_buf valid bit | di significant bit | do valid bit |
| 66bit to 32bit conversion | din_buf[65:0] | di[97:0]＝{gbox_di[31:0],din_buf[65:0]} | do[31:0] |
| 66bit to 16bit conversion | din_buf[65:0] | di[81:0]＝{gbox_di[15:0],din_buf[65:0]} | do[15:0] |
| 40bit to 32bit conversion | din_buf[65:26] | di[97:26]＝{gbox_di[31:0],din_buf[65:26]} | do[31:0] |
| 40bit to 16bit conversion | din_buf[65:26] | di[81:26]＝{gbox_di[15:0],din_buf[65:26]} | do[15:0] |
| 20bit to 16bit conversion | din_buf[65:46] | di[81:46]＝{gbox_di[15:0],din_buf[65:46]} | do[15:0] |
S104, the read-write controller controlling the bit width conversion circuit generates an address bus of the barrel shifter MUX array and outputs a valid indication signal based on the input valid indication signal and the input/output bit width conversion type.
Specifically, the RW Controller combines the input valid indication gbox_di_vld and the bit width conversion configuration, counts the generated barrel shifter MUX array address addr [ i-1:0] and outputs the valid indication gbox_do_vld. The circuit area of the Gecarbox circuit provided by the embodiment is reduced by more than 20% by using a 66bit to 32bit Gecarbox example, and barrel shifter MUX array compared with a traditional MUX array. Meanwhile, for all bit width conversion requirements with input less than or equal to 66bit and output less than or equal to 32bit, the barrel shifter MUX array and the input buffer in the embodiment can be all multiplexed, so that the area of the Gecarbox circuit is greatly reduced.
The invention provides a multiplexing method of a bit width conversion circuit, which comprises the following steps: acquiring the current input/output bit width conversion type; selecting an input/output valid bit corresponding to an input/output bit width conversion type from a barrel shifter MUX array of the bit width conversion circuit; barrel shifter MUX array is configured based on the input/output bit width conversion type with the largest MUX array area requirement among the supported multiple input/output bit width conversion types; performing an input/output bit width conversion of an input/output bit width conversion type based on the selected input/output valid bit; the read/write controller controlling the bit width conversion circuit generates an address bus of the barrel shifter MUX array and outputs a valid indication signal based on the input valid indication signal and the input/output bit width conversion type. By implementing the embodiment of the invention, the MUX of the Gecarbox circuit is configured into a barrel shift structure based on the input/output bit width conversion type with the largest requirement on the MUX array area, and the same barrel shifter MUX array is multiplexed for all the input/output bit width conversions, so that the suitability of the Gecarbox circuit is improved, and the circuit area is effectively reduced.
Embodiment two:
the present embodiment provides a bit width conversion circuit, specifically please refer to a structural schematic diagram of a gecarbox circuit shown in fig. 2, which includes: a data selector barrel shifter MUX array 21 of barrel shift structure and a read-write controller 22 electrically connected with barrel shifter MUX array 21; barrel shifter MUX array 21 is configured based on the input/output bit width conversion type with the largest MUX array area requirement among the supported plurality of input/output bit width conversion types; barrel shifter MUX array 21 is for selecting an input/output valid bit corresponding to a current input/output bit width conversion type and performing an input/output bit width conversion of the input/output bit width conversion type based on the selected input/output valid bit; the read/write controller 22 is configured to generate an address bus of the barrel shifter MUX array and output a valid indication signal based on the input valid indication signal and the input/output bit width conversion type.
In particular, in practical applications, in different application scenarios, there are generally different input/output bit width conversion requirements, and the bit width conversion circuit (gecarbox circuit) provided in this embodiment can support multiple different types of input/output bit width conversion.
It should be noted that in one implementation of this embodiment, not only the barrel shifter MUX array in the bit width conversion circuit can be multiplexed, but also the same input buffer can be multiplexed. Referring to fig. 3, another schematic structure of a gecarbox circuit is shown, where the gecarbox circuit in this embodiment further includes: an input buffer 23 electrically connected to the barrel shifter MUX array 21; the input buffer 23 is configured based on the largest valid input bit width among the plurality of input/output bit width conversion types; the input buffer 23 is used for selecting the input buffer valid bit corresponding to the input/output bit width conversion type, and performing the input/output bit width conversion of the input/output bit width conversion type in cooperation with the barrel shifter MUX array.
In addition, the MUX array of the gecarbox circuit in the present embodiment adopts the barrel shifter structure, and in order to meet the multiple bit width conversion requirements, the barrel shifter MUX array 21 in the present embodiment is configured based on the input/output bit width conversion type with the largest MUX array area requirement, so as to meet all the bit width conversion requirements within the largest input/output bit width conversion type. For different input/output bit width conversion requirements, the corresponding input/output valid bit needs to be selected in the barrel shifter MUX array 21 for bit width conversion.
In a preferred example of this embodiment, the barrel shifter MUX array 21 is also used to determine the input bit width M, the output bit width N, and the address bit width i of the input/output bit width conversion type; the input/output valid bit corresponding to the input/output bit width conversion type is selected from the data selector barrel shifter MUX array 21 of the barrel shift structure of the bit width conversion circuit according to M, N and i.
In a preferred example of this embodiment, the barrel shifter MUX array 21 is also used to determine the correspondence m=n+2 i -1, determining an input bit width M, an output bit width N and an address bit width i of the input/output bit width conversion type. Referring specifically to the schematic structure of barrel shifter MUX array shown in FIG. 4, the output do [ N-1:0 ] of the current I/O bit width conversion type is obtained]The bit width is N, and then the address addr [ i-1:0] is calculated based on N and the input maximum address]The bit width is i, and then N and i are substituted into the corresponding relation to calculate and obtain the input di [ M-1:0 ]]The bit width is M.
Also, in the present embodiment, address bit addr [ i-1 ] of barrel shifter MUX array]The selection end of the i-1 stage data selector MUX is connected to control the left shift of data by 2 i-1 Bits.
With continued reference to fig. 4, in the barrel shifter MUX array structure provided in the present embodiment, the corresponding relationship between the input bit width M, the output bit width N and the address bit width i is m=n+2 i At-1, the address bit addr [ 0]]The selection end of the 0 th level MUX is connected to control the left shift of data by 2 0 A bit; address bit addr [1 ]]The selection end of the 1 st-stage MUX is connected, and the control data is shifted left by 2 1 A bit; with such a push, the address bit addr [ i-1 ]]The selection end of the i-1 stage MUX is connected to control the left shift of data by 2 i-1 Bits.
The present invention provides a bit width conversion circuit, comprising: barrel shifter MUX array and read-write controller connected with barrel shifter MUX array; barrel shifter MUX array is configured based on the input/output bit width conversion type with the largest MUX array area requirement among the supported multiple input/output bit width conversion types; barrel shifter MUX array is used for selecting the input/output valid bit corresponding to the current input/output bit width conversion type and performing the input/output bit width conversion of the input/output bit width conversion type based on the selected input/output valid bit; the read-write controller is used for generating an address bus of the barrel shifter MUX array and outputting a valid indication signal based on the input valid indication signal and the input/output bit width conversion type. By implementing the embodiment of the invention, the MUX of the Gecarbox circuit is configured into a barrel shift structure based on the input/output bit width conversion type with the largest requirement on the MUX array area, and the same barrel shifter MUX array is multiplexed for all the input/output bit width conversions, so that the suitability of the Gecarbox circuit is improved, and the circuit area is effectively reduced.
The foregoing is a further detailed description of the invention in connection with specific embodiments, and it is not intended that the invention be limited to such description. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (10)
1. A multiplexing method of a bit-width conversion circuit, the multiplexing method of the bit-width conversion circuit comprising:
acquiring the current input/output bit width conversion type;
selecting an input/output valid bit corresponding to the input/output bit width conversion type from a data selector barrel shifter MUX array of a barrel shift structure of a bit width conversion circuit; the data selector barrel shifter MUX array is configured based on the input/output bit width conversion type with the largest MUX array area requirement among the supported multiple input/output bit width conversion types;
performing an input/output bit width conversion of the input/output bit width conversion type based on the selected input/output valid bit;
the read/write controller controlling the bit width conversion circuit generates an address bus of the array of data selectors barrel shifter MUX and outputs a valid indication signal based on an input valid indication signal and the input/output bit width conversion type.
2. The multiplexing method of the bit-width conversion circuit according to claim 1, wherein selecting the input/output valid bit corresponding to the input/output bit-width conversion type from the data selector barrel shifter MUX array of the barrel shift structure of the bit-width conversion circuit comprises:
determining an input bit width M, an output bit width N and an address bit width i of the input/output bit width conversion type;
and selecting an input/output valid bit corresponding to the input/output bit width conversion type from the array of data selectors barrel shifter MUX of the barrel shift structure of the bit width conversion circuit according to the input bit width M, the output bit width N and the address bit width i.
3. The multiplexing method of the bit width conversion circuit according to claim 2, wherein the determining the input bit width M, the output bit width N, and the address bit width i of the input/output bit width conversion type includes:
based on correspondence m=n+2 i -1, determining an input bit width M, an output bit width N and an address bit width i of said input/output bit width conversion type.
4. A multiplexing method for a bit width conversion circuit according to claim 3, wherein address bits addr [ i-1 ] of said array of data selectors barrel shifter MUX]The selection end of the i-1 stage data selector MUX is connected to control the left shift of data by 2 i-1 Bits.
5. The multiplexing method of a bit-width conversion circuit according to any one of claims 1 to 4, further comprising: selecting an input cache valid bit corresponding to the input/output bit width conversion type from an input cache of the bit width conversion circuit; the input buffer is configured based on the largest effective input bit width in a plurality of input/output bit width conversion types;
the performing the input/output bit width conversion of the input/output bit width conversion type based on the selected input/output valid bits of the array of data selectors barrel shifter MUX includes:
based on the selected input/output valid bit of the array of data selectors barrel shifter MUX and the input cache valid bit, an input/output bit width conversion of the input/output bit width conversion type is performed.
6. A bit width conversion circuit, comprising: a data selector barrel shifter MUX array of a barrel shift structure and a read-write controller electrically connected with the data selector barrel shifter MUX array; the data selector barrel shifter MUX array is configured based on the input/output bit width conversion type with the largest MUX array area requirement among the supported multiple input/output bit width conversion types;
the array of data selectors barrel shifter MUX is configured to select an input/output valid bit corresponding to a current input/output bit width conversion type and perform an input/output bit width conversion of the input/output bit width conversion type based on the selected input/output valid bit;
the read/write controller is configured to generate an address bus of the array of data selectors barrel shifter MUX and output a valid indication signal based on the input valid indication signal and the input/output bit width conversion type.
7. The bit width conversion circuit of claim 6, wherein the array of data selectors barrel shifter MUX is further configured to determine an input bit width M, an output bit width N, and an address bit width i of the input/output bit width conversion type; and selecting an input/output valid bit corresponding to the input/output bit width conversion type from the array of data selectors barrel shifter MUX of the barrel shift structure of the bit width conversion circuit according to the input bit width M, the output bit width N and the address bit width i.
8. The bit width conversion circuit of claim 6, wherein the array of data selectors barrel shifter MUX further usesBased on the corresponding relation m=n+2 i -1, determining an input bit width M, an output bit width N and an address bit width i of said input/output bit width conversion type.
9. The bit width conversion circuit of claim 8, wherein the address bits addr [ i-1 ] of the array of data selectors barrel shifter MUX]The selection end of the i-1 stage data selector MUX is connected to control the left shift of data by 2 i-1 Bits.
10. The bit-width conversion circuit of any of claims 6 to 9, further comprising: an input buffer electrically connected to the array of data selectors barrel shifter MUX; the input buffer is configured based on the largest effective input bit width in a plurality of input/output bit width conversion types;
the input buffer is used for selecting an input buffer valid bit corresponding to the input/output bit width conversion type, and the input/output bit width conversion of the input/output bit width conversion type is performed in cooperation with the data selector barrel shifter MUX array.
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| CN201811535041.5A CN109818603B (en) | 2018-12-14 | 2018-12-14 | Multiplexing method of bit width conversion circuit and bit width conversion circuit |
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| CN201811535041.5A CN109818603B (en) | 2018-12-14 | 2018-12-14 | Multiplexing method of bit width conversion circuit and bit width conversion circuit |
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