CN109817642B - Thin film transistor array substrate and method of manufacturing the same - Google Patents
Thin film transistor array substrate and method of manufacturing the same Download PDFInfo
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- CN109817642B CN109817642B CN201910056321.6A CN201910056321A CN109817642B CN 109817642 B CN109817642 B CN 109817642B CN 201910056321 A CN201910056321 A CN 201910056321A CN 109817642 B CN109817642 B CN 109817642B
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Abstract
The application provides a thin film transistor array substrate and a manufacturing method thereof, wherein a patterned black polyimide layer is used as a visible light absorption layer, and the patterned black polyimide layer and a patterned insulating layer form a visible light high-reflection medium layer to prevent visible light from irradiating an active layer, and the patterned black polyimide layer and the patterned insulating layer are used as non-conductive layers to prevent parasitic capacitance from being formed between the patterned black polyimide layer and a conductive layer in the thin film transistor array substrate.
Description
Technical Field
The present disclosure relates to the field of thin film transistor technologies, and in particular, to a thin film transistor array substrate and a method for manufacturing the same.
Background
Indium Gallium Zinc Oxide (IGZO) bottom gate Thin Film Transistors (TFTs) are being studied more and more, and their back channels are susceptible to damage in a plasma cutter environment, such as Dry Etching (Dry Etching). The indium gallium zinc oxide Top Gate (Top Gate) TFT has no problem of back channel etching damage, on one hand, a Gate dielectric is positioned above an active layer (indium gallium zinc oxide layer) to play a role in protection, on the other hand, the indium gallium zinc oxide Top Gate TFT realizes self-alignment through front exposure and dry etching, no overlapping area exists, and the process is simple.
However, in a Liquid Crystal Display (LCD) using a top gate TFT structure, an active layer is easily affected by backlight irradiation, and photo-generated carriers thereof affect TFT characteristics, and reliability also significantly attenuates with increasing illumination intensity and time, and especially when a higher mobility active layer is required, a light shielding layer is used in a partial top gate TFT structure design due to the problem of light irradiation on the active layer, that is, a metal layer is deposited under the active layer for light shielding treatment, and then an insulating Buffer (Buffer) layer is deposited. However, the metal light shielding layer and the conductive layer above the metal light shielding layer in the TFT easily form a capacitor structure, which increases parasitic capacitance and affects the performance of the TFT device.
Disclosure of Invention
An object of the present invention is to provide a thin film transistor array substrate and a method for fabricating the same, in which a patterned black polyimide layer and a patterned insulating layer constituting the thin film transistor array substrate can prevent visible light from being irradiated to an active layer and do not form parasitic capacitance with a conductive layer in the thin film transistor array substrate.
In order to achieve the purpose, the technical scheme is as follows.
A method of manufacturing a thin film transistor array substrate, the method comprising:
providing a substrate;
forming a patterned insulating layer and a patterned black polyimide layer, which are sequentially stacked, on the substrate, the patterned insulating layer having a refractive index for visible light greater than the refractive index for visible light of the substrate and the patterned black polyimide layer;
forming an active layer over the patterned black polyimide layer;
a conductive layer is formed over the active layer.
In the above method for manufacturing a thin film transistor array substrate, the forming of the patterned insulating layer and the patterned black polyimide layer sequentially stacked on the substrate includes:
sequentially forming a whole insulating layer and a whole black polyimide layer on the substrate;
and treating the whole insulating layer and the whole black polyimide layer through the same yellow light process to form a patterned insulating layer and a patterned black polyimide layer which are sequentially stacked.
In the above method for manufacturing a thin film transistor array substrate, the patterned insulating layer is a silicon nitride layer or a titanium dioxide layer.
In the above method of manufacturing a thin film transistor array substrate, the thickness of the patterned black polyimide layer is 0.8 to 1.5 micrometers.
In the above method of manufacturing a thin film transistor array substrate, the method further includes: and forming a buffer layer between the patterned black polyimide layer and the active layer.
A thin film transistor array substrate, comprising:
a substrate;
a patterned insulating layer and a patterned black polyimide layer formed on the substrate in a sequential stack, the patterned insulating layer having a refractive index for visible light greater than the refractive index of the substrate and the patterned black polyimide layer for visible light;
an active layer formed over the patterned black polyimide layer;
a conductive layer formed over the active layer.
In the thin film transistor array substrate, a method for preparing a patterned insulating layer and a patterned black polyimide layer, which are sequentially stacked, formed on the substrate includes the steps of:
forming a whole insulating layer and a whole black polyimide layer on the substrate;
and treating the whole insulating layer and the whole black polyimide layer through the same yellow light process to form a patterned insulating layer and a patterned black polyimide layer which are sequentially stacked.
In the thin film transistor array substrate, the patterned insulating layer is a silicon nitride layer or a titanium dioxide layer.
In the thin film transistor array substrate, the thickness of the patterned black polyimide layer is 0.8 to 1.5 micrometers.
In the above thin film transistor array substrate, a buffer layer is disposed between the patterned black polyimide layer and the active layer.
Has the advantages that: the application provides a thin film transistor array substrate and a manufacturing method thereof, wherein a patterned black polyimide layer is used as a visible light absorption layer, and the patterned black polyimide layer and a patterned insulating layer form a visible light high-reflection medium layer to prevent visible light from irradiating an active layer, and the patterned black polyimide layer and the patterned insulating layer are used as non-conductive layers to prevent parasitic capacitance from being formed between the patterned black polyimide layer and a conductive layer in the thin film transistor array substrate.
Drawings
Fig. 1 is a flowchart illustrating a method for manufacturing a thin film transistor array substrate according to an embodiment of the present disclosure;
fig. 2A to 2G are schematic structural views illustrating a process of manufacturing a thin film transistor array substrate according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 1, which is a flowchart of a method for manufacturing a thin film transistor array substrate according to an embodiment of the present application, the method includes the following steps:
s100, providing a substrate;
s101, forming a patterned insulating layer and a patterned black polyimide layer which are sequentially stacked on a substrate, wherein the refractive index of the patterned insulating layer to visible light is larger than that of the substrate and the patterned black polyimide layer to visible light;
s102, forming an active layer above the patterned black polyimide layer;
and S103, forming a conductive layer above the active layer.
The application arranges the patterned insulating layer and the patterned black polyimide layer which are sequentially laminated on the substrate, wherein the refractive index of the patterned insulating layer to visible light is larger than that of the substrate and the patterned black polyimide layer, so that the patterned insulating layer and the patterned black polyimide layer which are sequentially laminated form a high-reflection medium layer, the visible light incident into the substrate is subjected to first reflection on an interface of the substrate and the patterned insulating layer, the visible light incident into the patterned insulating layer is subjected to second reflection on the interface of the patterned insulating layer and the patterned black polyimide layer, and the visible light incident into the patterned black polyimide layer is absorbed by the black polyimide layer, namely, the highly reflective dielectric layer refracts visible light to the side where the backlight source is located, and the black polyimide layer in the highly reflective dielectric layer absorbs the visible light to prevent the visible light from irradiating the active layer. In addition, the patterned insulating layer and the patterned black polyimide layer as a non-conductive layer do not form parasitic capacitance with the conductive layer in the thin film transistor array substrate.
The following description is made in detail with reference to a method for manufacturing a thin film transistor array substrate according to another embodiment.
A manufacturing method of a thin film transistor array substrate includes the steps of:
as shown in fig. 2A, a substrate 10 is provided.
Specifically, a glass substrate is provided. In other embodiments, the substrate 10 may also be a flexible substrate.
As shown in fig. 2B, a patterned insulating layer 11 and a patterned black polyimide layer 12 are formed on a substrate 10 in this order, and the refractive index of the patterned insulating layer 11 to visible light is larger than the refractive index of the substrate 10 and the patterned black polyimide layer 12 to visible light.
Specifically, an entire insulating layer and an entire black polyimide layer are sequentially formed on the substrate 10.
In the present embodiment, the insulating layer is an inorganic insulating layer, and the method of forming the inorganic insulating layer includes, but is not limited to, chemical vapor deposition, plasma enhanced chemical vapor deposition, vacuum evaporation, and low pressure chemical vapor deposition. The insulating layer is a silicon nitride layer or a titanium dioxide layer, and in a preferred embodiment, the insulating layer is a silicon nitride layer. The thickness of the insulating layer is 30 nm-150 nm.
In this embodiment, a black polyimide layer is formed on the insulating layer by coating. The preparation raw materials of the black polyimide layer comprise aromatic diamine, aromatic dianhydride and black organic dye containing two terminal amino groups, or the preparation material of the black polyimide layer comprises polyimide and black filler. The aromatic diamine, the aromatic dianhydride and the black organic dye containing two terminal amino groups can form black polyamic acid through polycondensation, and the black polyamic acid forms black polyimide after imidization (the temperature is about 300 ℃); the polyimide and the black filler are physically blended to form a black polyimide layer, wherein the black filler includes, but is not limited to, carbon black, graphite, metal oxides, and nigrosine.
Next, the entire insulating layer and the entire black polyimide layer are treated by the same photolithography process to form the patterned insulating layer 11 and the patterned black polyimide layer 12, which are stacked.
Since the black polyimide layer has good chemical resistance, chemical stability and high temperature resistance unlike a common black organic layer (e.g., a black matrix layer), it cannot be directly patterned by exposure and development, and these characteristics of the black polyimide layer facilitate its patterning by a photolithography process. The insulating layer and the black polyimide layer are patterned simultaneously through photoresist coating, exposure, development and dry etching in sequence, which has the advantage of simplifying the manufacturing process, and the patterned black polyimide layer 12 prepared through the same yellow light process just covers the patterned insulating layer 11. The patterned insulating layer 11 is a silicon nitride layer or a titanium dioxide layer, and in a preferred embodiment, the patterned insulating layer 11 is a silicon nitride layer. The thickness of the patterned black polyimide layer 12 is 0.8 to 1.5 microns, and the thickness of the patterned black polyimide layer 12 is too thin, which results in too little visible light absorption, and the thickness of the patterned black polyimide layer 12 is too thick for subsequent planarization of the tft array substrate 10.
The refractive index of the silicon nitride layer to visible light is about 1.9, the refractive index of the patterned black polyimide layer to visible light is about 1.6, the refractive index of the glass substrate to visible light is about 1.5, the refractive index of the silicon nitride layer to visible light is larger than the refractive indexes of the patterned black polyimide layer and the glass substrate to visible light, the silicon nitride layer and the patterned black polyimide layer form a high-reflection dielectric layer to reflect visible light emitted by a backlight source, and the black polyimide layer has the function of absorbing visible light.
As shown in fig. 2C, an active layer 13 is formed on the patterned black polyimide layer 12.
Specifically, the semiconductor layer is formed by one of sputter deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, and vacuum evaporation, and the active layer is formed by patterning the semiconductor layer through a photolithography process. The active layer is a single crystal silicon layer, a polycrystalline silicon layer or a metal oxide semiconductor layer. The metal oxide semiconductor layer includes, but is not limited to, indium gallium zinc oxide.
Optionally, a buffer layer 14 is formed between the patterned black polyimide layer 12 and the active layer 13.
Specifically, the buffer layer 14 is formed by one of chemical vapor deposition, plasma enhanced chemical vapor deposition, vacuum evaporation, and low pressure chemical vapor deposition. The buffer layer 14 is an inorganic insulating material including, but not limited to, one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. The buffer layer 14 serves to block ions in the patterned black polyimide layer 12 from entering the active layer 13 to affect the electrical properties of the thin film transistor.
As shown in fig. 2D, a conductive layer 15 is formed over the active layer 13.
Specifically, before forming the conductive layer 15 over the active layer 13, a patterned gate insulating layer 16 needs to be formed on the active layer 13. After the gate insulating layer 16 is formed by one of chemical vapor deposition, plasma enhanced chemical vapor deposition, and vacuum evaporation, the gate insulating layer 16 is patterned by a photolithography process.
Next, a first conductive layer is formed by one of sputtering deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, and vacuum evaporation, and the first conductive layer is patterned by a photolithography process to form the conductive layer 15. The gate insulating layer 16 is a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. The thickness of the gate insulating layer 16 is 1000 a to 2000 a. The conductive layer 15 is a gate electrode made of materials including, but not limited to, molybdenum, aluminum, titanium, copper, and alloys thereof.
After the conductive layer 15 is formed, the conductive layer 15 may be used as a mask to form a source contact region 131 and a drain contact region 132 on the active layer 13 through an ion implantation process, the source contact region 131 and the drain contact region 132 are respectively located at two opposite sides of the conductive layer 15, and the active layer located between the source contact region 131 and the drain contact region 132 is a channel region 133. The vertical projection of the channel region 133 on the substrate 10 completely coincides with the vertical projection of the patterned black polyimide layer 12 on the substrate 10.
As shown in fig. 2E, an interlayer insulating layer 17 having a via hole is formed to cover the conductive layer 15, the active layer 13, and the buffer layer 14.
Specifically, the entire interlayer insulating layer 17 is formed by one of chemical vapor deposition, plasma enhanced chemical vapor deposition, vacuum evaporation, and low pressure chemical vapor deposition, and then the via hole 171 is formed on the entire interlayer insulating layer 17 by a photolithography process, and the via hole 171 is formed on the interlayer insulating layer 17 above the source contact region 131 and the drain contact region 132. The thickness of the entire interlayer insulating layer 17 was 4500-6000 angstroms.
As shown in fig. 2F, source and drain electrodes are formed on the interlayer insulating layer 17, and the source and drain electrodes are in contact with the active layer 13 through the via hole 171 on the interlayer insulating layer 17.
Specifically, a second conductive layer is formed on the interlayer insulating layer 17 and in the via hole thereof by one of sputtering deposition, plasma enhanced chemical vapor deposition, vacuum evaporation, and low pressure chemical vapor deposition, and then the second conductive layer is patterned by a photolithography process to form a source electrode and a drain electrode. The second conductive layer is made of materials including, but not limited to, molybdenum, aluminum, titanium, copper, and alloys thereof.
As shown in fig. 2G, a passivation layer 18 covering the source, drain and interlayer insulating layers 17 and having a via hole and a pixel electrode 19 on the passivation layer 18 are formed, and the pixel electrode 19 is connected to the drain electrode through the via hole on the passivation layer 18.
Specifically, the passivation layer 18 is formed by one of chemical vapor deposition, plasma enhanced chemical vapor deposition, vacuum evaporation and low pressure chemical vapor deposition, and then a via hole is formed on the passivation layer 18 above the drain electrode by a photolithography process.
Then, a whole surface of the ito layer is formed on the surface of the passivation layer 18 and the via hole thereon by sputtering deposition, and a pixel electrode 19 is formed by a photolithography process.
The present application also provides a thin film transistor array substrate manufactured by the above manufacturing method, the thin film transistor array substrate including:
a substrate;
a patterned insulating layer and a patterned black polyimide layer formed on the substrate in a sequential stack, the patterned insulating layer having a refractive index for visible light greater than the refractive index of the substrate and the patterned black polyimide layer for visible light;
an active layer formed over the patterned black polyimide layer;
a conductive layer formed over the active layer.
Further, the method for preparing the sequentially stacked patterned insulating layer and the patterned black polyimide layer formed on the substrate includes the steps of:
forming a whole insulating layer and a whole black polyimide layer on the substrate;
and treating the whole insulating layer and the whole black polyimide layer through the same yellow light process to form a patterned insulating layer and a patterned black polyimide layer which are sequentially stacked.
The patterned insulating layer and the patterned black polyimide layer are manufactured by the same yellow light process, so that the manufacturing process is simplified, and the patterned black polyimide layer is ensured to cover the patterned insulating layer exactly.
Further, the patterned insulating layer is a silicon nitride layer or a titanium dioxide layer. In a preferred embodiment, the patterned insulating layer is a silicon nitride layer.
Further, the thickness of the black polyimide layer is 0.8 to 1.5 micrometers. Too thin a patterned black polyimide layer may result in too little visible light absorption, and too thick a patterned black polyimide layer may be detrimental to subsequent planarization of the tft array substrate.
Further, a buffer layer is disposed between the patterned black polyimide layer and the active layer. The buffer layer serves to block ions in the patterned black polyimide layer from entering the active layer to affect the electrical properties of the thin film transistor.
According to the thin film transistor array substrate, the patterned black polyimide layer is used as the absorption layer of visible light, the patterned black polyimide layer and the patterned insulating layer form the high-reflection medium layer of the visible light to prevent the visible light from irradiating to the active layer, and the patterned black polyimide layer and the patterned insulating layer are used as the non-conductive layers and cannot form parasitic capacitance with the conductive layers in the thin film transistor array substrate.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A method for manufacturing a thin film transistor array substrate is characterized by comprising the following steps:
providing a substrate;
forming a patterned insulating layer and a patterned black polyimide layer, which are sequentially stacked, on the substrate, the patterned insulating layer having a refractive index for visible light greater than the refractive index for visible light of the substrate and the patterned black polyimide layer;
forming an active layer over the patterned black polyimide layer;
a conductive layer is formed over the active layer.
2. The method of manufacturing a thin film transistor array substrate of claim 1, wherein the forming of the patterned insulating layer and the patterned black polyimide layer sequentially stacked on the substrate comprises the steps of:
sequentially forming a whole insulating layer and a whole black polyimide layer on the substrate;
and treating the whole insulating layer and the whole black polyimide layer through the same yellow light process to form a patterned insulating layer and a patterned black polyimide layer which are sequentially stacked.
3. The method of claim 1, wherein the patterned insulating layer is a silicon nitride layer or a titanium dioxide layer.
4. The method of claim 1, wherein the patterned black polyimide layer has a thickness of 0.8 to 1.5 μm.
5. The method of manufacturing a thin film transistor array substrate of claim 1, further comprising the steps of: and forming a buffer layer between the patterned black polyimide layer and the active layer.
6. A thin film transistor array substrate, comprising:
a substrate;
a patterned insulating layer and a patterned black polyimide layer formed on the substrate in a sequential stack, the patterned insulating layer having a refractive index for visible light greater than the refractive index of the substrate and the patterned black polyimide layer for visible light;
an active layer formed over the patterned black polyimide layer;
a conductive layer formed over the active layer.
7. The thin film transistor array substrate of claim 6, wherein the method for preparing the sequentially stacked patterned insulating layer and patterned black polyimide layer formed on the substrate comprises the steps of:
forming a whole insulating layer and a whole black polyimide layer on the substrate;
and treating the whole insulating layer and the whole black polyimide layer through the same yellow light process to form a patterned insulating layer and a patterned black polyimide layer which are sequentially stacked.
8. The thin film transistor array substrate of claim 6, wherein the patterned insulating layer is a silicon nitride layer or a titanium dioxide layer.
9. The thin film transistor array substrate of claim 6, wherein the patterned black polyimide layer has a thickness of 0.8-1.5 microns.
10. The thin film transistor array substrate of claim 6, wherein a buffer layer is disposed between the patterned black polyimide layer and the active layer.
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| CN101324733B (en) * | 2008-08-04 | 2013-05-08 | 京东方科技集团股份有限公司 | Electronic paper active substrate and manufacturing method thereof as well as electronic paper display screen |
| WO2017073321A1 (en) * | 2015-10-26 | 2017-05-04 | ソニー株式会社 | Solid-state imaging device, manufacturing method therefor and electronic device |
| JP2018081815A (en) * | 2016-11-16 | 2018-05-24 | 株式会社ジャパンディスプレイ | Display device |
| CN107170748B (en) * | 2017-04-20 | 2019-11-08 | 上海天马微电子有限公司 | A kind of array substrate, display panel and display equipment |
| CN108878537B (en) * | 2017-05-12 | 2021-02-12 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method thereof, display panel and display device |
| CN107611032A (en) * | 2017-08-21 | 2018-01-19 | 北京大学深圳研究生院 | Thin film transistor (TFT) comprising light shield layer and preparation method thereof |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |