CN107611032A - Thin film transistor (TFT) comprising light shield layer and preparation method thereof - Google Patents
Thin film transistor (TFT) comprising light shield layer and preparation method thereof Download PDFInfo
- Publication number
- CN107611032A CN107611032A CN201710717954.8A CN201710717954A CN107611032A CN 107611032 A CN107611032 A CN 107611032A CN 201710717954 A CN201710717954 A CN 201710717954A CN 107611032 A CN107611032 A CN 107611032A
- Authority
- CN
- China
- Prior art keywords
- layer
- light shield
- tft
- active layer
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
This application discloses a kind of thin film transistor (TFT), including substrate；Formed over the substrate through patterned light shield layer, wherein the light shield layer uses insulated non-metal light screening material；The active layer formed more than the light shield layer, the active layer include raceway groove, source region and the drain region of the transistor；Gate electrode of the gate dielectric layer and formation formed on the active layer on the gate dielectric layer；And form the passivation layer on the active layer and the gate electrode.Present invention also provides the method for preparing this thin film transistor (TFT).
Description
Technical field
The application is related to thin film transistor (TFT) technology of preparing, more particularly to a kind of thin film transistor (TFT) comprising light shield layer and its
Preparation method.
Background technology
Display Technique and industry are one of most potential fields of current information technology and industry.Display Technique
Core is thin film transistor (TFT) (TFT) technology, FPD such as liquid crystal display (the Liquid Crystal of active array addressing mode
Display, LCD), organic light-emitting diode display (Organic Light-Emitting Diode, OLED) all rely on TFT
Control and driving.
Peripheral driver is realized with the continuous improvement of monitor resolution, frame frequency, or even using TFT, to TFT driving energy
Power requires more and more higher, and high mobility oxide TFT research more and more attracts attention.On the other hand, when TFT is used to have
During the new displays such as source matrix Organic Light Emitting Diode (AMOLED), to its requirement of long-time stability under gate stress more
Height, the device for now preparing high stability are particularly important.
For device architecture, two kinds of structures of TFT generally uses bottom gate and top-gated at present.For bottom grating structure, grid
Overlapping between source/drain is introduced into larger parasitic capacitance, so as to limit its application in fast circuit.Relative to bottom gate
Structure devices, the thin film transistor (TFT) of top-gated self-alignment structure, there is the shadow that technique is simple, can effectively reduce parasitic capacitance with it
The features such as ringing, being easy to device size to minimize, makes people scintillating, receives extensive concern.
For autoregistration top gate structure device, its existing urgent problem to be solved is：It is by ambient light
Influenceing greatly, the basic electricity characteristic of device changes greatly in the case where there is ambient light irradiation, meanwhile, the reliability and power consumption of device also can
It is affected by ambient light.
For this problem, currently employed main method is that layer of metal is deposited above substrate as light shield layer, then
One layer of gate dielectric layer is deposited above light shield layer as metallic spacer, this metallic spacer is that dielectric is used for light shield layer
Separated with active layer.Although such method solves influence of the ambient light to device to a certain extent, also due to metal
Light shield layer has conductive characteristic, need to be connect a fixed potential.If not connecing fixed potential, increase floating node, introduce
Capacitance Coupled, cause circuit unstable；If increasing the fixed potential, the complexity and power consumption of circuit can be increased.
The content of the invention
This application provides a kind of thin film transistor (TFT), including substrate；Formed over the substrate through patterned shading
Layer, wherein the light shield layer uses insulated non-metal light screening material；The active layer formed more than the light shield layer, it is described active
Layer includes raceway groove, source region and the drain region of the transistor；The gate dielectric layer formed on the active layer and formation are in the grid
Gate electrode on dielectric layer；And form the passivation layer on the active layer and the gate electrode.
Particularly, the thin film transistor (TFT) also includes the isolation of the insulation formed between the light shield layer and the active layer
Layer.
Particularly, the insulated non-metal material include non-hydrogenated non-crystalline silicon, coloured unitary/metal composite oxide and/
Or black organic material.
Particularly, the thickness of the non-hydrogenated amorphous silicon material is 50nm~200nm, the coloured unitary/composition metal
The thickness of oxide material is 50nm~200nm, and the thickness of the black organic material is 0.5~3 μm.
Particularly, the separation layer includes silica, silicon nitride, aluminum oxide and/or polyimides.
Present invention also provides a kind of thin film transistor (TFT), including substrate；Form gate electrode over the substrate；Formed
Gate dielectric layer on the gate electrode and the substrate；The active layer on the gate dielectric layer is formed, the active layer includes
Raceway groove, source region and the drain region of the transistor；The source/drain contact electrode formed on the active layer；Formed in the source/drain
Contact the passivation layer on electrode and the active layer；And formed on the passivation layer through patterned light shield layer, wherein
The light shield layer uses insulated non-metal light screening material.
Particularly, the insulated non-metal light screening material includes non-hydrogenated non-crystalline silicon, coloured unitary/metal composite oxide
And/or black organic material.
Particularly, the thickness of the non-hydrogenated amorphous silicon material is 50nm~200nm, and coloured unitary/composition metal aoxidizes
The thickness of thing material is 50nm~200nm, and the thickness of the black organic material is 0.5~3 μm.
Present invention also provides a kind of method for preparing thin film transistor (TFT), is included on substrate and forms light shield layer and it is entered
Row is graphical, wherein the light shield layer uses insulated non-metal light screening material；In light shield layer active layer formed above；Institute
State and deposit gate dielectric layer and gate electrode on active layer successively；Source region and leakage are formed in the active layer of the gate electrode both sides
Area；And form passivation layer on the active layer and the gate electrode.
Particularly, this method is additionally included in the separation layer that insulation is formed between the light shield layer and the active layer.
Present invention also provides a kind of method for preparing thin film transistor (TFT), is included on substrate and forms gate electrode layer and to it
It is patterned to form gate electrode；Gate dielectric layer is formed on the gate electrode；Active layer is formed on the gate dielectric layer；
Source/drain contact electrode is formed on the active layer；Contacted in the source/drain and form passivation layer on electrode and the active layer；
And light shield layer and graphical to its is formed on the passivation layer, wherein the light shield layer uses insulated non-metal lightproof material
Material.
What the application proposed is particularly scheme of the non-hydrogenated non-crystalline silicon as light shield layer using insulated non-metal material no matter
It is to be directed to top-gated device or bottom-gate device, ambient light can be effectively isolated, and need to lead to unlike metal light shield layer
Fixed potential, so reduce the lithography step that perforate is drawn, for the technique using metal light shield layer
20% efficiency can be improved.Meanwhile for top-gated device for, being introduced into also reduce in subsequent process steps of separation layer hides
The pollution that photosphere is brought to device.This method step of preparation process compared with the metallic spacer structure used instantly is simple,
Influence of the ambient light to thin film transistor (TFT) is effectively reduced on the premise of device performance is not influenceed.
Detailed description hereinafter with reference to accompanying drawing to the exemplary embodiment of the application.
Brief description of the drawings
It is combined in the description and the accompanying drawing of a part for constitution instruction shows embodiments herein, and even
It is used for the principle for explaining the application together with its explanation.
Fig. 1 a to Fig. 1 k are the process flow diagram for preparing thin film transistor (TFT) according to the application one embodiment；
Fig. 2 is the flow chart according to the method for preparing thin film transistor (TFT) of the application one embodiment.
Fig. 3 a to Fig. 3 g are the process flow diagram for preparing thin film transistor (TFT) according to another embodiment of the application；
Fig. 4 is the flow chart according to the method for preparing thin film transistor (TFT) of another embodiment of the application；And
Fig. 5 is the non-hydrogenated non-crystalline silicon light transmittance of different-thickness with the change schematic diagram of wavelength.
Embodiment
Each exemplary embodiment of the application is described in detail hereinafter with reference to accompanying drawing.It should be noted that unless have in addition
Body illustrates that the unlimited system of part and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
The scope of application.
The description only actually at least one exemplary embodiment is illustrative below, not as to this Shen
Please and its application or any restrictions that use.
It may be not discussed in detail for technology, method and apparatus known to person of ordinary skill in the relevant, but suitable
In the case of, the technology, method and apparatus should be considered as part for specification.
In shown here and discussion all examples, any occurrence should be construed as merely exemplary, without
It is as limitation.Therefore, other examples of exemplary embodiment can have different values.
It should be noted that similar label and letter represent similar terms in following accompanying drawing, therefore, once a certain item exists
It is defined, then it need not be further discussed in subsequent accompanying drawing in one accompanying drawing.
For material, thin film transistor (TFT) can use oxide semiconductor, polysilicon or other materials as active layer.
When using oxide semiconductor as active layer, oxide semiconductor can include Zinc oxide-base and indium oxide sill,
Including zinc oxide (ZnO), indium oxide (In2O3), aluminium mix zinc oxide (AZO), boron doping zinc-oxide (BZO), mg-doped zinc oxide
(MZO), indium gallium zinc (IGZO), gallium oxide zinc (GZO), tin indium oxide (ITO), tin oxide (SnO2), stannous oxide (SnO)
With cuprous oxide (Cu2O) etc..
This application provides a kind of thin film transistor (TFT) and the method for preparing the semiconductor thin-film transistor.
The present patent application is described in detail with reference to the accompanying drawings and examples.
Fig. 1 a to Fig. 1 k are the process flow diagram for preparing top-gate thin-film transistors according to the application one embodiment.
As shown in figure 1k, the thin film transistor (TFT) has substrate 102, forms light shield layer 104 on the substrate 102, is formed
Separation layer 106 on light shield layer 104, the active layer 108 formed on separation layer 106 (including source region 1082 and drain region
Domain 1084), gate dielectric layer 110 and 112 (can certainly be one layer of gate medium) and the grid electricity being sequentially formed on active layer 108
Pole 114, the passivation layer 120 formed on active layer 108 and gate electrode 114, and contact electrode 122,124 and 126.
If source electrode and drain electrode are formed according to the method that one embodiment is spread using Al, then gate electrode 114 with it is blunt
Also include layer of metal oxide such as Al between change layer 1202O3Film 118.The thin of the application one embodiment is described below
During the preparation method of film transistor, this layer film will be specifically introduced.Certainly, can also other modes be used to reduce source/drain
Resistivity.When method as use, then metal-oxide film 118 may not be present.
Fig. 2 is the flow chart according to the method for preparing thin film transistor (TFT) of the application one embodiment.
In S202, as shown in Figure 1a, one layer of light shield layer 104 can be deposited on the substrate 102 first, as shown in Figure 1 b to hiding
Photosphere 104 is patterned.Substrate 102 can use the transparent materials such as glass substrate or flexible substrate.
Currently when light shield layer is prepared, metal material is still used, although metal material there may be a series of lack
Fall into.Because nonmetallic materials are all much transparent first, secondly light-proofness is not to thin film transistor (TFT) light shield layer material
The sole requirement of material.To also need to meet following a series of requirement as light screening material.Find such material energy simultaneously
Enough apply it in the preparation process of thin film transistor (TFT), and the device performance of thin film transistor (TFT) do not had a negative impact,
Be conventional art can not and.At present, in the industry still to continue to use processing step complicated and have influence to device performance
Metal light shield layer.
First, the nonmetallic materials as light shield layer will have good light-proofness.It is preferable shape that all band, which is blocked,
State.But since the light of red band is relatively small on the influence of TFT transistor performances, therefore it is used as thin film transistor (TFT) shading
The nonmetallic materials of layer will can at least shelter from the light of green and blue wave band, that is, wavelength is in below 600nm light
Line.
Secondly, as shading layer material, its physical and chemical performance will be stablized.Because the preparation process of light shield layer is in device
Before other layer materials are formed, therefore after prepared by light shield layer, it is also necessary to undergo the long period, (temperature is most for higher temperature
It is high up to 300 DEG C or so) operating procedure.During such long heat treatment, it is desirable to the physical chemistry of light shield layer
Matter will be stablized, it is impossible to diffusion is produced because of heating so as to be had undesirable effect to device performance.
In addition, the resistivity as the nonmetallic materials of light shield layer will reach more than certain level, to prevent due to shading
Layer is conductive and influences the performance of device.Certainly, " insulation " so-called in the application is not required for resistivity and reaches conventional electrical determining
It is more than 10 in justice9Ω * cm level, as long as more than 105It is so-called in the application " exhausted that Ω * cm resistivity level can meets
The requirement of edge ", i.e., substantially non-electrically conducting requirement.
Also, shading layer material be able to will be patterned immediately.Light shield layer is grown on whole glass or flexible base board, and substrate exists
To reach transmitance as high as possible in addition to device area, therefore, the light shield layer outside TFT device areas is required for passing through figure
Change operation to be removed.
In addition, light shield layer thickness is also important parameter, light shield layer thickness is excessive easily to form step in device region, especially
It is for top-gated device, such step can directly affect the fundamental characteristics of device.And different light screening materials is directed to, fit
The light shield layer thickness of conjunction is also different.
In order to solve the problems, such as existing metal light shield layer, applicant is for nonmetallic materials and the characteristic of thin film transistor (TFT)
Substantial amounts of research has been carried out, has been carried out in selection shading layer material and by situation of the selected materials application in thin film transistor (TFT)
A series of experiments, to prepare the light shield layer that can meet a series of above-mentioned requirements.
According to one embodiment, a kind of shading layer material that disclosure satisfy that above-mentioned requirements can be amorphous silicon material.Above
The light of green and blue wave band will can at least be sheltered from as the nonmetallic materials of thin film transistor (TFT) light shield layer by speaking of.Such as figure
Shown in 5, for wavelength below 600nm blue light and green glow, transmitance as little as 10%, the 150nm of non-crystalline silicon thick 100nm with
The transmitance of the non-crystalline silicon of upper thickness is just already close to for zero.In addition, for example, the light for wavelength for such as 525nm,
The thickness and transmitance of non-crystalline silicon can be with as shown in the table
| Amorphous silicon thickness (nm) | Transmitance |
| 50 | 31.2% |
| 100 | 9.9% |
| 150 | 3.2% |
| 200 | 0.8% |
Table 1
From this example, amorphous silicon membrane thickness is thicker, and the following film transmission rates of wavelength 600nm are lower.From conjunction
Suitable thickness, such as the non-crystalline silicon that thickness is more than 100nm can effectively below absorbing wavelength 600nm blue lights and green glow.Although
As shown in the chart, do not have thickness in 100nm for the light that wavelength is below 600nm, the transmitance of non-crystalline silicon thick 50nm
Above non-crystalline silicon is preferable like that, but for specific thin film transistor (TFT), stops most of ultraviolet can and meet
It is required that so as to avoid the influence to device performance.Furthermore, it is contemplated that the size of device, light shield layer 104 can not possibly be too thick, therefore can
To use non-crystalline silicon of the thickness as such as 50nm-200nm to be used as light shield layer.
In addition it is critically important, should also be non-hydrogenated for the non-crystalline silicon as light shield layer.Because using tradition
PECVD methods formed non-crystalline silicon in can contain substantial amounts of hydrogen, if use as amorphous silicon material as light shield layer
Words, in the follow-up preparation process of device, hydrogen is possible to be diffused into device other materials layer and cause device performance negative shadow
Ring.
According to one embodiment, non-hydrogenated non-crystalline silicon can be formed using the method for low-temperature sputter, or according to other
Embodiment can also use the method for electron beam evaporation to form non-hydrogenated non-crystalline silicon.
According to another embodiment of the application, light shield layer 104 can use coloured unitary/metal composite oxide, for example,
The composite oxides of the nonferrous metal oxides such as chromium oxide, sub- titanium oxide and its composition.According to one embodiment, coloured unitary/
The thickness of metal composite oxide light shield layer or non-crystalline silicon light shield layer can be 50nm~200nm as needed.According to a reality
Example is applied, in the case where light shield layer 104 is using coloured unitary/metal composite oxide, electron beam evaporation, sputtering etc. can be used
Technology forms light shield layer 104 on the substrate 102.
According to another embodiment, light shield layer 104 can use black organic material, such as organic substrate (such as Ethylcellulose
Acid, it is poly- to stupid dicarboxylic acid ethyl ester alcohol (PET), polystyrene (PS), polyethers, polyimides, makrolon (PC), epoxy resin,
Phenoxy resin, polyether sulfone (PES), polyacrylate etc.) add black particles (such as carbon black, copper, cobalt, manganese, chromium, titanium oxide
And its composite oxide particle formed).According to another embodiment, the thickness of black organic material light shield layer is as needed
It can be 2~3 μm.According to another embodiment, in the case where light shield layer 104 is using black organic material, rod can be used to apply
The technologies such as method, spin coating method, spray application method, ink-jet method, screen painting are covered to form light shield layer 104 on the substrate 102.
According to one embodiment, after light shield layer 104 is deposited on the substrate 102, photoetching and etching can be carried out to it,
So as to graphical to light shield layer 104.According to one embodiment, for non-hydrogenated non-crystalline silicon light shield layer, reactive ion can be used to carve
The method for losing (RIE) realizes the graphical of light shield layer.
It should be understood that Fig. 1 a are illustrated that the operation carried out to individual devices structure, therefore merely illustrate to light shield layer
Graphical operation；And in actual fabrication process, it is the deposit that light shield layer is carried out on whole panel, and TFT devices are removed on panel
Greater area of pixel electrode area outside part region also be present, this region is to need complete printing opacity, the purpose of photoetching be by
The light shield layer in these regions removes.
Although non-hydrogenated non-crystalline silicon, coloured unitary/metal composite oxide, and/or black organic material three are enumerated herein
Kind light shield layer can be not limited to these three materials as insulation light screening material as the material of light shield layer.Before disclosure satisfy that
State and the insulated non-metal material of light shield layer requirement is likely to be applicable.But some it is nonmetallic be not appropriate for it is brilliant as film
The shading layer material of body pipe, such as amorphous carbon, its heat endurance is poor, and electric conductivity is strong, device can be polluted, influence device
Energy.
It is selectable, in S204, as illustrated in figure 1 c, one layer of separation layer 106 can be deposited on light shield layer 104.
For TFT devices, active layer raceway groove is very sensitive to impurity such as hydrogen, metal ion etc., and extremely micro is miscellaneous
Confrontation device performance can all cause very big influence.For the light shield layer 104 that insulate, even if fine again select and strict again
Preparation condition, inevitably can also introduce a small amount of impurity.Thus, separation layer is just particularly important.
For separation layer 106, still there is certain difficulty in it in selection and preparation.First, its material is with having
Active layer needs to form good contact, if separation layer flatness and surface roughness do not reach requirement, or with active interlayer contact
It is bad with the presence of compared with defect modes, then the mobility of device can be greatly reduced, and basic electricity characteristic can be affected.
Secondly, also it is worthy of careful study greatly in the selection of material and preparation technology, the separation layer required for the embodiment of the present application is
One layer of compactness is good, and good insulating, heat endurance and chemical stability are good, the few film of the impurity content such as hydrogen and metal ion.
At the same time, separation layer will also have good exclusion of water, the ability of oxygen.Reach above-mentioned requirements, not only in material selection
It there are certain requirements, be also required to optimize in preparation technology.
Therefore, insulation dielectric can be used according to one embodiment, separation layer 106, for example, silica (SiO2), nitridation
Silicon (SiNx), aluminum oxide (Al2O3) and/or polyimides.Other high temperature resistants and good organic of flatness can certainly be used
Or inorganic insulating material.
According to one embodiment, if separation layer 106 uses aluminum oxide, the thickness of separation layer 106 can be 30nm~
50nm；If separation layer 106 uses silica or silicon nitride, the thickness of separation layer 106 can be 100nm~300nm.
According to different embodiments, can be formed using technology of plasma reinforced chemical vapour deposition (PECVD) etc.
As the silicon nitride or silica of separation layer 106, aluminum oxide of the method formation of sputtering as separation layer 106 can be used,
Spin coating can be used to add the method for baking to form the polyimides as separation layer 106.
Certainly, if the flatness of light shield layer 104 is fine, and device other materials layer is not polluted, can also not
Using separation layer 106.
In S206, as shown in Figure 1 d, one layer of active layer 108 is deposited in active layer 104 or on separation layer 106, and to it
It is patterned.According to the embodiment of one, if there is no step S204, that is, do not need separation layer 106 if, Ke Yi
Step S206 is patterned using patterned active layer to light shield layer 104, so can further simplify lithography step.
According to one embodiment, active layer 108 can use oxide semiconductor material, such as indium gallium zinc oxide
(IGZO), aluminium zinc oxide (AZO), indium-zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), aluminium mix zinc oxide
(AZO), boron doping zinc-oxide (BZO), mg-doped zinc oxide (MZO) etc..
According to another embodiment, active layer 108 can also use polysilicon.
According to one embodiment, the thickness of active layer 108 can be 20nm~60nm, particularly 40nm as needed.
According to one embodiment, active layer 108 can be formed using magnetron sputtering technique etc..
It is selectable, in S208, plasma treatment can be carried out to active layer 108.
In one embodiment, the plasma treatment utilizes plasma enhanced chemical gas using oxygen-containing (O) plasma
The mutually technology such as deposition.Plasma gas containing O is oxygen (O2), nitrogen oxide (N2O) the plasma containing O of contour activation energy.
In S210, as shown in Fig. 1 e and 1f, double layer gate dielectric layer 110,112 and grid electricity are deposited successively on active layer 108
Pole layer 114.It is of course also possible to use the gate dielectric layer for the individual layer that homogenous material is formed.
According to one embodiment, double layer gate dielectric layer includes lower temperature gate dielectric layer 110 and higher temperature gate dielectric layer
112.According to one embodiment, lower temperature gate dielectric layer 110 and higher temperature gate dielectric layer 112 can use silicon nitride (SiNx)
And/or silica (SiOx) etc., using plasma enhancing chemical vapor deposition (PECVD) method is formed.
According to one embodiment, the growth temperature of lower temperature gate dielectric layer 110 is room temperature to 150 DEG C, especially can be
150 DEG C, thickness can be that 50~200nm, particularly thickness are 100nm；The growth temperature of higher temperature gate dielectric layer 112 can be with
For 200 DEG C~300 DEG C, particularly 300 DEG C, thickness can be that 50~200nm, particularly thickness are 100nm.
According to one embodiment, gate electrode layer 114 can use metal or non-metallic conducting material, for example, molybdenum, chromium, titanium, aluminium
Deng metal, the non-metallic conducting material such as tin indium oxide (ITO), aluminium-doped zinc oxide (AZO) and boron doping zinc-oxide (BZO), its
Can be the composite conductive layers of homogenous material conductive layer or bilayer or multilayer conductive material composition.It can be splashed using magnetic control
Penetrate, the technology such as electron beam evaporation or thermal evaporation forms gate electrode layer 114 on higher temperature gate dielectric layer 112.According to a reality
Example is applied, the thickness of gate electrode layer 114 can be 50nm~300nm, particularly 150nm.
In S212, as shown in Figure 1 g, double layer gate dielectric layer 110,112 and gate electrode layer 114 can be patterned.It can adopt
With the continuous photoetching of RIE and gate electrode layer 114 is etched with gate dielectric layer 110 and 112 to form gate electrode.
In S214, as shown in figure 1h, one layer of reacting metal layer can be deposited on the gate dielectric layer and gate electrode after graphical
116。
According to one embodiment, reacting metal layer 116 can use metallic aluminium (Al).The thickness of metallic aluminium (Al) can be 1~
6nm, particularly thickness are 3nm.According to one embodiment, DC sputtering can be used to deposit one layer of thin Al.It is of course also possible to adopt
The metal that can form source electrode and drain electrode in active layer by being diffused in by the use of other is used as the material of reacting metal layer 116.
In S216, as shown in figure 1i, device is made annealing treatment.
According to one embodiment, the annealing can use 200~300 DEG C of annealing conditions, promote in oxygen atmosphere
Such as metal Al is diffused into the active layer 108 not covered by gate electrode and gate dielectric layer, to form source region 1082 and drain region
1084, to reach the purpose for reducing source region and drain region resistivity.In addition, according to one embodiment, the top layer of reacting metal layer 116
Oxide Al can be oxidized to form2O3Film 118, plays passivation.
Certainly, except the above method, other method can also be used to realize the purpose for the resistivity for reducing source region and drain region.
In the case where adopting and being formed by other methods source region and drain region, sull 118 may not be included in device.
S218, as shown in fig. ij, passivation layer 120 can be formed on gate dielectric layer, active layer and gate electrode.
According to one embodiment, passivation layer 120 can use silicon nitride (SiNx) and/or silica (SiOx).According to a reality
Apply example, can using plasma strengthen chemical vapor deposition (PECVD) method under conditions of such as 150 DEG C over the entire substrate
Side's deposit passivation layer 122.According to one embodiment, the thickness of passivation layer 120 can be 100nm~300nm, particularly 200nm.
In S220, as shown in figure 1k, the contact hole 122,124 and 126 of each electrode is formed.
According to one embodiment, the contact hole 122,124 and 126 of each electrode can be formed by photoetching and etching.
According to one embodiment, conductive layer can use metal or metal conductive oxide film.Metal may include molybdenum,
Chromium, titanium, aluminium etc., metal conductive oxide film may include tin indium oxide (ITO), aluminium-doped zinc oxide (AZO), boron doping oxidation
Zinc (BZO) etc..
According to one embodiment, in the case of using metal as conductive layer, magnetron sputtering, electron beam evaporation can be used
Or thermal evaporation method forms conductive layer.
According to another embodiment, in the case of using metal oxide as conductive layer, magnetron sputtering or light can be used
The methods of learning plated film forms conductive layer.Metal or metal conductive oxide film can be monolayer material or bilayer
Or the composite conducting layer material of multilayer conductive material composition.
The thin film transistor (TFT) that the embodiment of the present application provides, using insulation light screening material as light shield layer, it can effectively reduce ring
Influence of the border light to device performance, but the application of current potential light shield layer need not be fixed, do not increase device architecture complexity journey
Degree, simplifies process flow steps, efficiency amplitude may be up to 20%, and device performance is not also had a negative impact.It is meanwhile logical
Setting separation layer is crossed, light shield layer further can be effectively reduced and influence of the pollution to device performance is introduced to device.
Fig. 3 a to Fig. 3 g are the process flow diagram for preparing bottom gate thin film transistor according to another embodiment of the application.
Stop although the presence that bottom gate thin film transistor has bottom gate may be constructed to form bottom device incident ray, top device
Ambient light still be possible to have undesirable effect device performance.It is not corresponding in current bottom gate thin film transistor
Structure suppresses to this problem.
As shown in figure 3g, the thin film transistor (TFT) has substrate 302, the gate electrode 304 formed on substrate 302, is formed
Gate dielectric layer 306 on gate electrode 304, the active layer 308 formed on the gate dielectric layer 306, active layer 308 include described
Raceway groove, source region and the drain region of transistor, the source/drain contact electrode 310 and 312 formed on active layer 308, are formed
Passivation layer 314 on source/drain contact electrode 310 and 312 and active layer 308, the light shield layer 316 formed on passivation layer 314,
And extraction electrode opening 318 and 320.
The bottom gate thin film transistor for preparing according to the application another embodiment is described below in conjunction with Fig. 3 a to Fig. 3 g
Method.Fig. 4 is the flow chart according to the method for preparing bottom gate thin film transistor of another embodiment of the application.
In S402, as shown in Figure 3 a, one layer of gate electrode layer can be deposited first on substrate 302, and gate electrode layer is entered
Go graphically to form gate electrode 304.
According to one embodiment, gate electrode 304 can use metal or non-metallic conducting material, for example, molybdenum, chromium, titanium, aluminium etc.
The non-metallic conducting material such as metal, tin indium oxide (ITO), aluminium-doped zinc oxide (AZO) and boron doping zinc-oxide (BZO), it can
To be composite conductive layers that homogenous material conductive layer or bilayer or multilayer conductive material form.Can use magnetron sputtering,
The technology such as electron beam evaporation or thermal evaporation forms gate electrode layer 308 on separation layer 306.According to one embodiment, gate electrode layer
Thickness is 50nm~300nm, particularly 150nm.
According to one embodiment, can on gate electrode layer spin coating photoresist, using the continuous photoetching of RIE and etching gate electrode
Layer forms gate electrode 304.
In S404, as shown in Figure 3 b, one layer of gate dielectric layer 306 can be deposited on gate electrode 304.
According to one embodiment, gate dielectric layer 306 can use silicon nitride (SiNx) and/or silica (SiOx) etc., using etc.
Gas ions enhancing chemical vapor deposition (PECVD) method is formed.
According to one embodiment, the growth temperature of gate dielectric layer 306 for 150 DEG C~300 DEG C, particularly 300 DEG C, thickness can
Think 50-200nm, particularly can be 200nm.
In S406, as shown in Figure 3 c, one layer of active layer 308 can be deposited on gate dielectric layer 306, and figure can be carried out to it
Shape.
According to one embodiment, active layer 308 can use oxide semiconductor material, such as indium gallium zinc oxide
(IGZO), aluminium zinc oxide (AZO), indium-zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), aluminium mix zinc oxide
(AZO), boron doping zinc-oxide (BZO), mg-doped zinc oxide (MZO) etc..
According to another embodiment, active layer 308 can use polysilicon.
According to one embodiment, the thickness of active layer 308 can be 20nm~60nm, particularly 40nm as needed.
According to one embodiment, magnetron sputtering technique etc. can be used to form active layer 308 in gate dielectric layer 306
On.
In S408, as shown in Figure 3 d, one layer of conductive layer can be deposited on active layer 308, and to its graphical formation source/
Miss touched electrode 310 and 312.
According to one embodiment, source/drain contact electrode 310 and 312 can use metal or non-metallic conducting material, for example,
The metals such as molybdenum, chromium, titanium, aluminium, tin indium oxide (ITO), aluminium-doped zinc oxide (AZO) and boron doping zinc-oxide (BZO) etc. are nonmetallic
Conductive material, it can be the composite conductive layers of homogenous material conductive layer or bilayer or multilayer conductive material composition.Can
Source/drain contact electrode 310 and 312 is formed on active layer 308 using technologies such as magnetron sputtering, electron beam evaporation or thermal evaporations.
According to one embodiment, the source/drain contact thickness of electrode 310 and 312 can be 50nm~300nm, particularly 150nm.
In S410, form bottom gate thin film contact hole and annealed.Specifically, annealing atmosphere can be vacuum, N2Gas, O2
Gas, preferably O2Gas, temperature are 150 DEG C~300 DEG C, preferably 250 DEG C.
In S412, as shown in Figure 3 e, it is blunt one layer of deposit on electrode 310 and 312 and active layer 308 can be contacted in source/drain
Change layer 314, and annealed.
According to one embodiment, passivation layer 314 can use silicon nitride (SiNx) and/or silica (SiOx).According to a reality
Apply example, can using plasma strengthen chemical vapor deposition (PECVD) method under conditions of such as 150 DEG C over the entire substrate
Side's deposit passivation layer 314.According to one embodiment, the thickness of passivation layer 314 can be 100nm~300nm, particularly 200nm.
Specifically, annealing atmosphere is vacuum, N2Gas, O2Gas, preferably O2Gas, temperature are 150 DEG C~300 DEG C, are preferably
250℃。
In S414, as illustrated in figure 3f, one layer of light shield layer 316 can be deposited on passivation layer 314.
According to one embodiment, a kind of shading layer material that disclosure satisfy that above-mentioned requirements can be amorphous silicon material.Above
The light of green and blue wave band will can at least be sheltered from as the nonmetallic materials of thin film transistor (TFT) light shield layer by speaking of.Such as figure
Shown in 5, non-crystalline silicon for wavelength in below 600nm blue light and green glow, the transmitance as little as 10% of non-crystalline silicon thick 100nm,
The transmitance of the non-crystalline silicon of more than 150nm thickness is just already close to for zero.In addition, for example, for wavelength be such as 525nm
Light, the thickness and transmitance of non-crystalline silicon can be with as shown in the table
| Amorphous silicon thickness (nm) | Transmitance |
| 50 | 31.2% |
| 100 | 9.9% |
| 150 | 3.2% |
| 200 | 0.8% |
Table 2
From this example, amorphous silicon membrane thickness is thicker, and the following film transmission rates of wavelength 600nm are lower.From conjunction
Suitable thickness, such as the thick non-crystalline silicons of more than 100nm can effectively below absorbing wavelength 600nm blue lights and green glow.Although as schemed
Shown in table, for the light that wavelength is below 600nm, the transmitance of non-crystalline silicon thick 50nm does not have thickness in more than 100nm
Non-crystalline silicon is preferable like that, but for specific thin film transistor (TFT), stops most of ultraviolet can and meet to require
So as to avoid the influence to device performance.Furthermore, it is contemplated that the size of device, light shield layer can not possibly be too thick, therefore can use
Such as 50nm-200nm non-crystalline silicon is as light shield layer.
In addition it is critically important, should also be non-hydrogenated for the non-crystalline silicon as light shield layer.Because using tradition
PECVD methods formed non-crystalline silicon in can contain substantial amounts of hydrogen, if use as amorphous silicon material as light shield layer
Words, in the follow-up preparation process of device, hydrogen is possible to be diffused into device other materials layer and cause device performance negative shadow
Ring.
Therefore, according to one embodiment, non-hydrogenated non-crystalline silicon can be formed using the method for low-temperature sputter, or according to
Other embodiment can also use the method for electron beam evaporation to form non-hydrogenated non-crystalline silicon.
According to another embodiment of the application, light shield layer 316 can use coloured unitary/metal composite oxide, for example,
The composite oxides of the nonferrous metal oxides such as chromium oxide, sub- titanium oxide and its composition.According to one embodiment, coloured unitary/
The thickness of metal composite oxide light shield layer or non-crystalline silicon light shield layer can be 50nm~200nm as needed.According to a reality
Example is applied, in the case where light shield layer 316 is using coloured unitary/metal composite oxide, electron beam evaporation, sputtering etc. can be used
Technology forms light shield layer 316.
According to another embodiment, light shield layer 316 can use black organic material, such as organic substrate (such as Ethylcellulose
Acid, it is poly- to stupid dicarboxylic acid ethyl ester alcohol (PET), polystyrene (PS), polyethers, polyimides, makrolon (PC), epoxy resin,
Phenoxy resin, polyether sulfone (PES), polyacrylate etc.) add black particles (such as carbon black, copper, cobalt, manganese, chromium, titanium oxide
And its composite oxide particle formed).According to another embodiment, the thickness of black organic material light shield layer is as needed
It can be 2~3 μm.According to another embodiment, in the case where light shield layer 316 is using black organic material, rod can be used to apply
Cover the technologies such as method, spin coating method, spray application method, ink-jet method, screen painting and form light shield layer 316.
According to one embodiment, after forming light shield layer 316, photoetching and etching can be carried out to it, so as to the figure of light shield layer 316
Shape., can be using the method for reactive ion etching (RIE) come real for non-hydrogenated non-crystalline silicon light shield layer according to one embodiment
Now light shield layer is graphical.It is the deposit that light shield layer is carried out on whole panel in actual fabrication process, and is removed on panel
Greater area of pixel electrode area also be present outside TFT device areas, this region is to need complete printing opacity, carries out photoetching here
Purpose be to remove the light shield layer in these regions.
Although three kinds of non-hydrogenated non-crystalline silicon, coloured unitary/metal composite oxide and black organic material screenings are enumerated herein
Photosphere can be not limited to these three materials as insulation light screening material as the material of light shield layer.It is foregoing right to disclosure satisfy that
The insulated non-metal material of light shield layer requirement is likely to be applicable.But some nonmetallic materials are not appropriate for as film crystalline substance
The light screening material of body pipe, such as amorphous carbon, its heat endurance is poor, and electric conductivity is strong, device can be polluted, influence device
Energy.
In S416, as shown in figure 3g, passivation layer 314 and light shield layer 316 can be patterned, form source/drain electrode
Fairlead 318 and 320.
According to one embodiment, the graphical of light shield layer can be realized using the method for reactive ion etching (RIE).
It should be understood that Fig. 3 g be illustrated that to individual devices structure carry out operation, except to light shield layer graphically with shape
Into outside extraction electrode opening, the deposit for being graphically additionally included in progress light shield layer on whole panel to light shield layer, and on panel
Greater area of pixel electrode area in addition to TFT device areas also be present, this region is to need complete printing opacity, and this is patterned
Purpose is to remove the light shield layer below these regions.
The bottom gate thin film transistor that another embodiment of the application provides, using insulation light screening material as light shield layer, can have
Effect reduces influence of the ambient light to device performance, but the application of current potential light shield layer need not be fixed, and does not increase device junction
Structure complexity, simplifies process flow steps, and device performance is not also had a negative impact.
Although some specific embodiments of the application are described in detail by example, the skill of this area
Art personnel it should be understood that example above merely to illustrate, rather than in order to limit scope of the present application.The skill of this area
Art personnel in the case where not departing from the scope and spirit of the present application to above example it should be understood that can modify.This Shen
Scope please is defined by the following claims.
Claims (11)
1. a kind of thin film transistor (TFT), including：
Substrate；
Formed over the substrate through patterned light shield layer, wherein the light shield layer uses insulated non-metal light screening material；
The active layer formed more than the light shield layer, the active layer include raceway groove, source region and the drain region of the transistor；
Gate electrode of the gate dielectric layer and formation formed on the active layer on the gate dielectric layer；And
Form the passivation layer on the active layer and the gate electrode.
2. thin film transistor (TFT) as claimed in claim 1, in addition to formed exhausted between the light shield layer and the active layer
The separation layer of edge.
3. thin film transistor (TFT) as claimed in claim 1 or 2, wherein the insulated non-metal material include non-hydrogenated non-crystalline silicon,
Coloured unitary/metal composite oxide and/or black organic material.
4. thin film transistor (TFT) as claimed in claim 3, wherein, the thickness of the non-hydrogenated amorphous silicon material for 50nm~
200nm, the thickness of the coloured unitary/composite metal oxide material are 50nm~200nm, the thickness of the black organic material
Spend for 0.5~3 μm.
5. thin film transistor (TFT) as claimed in claim 2, wherein, the separation layer include silica, silicon nitride, aluminum oxide and/
Or polyimides.
6. a kind of thin film transistor (TFT), including：
Substrate；
Form gate electrode over the substrate；
Form the gate dielectric layer on the gate electrode and the substrate；
The active layer on the gate dielectric layer is formed, the active layer includes raceway groove, source region and the drain region of the transistor；
The source/drain contact electrode formed on the active layer；
Formed and contact the passivation layer on electrode and the active layer in the source/drain；And
Formed on the passivation layer through patterned light shield layer, wherein the light shield layer uses insulated non-metal lightproof material
Material.
7. thin film transistor (TFT) as claimed in claim 6, wherein the insulated non-metal light screening material include non-hydrogenated non-crystalline silicon,
Coloured unitary/metal composite oxide and/or black organic material.
8. thin film transistor (TFT) as claimed in claim 7, wherein, the thickness of the non-hydrogenated amorphous silicon material for 50nm~
200nm, the thickness of coloured unitary/composite metal oxide material is 50nm~200nm, and the thickness of the black organic material is
0.5~3 μm.
9. a kind of method for preparing thin film transistor (TFT), including：
Light shield layer is formed on substrate and it is patterned, wherein the light shield layer uses insulated non-metal light screening material；
In light shield layer active layer formed above；
Gate dielectric layer and gate electrode are deposited successively on the active layer；
Source region and drain region are formed in the active layer of the gate electrode both sides；And
Passivation layer is formed on the active layer and the gate electrode.
10. method as claimed in claim 9, it is additionally included in the isolation that insulation is formed between the light shield layer and the active layer
Layer.
11. a kind of method for preparing thin film transistor (TFT), including：
Gate electrode layer is formed on substrate and it is patterned to form gate electrode；
Gate dielectric layer is formed on the gate electrode；
Active layer is formed on the gate dielectric layer；
Source/drain contact electrode is formed on the active layer；
Contacted in the source/drain and form passivation layer on electrode and the active layer；And
Light shield layer and graphical to its is formed on the passivation layer, wherein the light shield layer uses insulated non-metal lightproof material
Material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710717954.8A CN107611032A (en) | 2017-08-21 | 2017-08-21 | Thin film transistor (TFT) comprising light shield layer and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710717954.8A CN107611032A (en) | 2017-08-21 | 2017-08-21 | Thin film transistor (TFT) comprising light shield layer and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107611032A true CN107611032A (en) | 2018-01-19 |
Family
ID=61065471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710717954.8A Pending CN107611032A (en) | 2017-08-21 | 2017-08-21 | Thin film transistor (TFT) comprising light shield layer and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107611032A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389867A (en) * | 2018-02-26 | 2018-08-10 | 深圳市华星光电半导体显示技术有限公司 | The production method of array substrate and array substrate |
| CN109817642A (en) * | 2019-01-22 | 2019-05-28 | 深圳市华星光电技术有限公司 | Thin-film transistor array base-plate and its manufacturing method |
| CN111048622A (en) * | 2019-11-26 | 2020-04-21 | 中国科学院微电子研究所 | Optical transistor and method for manufacturing the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1026770A (en) * | 1996-07-11 | 1998-01-27 | Sharp Corp | Liquid crystal display device |
| CN1896857A (en) * | 2005-07-14 | 2007-01-17 | 三星电子株式会社 | Liquid crystal display device and making method |
| CN102956712A (en) * | 2011-08-22 | 2013-03-06 | 索尼公司 | Display, method of manufacturing the same and electric apparatus |
| CN103579356A (en) * | 2012-08-10 | 2014-02-12 | 北京京东方光电科技有限公司 | Oxide TFT, manufacturing method of oxide TFT, display panel and display device |
| CN106981478A (en) * | 2017-04-07 | 2017-07-25 | 京东方科技集团股份有限公司 | Top gate type thin film transistor and preparation method thereof, array base palte, display panel |
-
2017
- 2017-08-21 CN CN201710717954.8A patent/CN107611032A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1026770A (en) * | 1996-07-11 | 1998-01-27 | Sharp Corp | Liquid crystal display device |
| CN1896857A (en) * | 2005-07-14 | 2007-01-17 | 三星电子株式会社 | Liquid crystal display device and making method |
| CN102956712A (en) * | 2011-08-22 | 2013-03-06 | 索尼公司 | Display, method of manufacturing the same and electric apparatus |
| CN103579356A (en) * | 2012-08-10 | 2014-02-12 | 北京京东方光电科技有限公司 | Oxide TFT, manufacturing method of oxide TFT, display panel and display device |
| CN106981478A (en) * | 2017-04-07 | 2017-07-25 | 京东方科技集团股份有限公司 | Top gate type thin film transistor and preparation method thereof, array base palte, display panel |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389867A (en) * | 2018-02-26 | 2018-08-10 | 深圳市华星光电半导体显示技术有限公司 | The production method of array substrate and array substrate |
| CN109817642A (en) * | 2019-01-22 | 2019-05-28 | 深圳市华星光电技术有限公司 | Thin-film transistor array base-plate and its manufacturing method |
| CN111048622A (en) * | 2019-11-26 | 2020-04-21 | 中国科学院微电子研究所 | Optical transistor and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107680993B (en) | OLED panel and manufacturing method thereof | |
| KR102293971B1 (en) | Semiconductor device and method for manufacturing the same | |
| US9947757B2 (en) | Display device, array substrate, and thin film transistor | |
| CN104752343B (en) | The preparation method and its structure of dual gate oxide semiconductor TFT substrate | |
| TWI575087B (en) | Method of making oxide thin film transistor array, and device incorporating the same | |
| JP4982619B1 (en) | Manufacturing method of semiconductor element and manufacturing method of field effect transistor | |
| CN107424957A (en) | The preparation method of flexible TFT substrate | |
| CN104681629B (en) | Thin film transistor (TFT), array base palte and its respective preparation method, display device | |
| CN104900654B (en) | The preparation method and its structure of dual gate oxide semiconductor TFT substrate | |
| CN103489920B (en) | A kind of thin film transistor (TFT) and preparation method thereof, array base palte and display device | |
| KR20160036022A (en) | Semiconductor device and manufacturing method thereof | |
| CN106128944A (en) | The manufacture method of metal oxide thin-film transistor array base palte | |
| CN106129122B (en) | Oxide thin film transistor and preparation method thereof, array substrate, display device | |
| JP2009231664A (en) | Field-effect transistor, and manufacturing method thereof | |
| JP2009253204A (en) | Field-effect transistor using oxide semiconductor, and its manufacturing method | |
| TW201737358A (en) | Method for manufacturing semiconductor device | |
| CN102651339B (en) | TFT (Thin Film Transistor) array substrate and manufacturing method and display device of TFT array substrate | |
| EP3703112A1 (en) | Method for manufacturing oled backplane | |
| CN103346089B (en) | A kind of autoregistration bilayer channel metal-oxide thin film transistor (TFT) and preparation method thereof | |
| CN106847932A (en) | A kind of thin film transistor (TFT), array base palte, display device and method for fabricating thin film transistor | |
| CN103928343B (en) | Thin film transistor (TFT) and organic light emitting diode display preparation method | |
| CN110061034A (en) | The preparation method and OLED display panel of OLED display panel | |
| CN107611032A (en) | Thin film transistor (TFT) comprising light shield layer and preparation method thereof | |
| CN102945828A (en) | Active matrix organic light emitting diode driving back plate and preparation method of active matrix organic light emitting diode driving back plate | |
| US10121883B2 (en) | Manufacturing method of top gate thin-film transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180119 |