CN109817474B - Preparation method of chip-level all-solid-state SiC super capacitor - Google Patents
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Abstract
The invention relates to a preparation method of a chip-level all-solid-state SiC super capacitor, belonging to the technical field of micro-energy manufacturing, and the preparation method comprises the following steps: cleaning, soaking and drying the SiC wafer, and then obtaining the SiC nano array film after anodic oxidation etching and stripping; immersing the SiC nano-array film into a solid electrolyte, taking out the SiC nano-array film, and directly pressing to obtain a super capacitor electrode; the chip-level all-solid-state SiC super capacitor has the advantages of simple process, low preparation cost, good repeatability, small thickness reaching the micron level, capability of being integrated on a chip and wide application field.
Description
Technical Field
The invention relates to a preparation method of a chip-level all-solid-state SiC super capacitor, belonging to the technical field of micro-energy manufacturing.
Background
The rapid development of micro portable wearable electronic devices such as micro electro mechanical systems, micro robots, implantable medical devices, and the like, has greatly increased the demand for micro/nano power sources of chip scale and the like. Therefore, the research of the miniature electrochemical energy storage device attracts great attention. Compared with a micro battery, the micro super capacitor has the advantages of rapid energy collection, high-speed power transmission, good compatibility with the silicon industry and the like. In addition, the micro supercapacitor can achieve high energy transfer ratio at high charge and discharge rates due to the shortened ion diffusion length. At present, chip-scale micro supercapacitors are prepared by adopting an interdigital electrode mode. The capacitor electrode area of the interdigital electrode tends to occupy only half or less of the substrate area. This results in a lower amount of active material loading across the device, which in turn limits the increase in energy density of the device. In addition, supercapacitor fabrication in the form of interdigitated electrodes typically requires expensive lithographic equipment and complex fabrication processes. The super capacitor adopts a sandwich structure, so that the defects can be overcome, the electrode area occupation ratio of the super capacitor is high, the production process is simple, and the super capacitor is widely applied to commercial super capacitors.
There are however problems with such capacitors in terms of integratability:
1) miniaturization is difficult, such capacitors are usually composed of electrodes, a diaphragm and an electrolyte, and the thickness of the device is difficult to control;
2) the risk of liquid electrolyte leakage exists, and the leakage of water-system electrolyte easily endangers the whole circuit;
3) the electrode arrangement is volumetrically inefficient and does not accommodate more electrode active material in the active volume.
Therefore, based on the above discussion, if an effective method for manufacturing a chip-scale supercapacitor can be explored, the main problems of the existing chip-scale supercapacitor can be expected to be solved, and the application of the chip-scale supercapacitor in the field of microcircuits is strongly promoted.
Disclosure of Invention
Aiming at the existing problems, the invention provides the SiC nano array film and the application thereof in the super capacitor, and the super capacitor has the advantages of small volume, wide application field and strong performance.
In order to achieve the purpose, the invention adopts the following technical scheme:
a preparation method of a chip-level all-solid-state SiC super capacitor comprises the following steps:
cleaning, soaking and drying the SiC wafer, and then obtaining the SiC nano array film after anodic oxidation etching and stripping;
and (3) immersing the SiC nano array film into a solid electrolyte, taking out the SiC nano array film, and directly pressing to obtain the super capacitor.
Preferably, the SiC wafer is industrial grade. Namely, it isThe cumulative length of the scratches on the surface of the SiC wafer is less than 1 diameter, the number of the scratches is less than or equal to 3, and the density of the micropipes is less than or equal to 1/cm2。
Preferably, the soaking is carried out in an ethanol solution of hydrofluoric acid, and the soaking time is 100-140s, wherein the volume ratio of the hydrofluoric acid to the ethanol is 0.8-1.2: 1.
Preferably, the drying is to dry the SiC wafer in an oven at 35-45 ℃ for 8-12 min.
Preferably, the cathode material is a carbon plate.
Preferably, the etching liquid comprises ethanol, hydrofluoric acid and hydrogen peroxide in a volume ratio of 3:6: 1.
Preferably, the appearance of the SiC nano array film is a long nanowire.
Further preferably, the long nanowires have a diameter of 18-22 nm.
Preferably, the etching treatment time is 10-15min, and the stripping treatment time is 1-5 s.
Preferably, the etching treatment and the stripping treatment are carried out under the same treatment conditions, and both adopt a pulse power supply constant current mode, and the current density is 130mAcm-2. In the etching process, the morphology of the SiC wafer can be regulated and controlled by controlling the etching time, the morphology of the film can be monitored by the SEM technology, and finally the SiC film with the required morphology is accurately obtained.
Compared with the SiC nano array with single appearance prepared by the traditional method, the SiC nano array with single appearance can be better controlled in the anodic oxidation etching process, the appearance change of the SiC nano array can be changed from the nano hole to the nano wire and then to the disordered porous appearance, the length of the nano wire can be controlled, the SiC nano array with longer appearance of the nano wire needs to be selected as a product which can be practically applied, and the appearance of the short nano wire and the disordered porous appearance can cause the reduction of the performance of the product in the application process.
Meanwhile, when the SiC nano-array film is prepared, the film is obtained by stripping the C surface of the SiC wafer. The front surface of the SiC wafer is a C surface, the specific components of the back surface are uncertain, the C surface is firstly contacted with an electrode clamp in the etching and stripping processes, good C surface etching can be formed, at the moment, partial etching can also occur on the back surface, but the etching effect is poor, the required etching effect cannot be obtained, and generally only an etching film of the C surface is taken. Although the C surface can obtain a better film after the first etching, the C surface is not easy to strip at the moment, the surface needs to be changed for short-time etching, namely the SiC wafer is overturned, the back surface is in contact with the electrode clamp for etching for several seconds, a large number of bubbles can be formed on the C surface at the moment, and then the C surface is promoted to strip by utilizing the escaped bubbles, and finally the SiC nano array film is obtained.
After the required film is obtained, since the film itself can be directly used as an electrode, the film electrode needs to be assembled into a super capacitor, and an electrolyte is necessary. The invention adopts PVA/KCl solid electrolyte which can be obtained by simple mixing and stirring and other processes, and the operation is simple and reliable. And then, the SiC film is immersed in the electrolyte for 46-50h, so that good adaptability between the film and the electrolyte is ensured, and the performance reduction of the device caused by poor contact between the film and the electrolyte is avoided. The morphology surface of the film has a proper pore structure, which is beneficial to the immersion of solid electrolyte and the transport of ions, and the pores on the back surface of the morphology surface are very small, so that the electrolyte cannot enter, which is not beneficial to energy storage. And finally, pressing the appearance surfaces of the two fully soaked SiC nano array films to obtain the chip-level all-solid-state SiC super capacitor.
Preferably, the electrolyte is a solid electrolyte and has a thickness of 7 to 9 μm.
Preferably, the electrolyte comprises KCl and polyvinyl alcohol, wherein the mass ratio of KCl to polyvinyl alcohol is 1.8-2.2: 1.
Preferably, the electrolyte is prepared by the following steps: dissolving KCl in deionized water, heating to 80-90 deg.C, stirring while slowly adding polyvinyl alcohol, and stirring until the solution is clear.
Preferably, the pressing specifically comprises: selecting two SiC nanometer array films soaked with electrolyte, oppositely pressing the surfaces with the shapes, and erasing the electrolyte adhered to the back surface.
Preferably, the thickness of the electrode is 15-17 μm, and the thickness of the supercapacitor is 37-43 μm.
The capacitor thickness finally obtained by the invention is micron-sized, and only consists of the film and the electrolyte, so that the structure of the super capacitor is greatly simplified, the space of the capacitor is compressed, the performance of the super capacitor serving as a micro power supply is greatly improved, the super capacitor can be conveniently implanted in a smaller space or structure, and the practicability is higher.
Compared with other materials, the invention has the following advantages:
(1) the chip-level all-solid-state SiC super capacitor disclosed by the invention is simple in process method, low in preparation cost and good in repeatability.
(2) The chip-level all-solid-state SiC super capacitor has small thickness reaching the micron level, can be integrated on a chip, and has wide application field.
(3) The chip-level all-solid-state SiC super capacitor disclosed by the invention has higher specific capacitance, coulombic efficiency and rate capability.
(4) The chip-level all-solid-state SiC super capacitor has higher energy density and power density.
Drawings
FIG. 1 is an X-ray diffraction (XRD) spectrum of a SiC thin film obtained in example 1 of the present invention after polishing;
FIG. 2 is a High Resolution Transmission Electron Microscopy (HRTEM) image of a chip scale all solid state SiC supercapacitor electrode in example 1 of the present invention;
FIG. 3 is an Electron Diffraction Spectroscopy (EDS) spectrum of a chip-scale all-solid-state SiC supercapacitor electrode in example 1 of the present invention;
FIG. 4 is a cross-sectional view of a chip-scale all-solid-state SiC supercapacitor in example 1 of the present invention;
FIG. 5 is a photograph of a thickness test of a chip-scale all-solid-state SiC supercapacitor in example 1 of the present invention;
FIG. 6 shows the sweep rate of the chip-scale all-solid-state SiC super capacitor of the present invention at different sweep rates (from 10 mVs)-1To 200mVs-1) Cyclic Voltammetry (CV) curves under;
FIG. 7 shows the sweep rate of the chip-scale all-solid-state SiC super capacitor of the present invention at different sweep rates (from 500mVs-1To 1000mVs-1) Cyclic Voltammetry (CV) curves under;
FIG. 8 is a graph of the relationship between the specific capacitance and the sweep rate of the chip-scale all-solid-state SiC supercapacitor according to the present invention;
FIG. 9 is a cycle stability curve for a chip-scale all-solid-state SiC supercapacitor according to the present invention;
fig. 10 is a graph of power density versus energy density for a chip-scale all-solid-state SiC supercapacitor of the invention (containing literature comparative data).
Detailed Description
The following are specific embodiments of the present invention and are further described with reference to the accompanying drawings, but the present invention is not limited to these embodiments.
Example 1
Cutting an industrial grade SiC wafer into the size of 0.7 multiplied by 1.5cm2Respectively carrying out ultrasonic cleaning on the SiC wafer in acetone and deionized water for 15min, then immersing the SiC wafer in a mixed solution of hydrofluoric acid and ethanol with the volume ratio of 1:1 for 120s, taking out the SiC wafer, and drying the SiC wafer in a drying oven at 40 ℃ for 10 min;
immersing the dried SiC wafer serving as an anode, a C surface of the SiC wafer contacting an electrode holder and a carbon plate serving as a cathode into an etching solution mixed by ethanol, hydrofluoric acid and hydrogen peroxide in a volume ratio of 3:6:1, wherein the current density is 130mAcm-2Etching for 13min under the pulse current, and taking out;
the back surface of the C surface of the SiC wafer was brought into contact with the electrode holder and immersed again in the etching solution at a current density of 130mAcm-2Stripping for 10s under the pulse current to obtain the SiC nanowire array film;
dissolving 10g of KCl in 50mL of deionized water, stirring at 85 ℃, slowly adding 5g of PVA into the KCl solution, and continuously stirring until the solution is clear to obtain a PVA/KCl solid electrolyte;
and (3) immersing the SiC nanowire array film into PVA/KCl solid electrolyte for 48h, selecting two films, oppositely pressing the surfaces with the shapes, and erasing the residual PVA/KCl solid electrolyte on the back surface of the SiC film by using absorbent paper to obtain the supercapacitor.
Example 2
Cutting an industrial grade SiC wafer into the size of 0.7 multiplied by 1.5cm2Respectively carrying out ultrasonic cleaning on the SiC wafer in acetone and deionized water for 15min, then immersing the SiC wafer in a mixed solution of hydrofluoric acid and ethanol with the volume ratio of 1:1 for 120s, taking out the SiC wafer, and drying the SiC wafer in a drying oven at 40 ℃ for 10 min;
immersing the dried SiC wafer serving as an anode, a C surface of the SiC wafer contacting an electrode holder and a carbon plate serving as a cathode into an etching solution mixed by ethanol, hydrofluoric acid and hydrogen peroxide in a volume ratio of 2.5:6:1 at a current density of 120mAcm-2Etching for 10min under the pulse current, and taking out;
the back surface of the C surface of the SiC wafer is contacted with the electrode clamp and is immersed into the etching solution again, and the current density is 120mAcm-2Stripping for 10s under the pulse current to obtain the SiC nanowire array film;
dissolving 10g of KCl in 50mL of deionized water, stirring at 85 ℃, slowly adding 5g of PVA into the KCl solution, and continuously stirring until the solution is clear to obtain a PVA/KCl solid electrolyte;
and (3) immersing the SiC nanowire array film into PVA/KCl solid electrolyte for 48h, selecting two films, oppositely pressing the surfaces with the shapes, and erasing the residual PVA/KCl solid electrolyte on the back surface of the SiC film by using absorbent paper to obtain the supercapacitor.
Example 3
Cutting an industrial grade SiC wafer into the size of 0.7 multiplied by 1.5cm2Respectively carrying out ultrasonic cleaning on the SiC wafer in acetone and deionized water for 15min, then immersing the SiC wafer in a mixed solution of hydrofluoric acid and ethanol with the volume ratio of 1:1 for 120s, taking out the SiC wafer, and drying the SiC wafer in a drying oven at 40 ℃ for 10 min;
immersing the dried SiC wafer serving as an anode, a C surface of the SiC wafer contacting an electrode holder and a carbon plate serving as a cathode in an etching solution mixed by ethanol, hydrofluoric acid and hydrogen peroxide in a volume ratio of 3.5:6:1 at a current density of 140mAcm-2Etching for 15min under the pulse current, and taking out;
the back surface of the C surface of the SiC wafer was brought into contact with the electrode holder and immersed again in the etching solution at a current density of 140mAcm-2Pulse ofStripping under current for 10s to obtain the SiC nanowire array film;
dissolving 10g of KCl in 50mL of deionized water, stirring at 85 ℃, slowly adding 5g of PVA into the KCl solution, and continuously stirring until the solution is clear to obtain a PVA/KCl solid electrolyte;
and (3) immersing the SiC nanowire array film into PVA/KCl solid electrolyte for 48h, selecting two films, oppositely pressing the surfaces with the shapes, and erasing the residual PVA/KCl solid electrolyte on the back surface of the SiC film by using absorbent paper to obtain the supercapacitor.
Example 4
Cutting an industrial grade SiC wafer into the size of 0.7 multiplied by 1.5cm2Respectively carrying out ultrasonic cleaning on the SiC wafer in acetone and deionized water for 15min, then immersing the SiC wafer in a mixed solution of hydrofluoric acid and ethanol with the volume ratio of 1:1 for 120s, taking out the SiC wafer, and drying the SiC wafer in a drying oven at 40 ℃ for 10 min;
immersing the dried SiC wafer serving as an anode, a C surface of the SiC wafer contacting an electrode holder and a carbon plate serving as a cathode into an etching solution mixed by ethanol, hydrofluoric acid and hydrogen peroxide in a volume ratio of 3:6:1, wherein the current density is 130mAcm-2Etching for 13min under the pulse current, and taking out;
the back surface of the C surface of the SiC wafer was brought into contact with the electrode holder and immersed again in the etching solution at a current density of 130mAcm-2Stripping for 10s under the pulse current to obtain the SiC nanowire array film;
dissolving 9g of KCl in 50mL of deionized water, stirring at 80 ℃, slowly adding 5g of PVA into the KCl solution, and continuously stirring until the solution is clear to obtain a PVA/KCl solid electrolyte;
and (3) immersing the SiC nanowire array film into PVA/KCl solid electrolyte for 10h, selecting two films, oppositely pressing the surfaces with the shapes, and erasing the residual PVA/KCl solid electrolyte on the back surface of the SiC film by using absorbent paper to obtain the supercapacitor.
Example 5
Cutting an industrial grade SiC wafer into the size of 0.7 multiplied by 1.5cm2Respectively carrying out ultrasonic cleaning on the SiC wafer in acetone and deionized water for 15min, and then immersing the SiC wafer in the acetone and the deionized waterPutting the SiC wafer into a mixed solution of hydrofluoric acid and ethanol with the volume ratio of 1:1 for 120s, taking out the mixed solution, and drying the SiC wafer in a drying oven at 40 ℃ for 10 min;
immersing the dried SiC wafer serving as an anode, a C surface of the SiC wafer contacting an electrode holder and a carbon plate serving as a cathode into an etching solution mixed by ethanol, hydrofluoric acid and hydrogen peroxide in a volume ratio of 3:6:1, wherein the current density is 130mAcm-2Etching for 13min under the pulse current, and taking out;
the back surface of the C surface of the SiC wafer was brought into contact with the electrode holder and immersed again in the etching solution at a current density of 130mAcm-2Stripping for 10s under the pulse current to obtain the SiC nanowire array film;
dissolving 11g of KCl in 50mL of deionized water, stirring at 90 ℃, slowly adding 5g of PVA into the KCl solution, and continuously stirring until the solution is clear to obtain a PVA/KCl solid electrolyte;
and (3) immersing the SiC nanowire array film into PVA/KCl solid electrolyte for 50h, selecting two films, oppositely pressing the surfaces with the shapes, and erasing the residual PVA/KCl solid electrolyte on the back surface of the SiC film by using absorbent paper to obtain the supercapacitor.
Example 6
The only difference from example 1 is that example 6 employs only the ethanol soaking treatment.
Example 7
The difference from the embodiment 1 is only that the etching solution of the embodiment 7 is composed of ethanol and hydrofluoric acid in a volume ratio of 1: 2.
Example 8
The difference from the embodiment 1 is only that the etching solution of the embodiment 8 is composed of hydrofluoric acid and hydrogen peroxide in a volume ratio of 6: 1.
Example 9
The only difference from example 1 is that the etching treatment time of example 9 was 9 min.
Example 10
The only difference from example 1 is that the etching treatment time of example 10 was 16 min.
Example 11
The only difference from example 1 is that the time for the stripping treatment in example 11 was 0.5 s.
Example 12
The only difference from example 1 is that the time for the stripping treatment in example 12 was 18 seconds.
Example 13
The only difference from example 1 is that in example 13, one textured film side was laminated against the other non-textured film side.
Example 14
The only difference from example 1 is that in example 14, two topographically free film sides are pressed together.
Comparative example 1
The only difference from example 1 is that the morphology of the SiC thin film of comparative example 1 is nanoporous.
Comparative example 2
The only difference from example 1 is that the morphology of the SiC thin film of comparative example 2 is short nanowires.
Comparative example 3
The only difference from example 1 is that the morphology of the SiC thin film of comparative example 3 is a disordered porous morphology.
The supercapacitors prepared in examples 1-14 and comparative examples 1-3 were tested for specific capacitance, power density, and energy density, and the results are shown in table 1:
table 1: performance of the supercapacitors of examples 1-14 and comparative examples 1-3
As can be seen from the data in Table 1, the etching reaction is difficult to occur in examples 7 and 8, the SiC nanowire film cannot be peeled off due to too short peeling time in example 11, and the electrode performance is greatly weakened due to the fact that the surfaces with the appearances are not pressed relatively in examples 13 and 14, and finally the failed capacitor is obtained without value.
Wherein, fig. 1 is an XRD spectrum of the SiC film obtained in embodiment 1 of the present invention after grinding, which shows that the phase component of the SiC film obtained by anodic oxidation etching is 4H-SiC;
FIG. 2 is a high-resolution TEM image of the SiC film obtained in example 1 of the present invention, which shows that the lattice spacing is 0.265 nm;
FIG. 3 is an EDS spectrum of the SiC film obtained in example 1 of the present invention, in which the ratio of Si element to C element is close to 1:1, indicating that the etched sample is mainly composed of SiC;
FIGS. 4 and 5 are a cross-sectional view and a photograph of the combined SiC chip-scale supercapacitor of example 1, showing an electrode thickness of 16 μm, an electrolyte thickness of 8 μm, and a capacitor overall thickness of 40 μm;
FIGS. 6 and 7 show the SiC supercapacitor of example 1 at different scan rates (from 10 mVs)-1To 1000mVs-1) Cyclic voltammetry curve of 10mVs by calculation-1The specific capacitance of the device is as high as 22.3mFcm-2The capacitor has remarkable energy storage characteristics; at up to 1000mVs-1The CV curve can still keep the shape of an approximate rectangle under the sweeping speed, which shows that the capacitor has smaller internal resistance and ideal double electric layer energy storage characteristics;
FIG. 8 is a plot of specific capacitance versus sweep rate calculated from FIGS. 6 and 7, even at 500mVs-1The specific capacitance still remains 14.8mFcm at the scanning speed of-2The super capacitor is shown to have better rate performance;
FIG. 9 shows that the SiC supercapacitor of example 1 of the present invention has a specific capacitance of 21.14mFcm after 10000 cycles of cyclic voltammetry for cyclic stability at room temperature-2The super capacitor has an ultra-long service life;
FIG. 10 is a graph showing the relationship between the energy density and the power density of the SiC supercapacitor according to example 1 of the present invention, in which the energy density and the power density of the SiC supercapacitor reached 1.31mWhcm-3And 2.8Wcm-3Is obviously superior to a plurality of reported micro supercapacitors.
And fig. 6-10 were obtained from testing the chip scale all solid state SiC supercapacitor of example 1 packaged into a button cell in order to protect the capacitor from damage by the test clip.
While the invention has been described in detail and with reference to specific embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof.
Claims (5)
1. A preparation method of a chip-level all-solid-state SiC super capacitor is characterized by comprising the following steps:
cleaning, soaking and drying the SiC wafer, and then obtaining the SiC nano array film after anodic oxidation etching and stripping;
immersing the SiC nano-array film into a solid electrolyte, taking out the SiC nano-array film, and directly pressing to obtain a super capacitor; the pressing specifically comprises the following steps: selecting two SiC nanometer array films soaked with electrolyte, oppositely pressing the surfaces with the shapes, and erasing the electrolyte adhered to the back surfaces;
the etching treatment time is 10-15min, and the stripping treatment time is 1-15 s;
the SiC nano array film is in a long nanowire shape; the diameter of the long nanowire is 18-22 nm.
2. The method for preparing the chip-scale all-solid-state SiC supercapacitor according to claim 1, wherein the thickness of the solid electrolyte is 7-9 μm.
3. The preparation method of the chip-scale all-solid-state SiC supercapacitor according to claim 1, wherein the electrolyte comprises KCl and polyvinyl alcohol, and the mass ratio of KCl to polyvinyl alcohol is 1.8-2.2: 1.
4. The method for preparing the chip-scale all-solid-state SiC supercapacitor according to any one of claims 1 to 3, wherein the electrolyte is prepared by: dissolving KCl in deionized water, heating to 80-90 deg.C, stirring while slowly adding polyvinyl alcohol, and stirring until the solution is clear.
5. The preparation method of the chip-scale all-solid-state SiC supercapacitor according to claim 1, wherein the thickness of the electrode is 15-17 μm, and the thickness of the supercapacitor is 37-43 μm.
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