CN109804307A - Liquid crystal display device and projection display device - Google Patents
Liquid crystal display device and projection display device Download PDFInfo
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- CN109804307A CN109804307A CN201780062196.9A CN201780062196A CN109804307A CN 109804307 A CN109804307 A CN 109804307A CN 201780062196 A CN201780062196 A CN 201780062196A CN 109804307 A CN109804307 A CN 109804307A
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- semiconductor film
- display device
- liquid crystal
- crystal display
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Abstract
A kind of liquid crystal display device is provided with the scan line with light-shielding characteristic；It is arranged in face of scan line and has the semiconductor film of the channel region between source region and drain region and source region and drain region；In face of the gate electrode of the channel region of semiconductor film；First interlayer dielectric of covering grid electrode；And the first interlayer dielectric electric connection grid electrode and scan line are penetrated, and stand on the shading wall of the channel region of semiconductor film and the source region of semiconductor film and drain region side.
Description
Technical field
This technology is related to the liquid crystal display device with TFT (thin film transistor (TFT)) substrate and the projection type with TFT substrate
Display device.
Background technique
The light modulation that liquid crystal display panel (liquid crystal display device) is used as in such as projector (projection display device) is set
Standby (light valve) (for example, patent document 1 etc.).For example, liquid crystal display panel has liquid crystal layer between TFT substrate and counter substrate.
Citation list
Patent document
Patent document 1: Japanese Unexamined Patent Application Publication 2011-186108.
Summary of the invention
However, light leakage electric current is generated in the case where using up irradiation TFT substrate, difference thus this may cause caused by
Picture quality such as flashes.This is but also must inhibit the generation of this light leakage electric current and keep the aperture ratio of liquid crystal display panel.Hole
Diameter is than one of the important performance indexes for light modulation device.
Accordingly, it is desirable to provide a kind of liquid crystal display of generation for the leakage current for being able to maintain aperture ratio and inhibiting transistor fills
It sets and projection display device.
Liquid crystal display device according to the embodiment of this technology includes: the scan line with light-shielding characteristic；It is arranged to
In face of scan line and there is the semiconductor film of channel region between source/drain region and source/drain region；In face of the channel region of semiconductor film
Gate electrode；First interlayer dielectric of covering grid electrode；And penetrate the first interlayer dielectric and by gate electrode and scan line that
The shading wall of this electric coupling, the shading wall are upright transverse to the channel region of semiconductor film and the source/drain region of semiconductor film.
Projection display device according to the embodiment of this technology includes aobvious according to the foregoing liquid crystal of the embodiment of this technology
Showing device.
In liquid crystal display device and projection display device according to each embodiment of this technology, it is arranged essentially parallel to
The scan line and be substantially perpendicular to the upright shading wall shielding semiconductor film of semiconductor film that semiconductor film is arranged.Shading wall also has
There is flush plug structure, and is less likely to influence aperture ratio compared with other light shading methods.
According to the liquid crystal display device and projection display device of each embodiment of this technology, scan line and screening are provided
Light wall, so as to inhibit transistor leakage current generation.This also allows to inhibit the reduction of aperture ratio.Therefore, it can keep
Aperture ratio and inhibit transistor leakage current generation.Note that said effect is not necessarily restrictive, and this can be provided
Any effect described in open.
Detailed description of the invention
Fig. 1 is the signal for showing the cross-sectional configuration of the major part of liquid crystal display device of the embodiment according to this technology
Figure.
Fig. 2 is the plan view of TFT substrate shown in Fig. 1.
Fig. 3 is the sectional view intercepted along line III-III' shown in Fig. 2.
Fig. 4 is the sectional view intercepted along line IV-IV' shown in Fig. 2.
Fig. 5 is the exemplary schematic diagram for showing the equivalent circuit of liquid crystal display device shown in FIG. 1.
Fig. 6 A is the exemplary sectional view of the manufacturing process of TFT substrate shown in Fig. 4 is waited.
Fig. 6 B is the sectional view of the process after Fig. 6 A.
Fig. 6 C is the sectional view of the process after Fig. 6 B.
Fig. 7 A is the sectional view of the process after Fig. 6 C.
Fig. 7 B is the sectional view of the process after Fig. 7 A.
Fig. 7 C is the sectional view of the process after Fig. 7 B.
Fig. 8 A is the sectional view of the process after Fig. 7 C.
Fig. 8 B is the sectional view of the process after Fig. 8 A.
Fig. 8 C is the sectional view of the process after Fig. 8 B.
Fig. 9 A is the sectional view of the process after Fig. 8 C.
Fig. 9 B is the sectional view of the process after Fig. 9 A.
Figure 10 A is the sectional view of the process after Fig. 9 B.
Figure 10 B is the sectional view of the process after Figure 10 A.
Figure 11 is the plan view according to the structure of the TFT substrate of comparative example 1.
Figure 12 is the perspective view of TFT substrate shown in Figure 11.
Figure 13 is the plan view according to the structure of the TFT substrate of comparative example 2.
Figure 14 is the perspective view of a part of TFT substrate shown in Fig. 2.
Figure 15 is the perspective view of TFT substrate shown in Fig. 2.
Figure 16 is the explanatory diagram into the luminous intensity of transistor shown in Fig. 2.
Figure 17 is the schematic diagram for indicating to apply the structure of the projection display device of liquid crystal display device shown in FIG. 1.
Specific embodiment
Hereinafter, some embodiments of this technology are described in detail with reference to the attached drawings.Note that providing description in the following order.
1. embodiment
Transverse to the example of the shading wall of semiconductor film setting
2. modified example
The electrode of holding capacitor device has the example of light-shielding characteristic
3. applying example
[embodiment]
(structure)
Fig. 1 shows the cross-sectional structure of the liquid crystal display device 1 according to the embodiment of this technology.Liquid crystal display device 1
Light modulation device as such as projection display device (projection display device 200 of Figure 17 described later).Liquid crystal
Display device 1 successively includes TFT substrate 10, pixel electrode 20, centering film 21a, liquid crystal layer 22, centering film 21b, opposite electrode 23
With counter substrate 24.
Fig. 2 shows the planar structure of TFT substrate 10, Fig. 3 shows the cross along line III-III' shown in Fig. 2 interception
Cross section structure and Fig. 4 show the cross-sectional structure along line IV-IV' shown in Fig. 2 interception.TFT substrate 10 is in substrate 11
On successively include scan line 12, semiconductor film 13, gate electrode 14, holding capacitor device 16 and photomask 17.Gate electrode 14 and scanning
Line 12 is electrically coupled to each other by shading wall 15A and 15B.Interlayer dielectric 18A is set between scan line 12 and semiconductor film 13
(the second interlayer dielectric), and (the first interlayer is exhausted by setting interlayer dielectric 18B between gate electrode 14 and holding capacitor device 16
Velum) and interlayer dielectric 18C.Gate insulating film 19 is arranged between semiconductor film 13 and gate electrode 14.
Fig. 5 shows the configuration example of the equivalent circuit in single pixel.Equivalent circuit is active type driving circuit, packet
Include transistor Tr, holding capacitor device 16 and liquid crystal display.Transistor Tr has semiconductor film 13, gate electrode 14 and grid exhausted
Velum 19.Liquid crystal display has pixel electrode 20.
The gate electrode 14 of transistor Tr is couple to corresponding scan line 12.One of the source electrode and drain electrode of transistor Tr coupling
It is connected to corresponding data line LD, and another one is couple to pixel electrode 20.Holding capacitor device 16 is arranged on common wire LC and Tr
The other of source electrode and drain electrode between.
Transistor Tr is connected according to the scanning signal (strobe pulse) provided from scan line 12, to mention to from data line LD
The signal potential of the picture signal of confession sample and the signal potential is supplied to holding capacitor device 16.
In the following, it is described that constituting each unit of TFT substrate 10.
Substrate 11 is used to support transistor Tr and holding capacitor device 16, and by for example including quartz, glass, silicon, plastics
The tabular component of film etc. is constituted.
In addition to as described above as the function for the wiring that scanning signal is supplied to transistor Tr other than, scan line 12 also has
There is light shield function.This prevents light to be applied to transistor Tr, so as to prevent due to failure caused by generating light leakage electric current.
In the plan view, shading scan line 12 is arranged at the position that the semiconductor film 13 and gate electrode 14 of transistor Tr are overlapped than crystalline substance
In the wider range of the semiconductor film 13 and gate electrode 14 of body pipe Tr.That is, the following table of semiconductor film 13 and gate electrode 14
Face is scanned line 12 and covers.Scan line 12 is arranged to predetermined pattern.Specifically, scan line 12 is extended with preset width, for example,
Extend in X-direction and Y-direction in Fig. 2.Scan line 12 is made of low reflectivity material.It can be by the Gao Rong of such as tungsten and titanium
The refractory metal silicide of point metal material or such as tungsten silicide (WSi) is used for scan line 12.Scan line 12 has for example
The thickness (Z-direction in Fig. 3 and Fig. 4) of 200nm.Adhesive layer 12a can be arranged between scan line 12 and substrate 11.Bonding
Layer 12a is for example made of polysilicon etc..
Interlayer dielectric 18A is arranged in the whole surface of substrate 11, to cover scan line 12.Interlayer dielectric 18A
Such as by silica (SiO2) constitute.For example, it is preferable to which the surface to interlayer dielectric 18A carries out planarization process, and keep it flat
Smoothization.In the interlayer dielectric 18A that surface is flattened, the machinability for forming top layer is improved, and is bent by force so as to improve
Than.Interlayer dielectric 18A has the thickness of such as 300nm to 600nm.
Semiconductor film 13 is arranged on interlayer dielectric 18A with predetermined pattern.Semiconductor film 13 is arranged in face of sweeping
A part of line 12 is retouched, there is interlayer dielectric 18A therebetween.Semiconductor film 13 is extended with preset width, for example, the X in Fig. 2
Side upwardly extends.Semiconductor film 13 has channel region 13C at the position in face of gate electrode 14.In semiconductor film 13, channel
Area 13C is clipped in the middle by LDD (lightly doped drain) area 13L-1 and 13L-2 and source/drain region 13SD-1 and 13SD-2.Specifically,
Channel region 13C is arranged between source/drain region 13SD-1 and source/drain region 13SD-2, and LDD region 13L-1 is arranged on source/drain region
Between 13SD-1 and channel region 13C and LDD region 13L-2 is arranged between source/drain region 13SD-2 and channel region 13C.LDD
Area 13L-1 and 13L-2 are the area that carrier impurity is spread with low concentration.For example, LDD region 13L-2 is input side LDD region, and LDD
Area 13L-1 is outlet side LDD region.When transistor Tr ends (closing), this LDD region 13L-1 and 13L-2, which is arranged, to be allowed to reduce
Leakage current.Source/drain region 13SD-1 and 13SD-2 are the resistance reduction area that carrier impurity is spread with high concentration.Source/drain region 13SD-
The semiconductor film 13 of 1 side is conductively coupled to holding capacitor device 16, and the semiconductor film of the source/drain region side 13SD-2 via coupling aperture H1
13 are conductively coupled to data line LD via coupling aperture H2.Semiconductor film 13 is by the semiconductor film for example including amorphous silicon, polysilicon etc.
Film is constituted.
Gate insulating film 19 is arranged in the whole surface of substrate 11, to cover semiconductor film 13.Gate insulating film 19
Such as it is made of silica (SiO2) film or silicon nitride (SiN) film.For example, can use CVD (chemical vapor deposition) method shape
At this gate insulating film 19.Gate insulating film 19 can also be made of heat oxide film.
Gate electrode 14 is arranged on gate insulating film 19 with predetermined pattern.Gate electrode 14 is to be enough to be wider than semiconductor film 13
Width (distance in Y-direction in Fig. 2) width setting.For example, gate electrode 14 is by the impurity doped with such as phosphorus (P)
Polysilicon film is constituted.For example, the stacked structure of polysilicon film and tungsten silicide film etc. may be constructed gate electrode 14.Gate electrode 14 has
Such as the thickness of 100nm to 220nm.
Interlayer dielectric 18B is arranged in the whole surface of substrate 11, with covering grid electrode 14.With interlayer dielectric
18A is similar, it is preferable that interlayer dielectric 18B is made of such as silica and its surface is flattened.
Shading wall 15A and 15B are arranged in through-hole SA15 and SB15.Through-hole SA15 and SB15 penetrate interlayer dielectric
18B and gate insulating film 19, and scan line 12 is reached via a part of interlayer dielectric 18A.In the present embodiment, shading wall
15A and 15B at least transverse to the channel region 13C of semiconductor film 13, LDD region 13L-1 and 13L-2 and source/drain region 13SD-1 and
13SD-2 is upright.Although will describe details later, this allows to effectively shielding semiconductor film 13 from the influence of light, with
Inhibit the generation of the leakage current of TFT.In addition, shading wall 15A and 15B have flush plug structure.With other light shading method phases
Than this allows to prevent that the reduction of aperture ratio.
Shading wall 15A and 15B include the surface substantially parallel with the XZ plane in Fig. 2 and Fig. 4, and are arranged to
It is substantially perpendicular to the semiconductor film 13 on the surface including being parallel to X/Y plane.Shading wall 15A and 15B are arranged essentially parallel to the (side X
To) extending direction of semiconductor film 13 extends.Channel region 13C, LDD region of the shading wall 15A and 15B transverse to semiconductor film 13
13L-1 and 13L-2, source/drain region 13SD-1 and 13SD-2 and coupling aperture H1 are configured.Preferably, shading wall 15A and 15B
Also transverse to the coupling aperture H1 setting of semiconductor film 13.This allows to prevent that light enters semiconductor film in broader region
13.Shading wall 15A and 15B are arranged on two sides of semiconductor film 13 and facing with each other, have semiconductor film 13 therebetween.Shading
Wall 15A is arranged in the side of semiconductor film 13 transverse to semiconductor film 13 and shading wall 15B is in the other side of semiconductor film 13
It is arranged transverse to semiconductor film 13.The lower end of each shading wall 15A and 15B are contacted with scan line 12, and each shading wall 15A
Same plane is constituted with the upper end of 15B and the upper surface of interlayer dielectric 18B.The lower end of each shading wall 15A and each shading
Part between the upper end of wall 15A and 15B is contacted with gate electrode 14.Specifically, the face on each surface of shading wall 15A and 15B
The part (for example, intermediate region) of gate electrode 14 is contacted with gate electrode 14.Shading wall 15A and 15B are so-called common contact,
And light shield can be set in the range more wider than typical contact.Shading wall 15A and 15B respectively have such as 200nm extremely
The thickness (distance in the Y direction) of 400nm.Through-hole SA15 and SB15 respectively have the width of such as 200nm to 400nm, should
Width is substantially the same with the thickness of each shading wall 15A and 15B.For example, shading wall 15A can be constituted by refractory metal
And 15B.For example, shading wall 15A and 15B is made of tungsten (W).Shading wall 15A and 15B can also be by the high-melting-points of such as titanium and molybdenum
Metal is constituted.In through-hole SA15 and SB15, shading wall 15A and 15B can be arranged on barrier metal layer 15Ab and 15Bb.
Barrier metal layer 15Ab and 15Bb are for example made of titanium nitride (TiN).
Interlayer dielectric 18C is arranged in the whole surface of substrate 11, covers the upper end of each shading wall 15A and 15B
And interlayer dielectric 18B.Similar with interlayer dielectric 18A and 18B, interlayer dielectric 18C is for example made of silica, and
Thickness with such as 100nm to 200nm.
Holding capacitor device 16 is arranged in the presumptive area on interlayer dielectric 18C and covering transistor Tr.Specifically,
Holding capacitor device 16 is set at position Chong Die with semiconductor film 13 and gate electrode 14 in the plan view, and at least covering half
Channel region 13C, LDD region 13L-1 and 13L-2 and the source/drain regions 13SD-1 and 13SD-2 and gate electrode 14 of electrically conductive film 13.
Holding capacitor device 16 have width for example roughly the same with the width of scan line 12, and be set in the plan view with scanning
At the position of a part overlapping of line 12.Channel region 13C, LDD region 13L-1 and 13L-2 and the source/drain region of semiconductor film 13
Respective lower that 13SD-1 and 13SD-2 and gate electrode 14 are covered with scanned line 12 and has and be kept capacitor
The respective upper surfaces of 16 coverings.
Holding capacitor device 16 include the sequence according to this on interlayer dielectric 18C lower electrode 16B, dielectric layer 16I and on
Electrode 16U.Lower electrode 16B is conductively coupled to the semiconductor film 13 on the side 13SD-1 of source/drain region via coupling aperture H1.Coupling aperture H1 quilt
It is arranged in interlayer dielectric 18B and 18C and gate insulating film 19.For example, lower electrode 16B and top electrode 16U by doped with
The polysilicon film of such as impurity of phosphorus (P) is constituted.Lower electrode 16B and top electrode 16U can be made of metal material.For example, being situated between
Electric layer 16I is made of silicon nitride film.Dielectric layer 16I is preferably made of insulating film, and the dielectric constant of the insulating film is higher than silica
The dielectric constant of film.
Photomask 17 on holding capacitor device 16 applies light to transistor Tr for preventing.Photomask 17 for example with guarantor
The identical flat shape of capacitor 16 is held, and position Chong Die with holding capacitor device 16 in the plan view is set.Namely
Say, photomask 17 at least cover semiconductor film 13 channel region 13C, LDD region 13L-1 and 13L-2 and source/drain region 13SD-1 and
13SD-2 and gate electrode 14.Preferably, photomask 17 also covers coupling aperture H1.This allows to be effectively prevented light and enters half
The source/drain region 13SD-1 of electrically conductive film 13.Preferably, photomask also covers shading wall 15A and 15B.This allows light to enter
Gap is smaller, to allow more effective light shield.Photomask 17 for example passes through shading refractory metal or refractory metal silicon
Compound is constituted.The example of shading refractory metal includes tungsten, and the example of shading refractory metal silicide includes tungsten silicide.
For example, the pixel electrode 20 in TFT substrate 10 is arranged for each pixel and is conductively coupled to transistor Tr.It is opposed
Electrode 23 is arranged in counter substrate 24, using the electrode shared as multiple pixels, and is maintained at such as common potential.Liquid crystal
Layer 22 is made of liquid crystal, to be driven by VA (vertical centering) mode, TN (twisted-nematic) mode, IPS (in-plane switching) mode etc..
Centering film 21a and centering film 21b is separately positioned on 22 side of surface and liquid crystal layer of the pixel electrode 20 on 22 side of liquid crystal layer
Opposite electrode 23 surface on.
For example, above-mentioned liquid crystal display device 1 (Fig. 6 A to Figure 10 B) can be manufactured by the following method.
Firstly, sequentially forming adhesion-layer materials film 12aM and conductive film 12M on the substrate 11.Hereafter, as shown in Figure 6A, sharp
The pattern of resist RS is formed in the presumptive area on conductive film 12M with photoetching technique.Then, it will be bonded using etching technique
Layer material film 12aM and conductive film 12M patterning, to form adhesive layer 12a and scan line 12.Forming adhesive layer 12a and scanning
After line 12, resist RS is removed.
Then, as shown in Figure 6B, it is formed after interlayer dielectric 18A in the whole surface of substrate 11, executes CMP and (change
Learn mechanical polishing) it handles to planarize the surface (Fig. 6 C) of interlayer dielectric 18A.
Later, as shown in Figure 7 A, semiconductor film 13 is formed in the presumptive area on interlayer dielectric 18A.For example, passing through
Amorphous silicon film, polysilicon film etc. are formed on interlayer dielectric 18A, and then using photoetching technique and etching technique to its into
Row patterning is to form semiconductor film 13.It is handled by carrying out impurity introducing appropriate when forming semiconductor film 13, heat treatment
Deng characteristic of semiconductor can be improved.
As shown in Figure 7 B, after forming semiconductor film 13, the grid of covering semiconductor film 13 and interlayer dielectric 18A are formed
Pole insulating film 19.For example, can use CVD method forms silicon oxide film, silicon nitride film etc. to form gate insulating film 19.Grid
Insulating film 19 can also be formed by heat oxide film.
Then, as seen in figure 7 c, it is formed after conductive film 14M on gate insulating film 19, by means of photoetching technique and erosion
Lithography patterns conductive film 14M.This forms gate electrode 14 (Fig. 8 A).For example, can will be doped with impurity (such as phosphorus)
Polysilicon film is used as conductive film 14M.By progress impurity importing processing appropriate, heat treatment etc., gate electrode 14 can formed
The characteristic of Shi Tigao gate electrode 14.
As shown in figs. 8 b and 8 c, after forming gate electrode 14, covering grid electrode 14 and gate insulating film 19 are formed
Interlayer dielectric 18B, and make its surface planarisation using CMP processing etc..Then, as shown in fig. 9 a and fig. 9b, penetrated bed is formed
Between insulating film 18B and gate insulating film 19 and reach the through-hole SA15 and SB15 of scan line 12.In two lateral edges of semiconductor film 13
Semiconductor film 13 extending direction formed through-hole SA15 and SB15.
The method to form through-hole SA15 and SB15 is more specifically described.Firstly, as shown in Figure 9 A, through-hole SA15 and SB15 is each
From for example primary formation is etched using anisotropic dry, width (distance in Y-direction) range is not up to gate electrode 14.This
When, through-hole SA15 and SB15 do not extend into gate electrode 14, therefore can prevent from spreading due to plasma damage caused by handling
To transistor Tr (gate electrode 14).It then, as shown in Figure 9 B, for example, will be every by wet etching, anisotropic dry etching etc.
The width of a through-hole SA15 and SB15 is widened to gate electrode 14.Such as wet etching or the method for anisotropic dry etching will not
Plasma damage is caused to gate electrode 14, therefore the characteristic of transistor Tr will not be reduced.This two-stage processing allows to be formed
Through-hole SA15 and SB15.For example, in the case where that need not consider the plasma damage to gate electrode 14, can also by it is each to
Anisotropic dry etching forms through-hole SA15 and SB15 with a phase process.
For example, after forming through-hole SA15 and SB15, titanium nitride and tungsten are sequentially formed in through-hole SA15 and SB15
Film.Later, the excessive titanium nitride and excessive tungsten on interlayer dielectric 18 are removed by CMP processing or etch-back process.This
Barrier metal layer 15Ab and shading wall 15A is formed in through-hole SA15, and barrier metal layer 15Bb and screening are formed in through-hole SB15
Light wall 15B (Figure 10 A).
As shown in Figure 10 B, after forming shading wall 15A and 15B, the upper end for covering each shading wall 15A and 15B is formed
And the interlayer dielectric 18C of interlayer dielectric 18B.Then, using photoetching technique and etching technique on interlayer dielectric 18C
Presumptive area in form lower electrode 16B, dielectric layer 16I, top electrode 16U and photomask 17.This forms TFT substrate 10.
After forming TFT substrate 10, pixel electrode 20 and centering film 21a are formed in TFT substrate 10.Meanwhile right
It sets and forms opposite electrode 23 and centering film 21b on the side of substrate 24.By the way that above-mentioned TFT substrate 10 and counter substrate 24 is laminated simultaneously
Inject liquid crystal therebetween to form liquid crystal layer 22.This completes liquid crystal display devices 1 shown in FIG. 1.
(operation)
In liquid crystal display device 1, to the light transmittance of each pixel control liquid crystal layer 22, so that figure of the transmitting based on input
As the light with contrast of signal.Transistor Tr is conductively coupled to pixel electrode 20 and executes the switching control of pixel electrode 20.
(work and effect)
In the liquid crystal display device 1 of the present embodiment, shading the wall 15A and 15B of flush plug structure are arranged on TFT
In substrate 10, therefore aperture ratio can be kept and inhibit the generation of TFT leakage current.Hereinafter, (compare and show with reference to comparative example
Example 1 and 2) this is described in detail.
Figure 11 shows the planar structure of the TFT substrate according to comparative example 1 (TFT substrate 100).Figure 12 is TFT substrate
The perspective view of 100 structure.In TFT substrate 100, photomask 170 is set using the upper layer as gate electrode 14.Photomask 170
A part of covering grid electrode 14.Photomask 170 is conductively coupled to gate electrode 14 via coupling aperture 151, and also via coupling aperture
152 are conductively coupled to scan line 12.Coupling aperture 151 along the extending direction (X-direction in Figure 11) with semiconductor film 13 substantially
Orthogonal direction (Y-direction in Figure 11) is arranged on gate electrode 14.Coupling aperture 152 is along the extending direction with semiconductor film 13
Semiconductor film 13 of the essentially parallel directions (X-direction in Figure 11) on the two sides of semiconductor film 13 is arranged.Coupling
Hole 152 is arranged transverse to the channel region 13C, LDD region 13L-1 and source/drain region 13SD-1 of semiconductor film 13.It is arranged in coupling aperture
Photomask 170 in 152 prevents light from entering semiconductor film 13 from side.
Figure 13 shows the planar structure of the TFT substrate according to comparative example 2 (TFT substrate 101).In TFT substrate 101
In, coupling aperture 152 is arranged longer than TFT substrate 100, and photomask 170 transverse to semiconductor film 13 channel region 13C,
LDD region 13L-1 and 13L-2 and source/drain region 13SD-1 and 13SD-2 setting.Therefore, TFT substrate 101 can compare TFT substrate
100, which more efficiently prevent from light, enters semiconductor film 13 from side.
However, for light-shielding characteristic, aperture ratio and transistor characteristic, it may in this TFT substrate 100 and 101
There are following problems.
Firstly, the description for the problem of providing light-shielding characteristic.In TFT substrate 100 and 101, although set up in coupling aperture
Photomask 170 in 152 prevents light from entering semiconductor film 13 from side, but in the case where film formation technology, it is difficult to it is formed
With the photomask 170 of adequate thickness in coupling aperture 152.It is impossible for carrying out light shield appropriate with thin photomask 170
's.Enter in addition, the photomask 170 being arranged in coupling aperture 152 can not be effectively prevented light from 13 side of semiconductor film.This
It is because of even if the light-shielding characteristic with higher of TFT substrate 101, it is also not possible to so that coupling aperture 152 is extended long enough, cause
Many gaps that diffraction light enters.Specifically, it is impossible to transverse to what holding capacitor device 16 and semiconductor film 13 were coupled to each other
Coupling aperture 152 is arranged in coupling aperture H1.
Next, the description for the problem of providing aperture ratio.By forming simultaneously pattern after forming coupling aperture 151 and 152
Change photomask 170 to manufacture TFT substrate 100 and 101.In such manufacturing process, the width for reducing coupling aperture 152 may draw
The trouble for forming photomask 170 is acted, and therefore the width of coupling aperture 152 tends to broaden.In addition, coupling aperture 152 and photomask
170 position alignment is necessary, it is therefore necessary to allow scheduled space to ensure region.For these reasons, it is difficult to improve
Aperture ratio.
Then, the description for the problem of providing transistor characteristic.In TFT substrate 100 and 101, coupling can be formed simultaneously
Hole 151 and 152.However, in this case, after coupling aperture 151 reaches gate electrode 14, subsequently forming coupling aperture 152.Knot
Fruit carries out over etching to gate electrode 14.In the case where gate electrode 14 includes metal, is reacted and produced due to caused by over etching
Object adheres to the inside of coupling aperture 151 and may cause deficiencies in electrical conductivity.In addition, may half-and-half be led when forming coupling aperture 151
Body film 13, gate electrode 14 and gate insulating film 19 cause plasma damage.Specifically, in amorphous silicon, polysilicon etc. for half
In the TFT substrate 100 and 101 of electrically conductive film 13, the gate insulating film 19 as caused by the overcurrent element in corona treatment
Deterioration compare in MOS (metal-oxide semiconductor (MOS)) equipment be easier.This is because on the substrate 11 for including quartz, half
Electrically conductive film 13 and gate electrode 14 are electrically floating.
On the contrary, in the present embodiment, the shading wall 15A and 15B of flush plug structure is arranged transverse to semiconductor film 13.
Therefore, for light-shielding characteristic, aperture ratio and transistor characteristic, it is more advantageous than TFT substrate 100 and 101.With reference to Figure 14 and
This is described in Figure 15.Figure 14 is the vertical of the major part for the TFT substrate 10 for removing holding capacitor device 16 and photomask 17
Body figure.Figure 15 is that the perspective view of TFT substrate 10, wherein holding capacitor device 16 and photomask 17 are added to the TFT substrate in Figure 14.
Shading wall 15A and 15B with flush plug structure can be formed, with enough thickness.Furthermore it is possible to
Shading wall 15A and 15B is set in the broader region of coupling aperture 152 than TFT substrate 100 and 101, so as to improve optical screen
Cover characteristic.Shading wall 15A and 15B at least transverse to the channel region 13C of semiconductor film 13, LDD region 13L-1 and 13L-2 and source/
Drain region 13SD-1 and 13SD-2 setting, and therefore, it is arranged in the wider range of the coupling aperture 152 than TFT substrate 100.This
Outside, shading wall 15A and 15B is also arranged transverse to coupling aperture H1, and therefore can be in the model of the coupling aperture 152 than TFT substrate 101
Enclose broader range inner shield light.In TFT substrate 10, transistor Tr is scanned line 12 from downside and surrounds, and is hidden from cross side
Light wall 15A and 15B are surrounded, and are surrounded from upside by photomask 17, therefore light can dimensionally be inhibited to enter transistor Tr (figure
14 and Figure 15).In such TFT substrate 10, the gap that diffraction light enters is smaller, therefore allows to own to including stray light
Light is adequately shielded.
Figure 16 indicates the semiconductor film 13 for entering TFT substrate 10,101 and 101 using FDTD (Finite difference time domain) simulation
LDD region 13L-1 and 13L-2 light energy calculated result.Light intensity of the TFT substrate 10 in LDD region 13L-1 and 13L-2
Degree is respectively less than the luminous intensity of TFT substrate 100 and 101, and suitably provides light shield.In TFT substrate 100, into LDD
The luminous intensity of the light strength ratio TFT substrate 10 of area 13L-2 is 21.1 times high, and enters the light strength ratio TFT base of LDD region 13L-1
The luminous intensity of plate 10 is 3.0 times high.In TFT substrate 101, the luminous intensity into LDD region 13L-2 is the luminous intensity of TFT substrate 10
2 times, and enter LDD region 13L-1 light strength ratio TFT substrate 10 luminous intensity it is 1.6 times high.
In addition, can reduce in the through-hole SA15 and SB15 of shading wall 15A and 15B for forming flush plug structure
Its width, and the problem of be furthermore not in position alignment.Therefore, aperture ratio is maintained.For example, in 0.64WUXGA panel
In, estimate the aperture ratio of TFT substrate 10 and the aperture ratio of TFT substrate 101.As a result, the aperture ratio in TFT substrate 101 is
While 65.5%, the aperture ratio of TFT substrate 10 is 67%.In addition, forming shading wall 15A and 15B in TFT substrate 10
When do not need to pattern, therefore allow simplify manufacturing process.
In addition, gate electrode 14 is not subjected to over etching in the forming process of through-hole SA15 and SB15.In addition, institute as above
It states, through-hole SA15 and SA16 can be formed while inhibiting the plasma damage to gate electrode 14.Therefore, crystal is maintained
The characteristic of pipe Tr.
As described above, in the present embodiment, the shading wall 15A and 15B and shading for providing flush plug structure are swept
Line 12 is retouched, so as to inhibit the generation of the leakage current of transistor Tr as caused by the application of light, maintains aperture ratio.
It can also keep the characteristic of transistor Tr.
In addition, be additionally provided with photomask 17, so as to together with scan line 21 and shading wall 15A and 15B more effectively
Light is prevented to be applied to transistor Tr.
[modified example]
In the aforementioned embodiment, the case where being provided separately notwithstanding photomask 17 and holding capacitor device 16, but can
Shading holding capacitor device 16 is arranged and can be omitted photomask 17.Specifically, if light-shielding conductive film is used for lower electrode
16D, top electrode 16U or both are then enough.Light-shielding conductive film includes such as aluminium (Al), titanium (Ti).
[applying example]
For example, the liquid crystal display device 1 of this technology can be applied to projection display device.
Figure 17 is to show that (projection type is aobvious using the projection display device that the application of liquid crystal display device 1 is light modulation device
Showing device 200) topology example schematic diagram.Projection display device 200 is the display for example projected image on screen
Device.Projection display device 200 is for example couple to external image via I/F (interface) and provides device (such as calculating of PC class
Machine or various types of image players), and projection etc. is executed based on the picture signal for being input to I/F on the screen.Note that
The structure of projection display device 200 described below is example, and is not limited to according to the projection display device of this technology
This structure.
Projection display device 200 includes light source 211, multi lens array 212, PbS array 213, condenser lens 214, anti-
Penetrate mirror 215, dichroscope 216 and 217, light modulation device 218a to 218c, dichroic prism 219 and projecting lens 220.Example
Such as, the liquid crystal display device 1 of previous embodiment is used as each of light modulation device 218a to 218c.
Light source 211 is by reflector 211b by the light output emitted by luminescence unit 211a to multi lens array 212.Mostly thoroughly
There are multiple lens elements to be arranged as array and collect the structure of the light exported from light source 211 for lens array 212.Example
Such as, PbS array 213 is by the light polarization collected by multi lens array 212 at the light in predetermined polarisation direction, such as P polarization wave.It focuses
Lens 214 collect the light for having been converted into the light in predetermined polarisation direction by PbS array 213.
The transmission of dichroscope 216 enters the feux rouges R of the light of dichroscope 216 via condenser lens 214 and reflecting mirror 215,
And reflect green light G and blue light B.The feux rouges R transmitted by dichroscope 216 is directed into light modulation device via reflecting mirror 215
218a。
Dichroscope 217 transmits the blue light B of the light reflected by dichroscope 216 and reflects green light G.By dichroscope 217
The green light G of reflection is directed into light modulation device 218b.Meanwhile the blue light B transmitted by dichroscope 217 is via reflecting mirror 215
It is directed into light modulation device 218c.
Each of light modulation device 218a to 218c modulates the incident light of each color, and by the modulation of each color
Light is input in dichroic prism 219.The photosynthetic of modulated and input each color is become single by dichroic prism 219
Optical axis.The synthesis light of each color projects on screen etc. via projecting lens 220.
In projection display device 200, corresponding to as trichromatic red, three three kinds of colors of green and blue
Light modulation device 218a to 218c is combined to show each color.That is, projection display device 200 is so-called three
CCD projection display device.
Other than above-mentioned projection display device, liquid crystal display device 1 applies also for television equipment, desk-top personal meter
The monitor of calculation machine, the imaging device of laptop PC, such as video camera or digital still camera, PDA (a number
Word assistant) and such as mobile phone or smart phone electronic device.
Although giving the description to this technology by reference to embodiment and modified example, this technology is not limited to aforementioned
Embodiment etc., and it can be carry out various modifications.For example, the portion of the liquid crystal display device illustrated in the aforementioned embodiment
Part, arrangement, quantity etc. are only example, and need not have all components, and can further include other component.
Note that effect described herein is only illustrative, and without being limited thereto, it may also include other effects.
Note that the technology can have following configuration.
(1)
A kind of liquid crystal display device, comprising:
Scan line has light-shielding characteristic；
Semiconductor film is arranged in face of scan line and has source/drain region and the channel region between source/drain region；
Gate electrode, in face of the channel region of semiconductor film；
First interlayer dielectric, covering grid electrode；And
Shading wall penetrates the first interlayer dielectric and gate electrode and scan line is electrically coupled to each other, and shading wall is transverse to half
The channel region of electrically conductive film and the source/drain region of semiconductor film are upright.
(2)
It further include substrate according to the liquid crystal display device of (1), wherein
Scan line, semiconductor film, gate electrode and the first interlayer dielectric are successively set on substrate.
(3)
According to the liquid crystal display device of (2), further includes:
Second interlayer dielectric, between scan line and semiconductor film；And
Gate insulating film, between semiconductor film and gate electrode, wherein
Shading wall is arranged in the first interlayer dielectric, gate insulating film and the second interlayer dielectric.
(4)
According to (1) to the liquid crystal display device of any one of (3), wherein shading wall is stood on the two sides of semiconductor film.
(5)
According to (1) to the liquid crystal display device of any one of (4), wherein shading wall has the lower end contacted with scan line,
And shading wall contacts between lower end and upper end with gate electrode.
(6)
According to the liquid crystal display device of (5), wherein the upper end of shading wall and the upper surface of the first interlayer dielectric are constituted together
One plane.
(7)
According to (1) to the liquid crystal display device of any one of (6), wherein scan line is in the plan view than gate electrode and half
Electrically conductive film is wide, and is arranged at the position Chong Die with gate electrode and semiconductor film.
(8)
It further include the holding capacitor on the first interlayer dielectric according to (1) to the liquid crystal display device of any one of (7)
Device, holding capacitor device successively have lower electrode, dielectric layer and top electrode.
(9)
According to the liquid crystal display device of (8), wherein
Lower electrode, top electrode or both have light-shielding characteristic, and
The ditch of covering grid electrode in the plan view, the source/drain region of semiconductor film and semiconductor film is set in holding capacitor device
At the position in road area.
(10)
According to the liquid crystal display device of (8) or (9), wherein shading wall is also transverse to by holding capacitor device and semiconductor film
The coupling aperture being coupled to each other is upright.
(11)
It further include the photomask on the first interlayer dielectric according to (1) to the liquid crystal display device of any one of (8),
Photomask covers the channel region and gate electrode of the source/drain region of semiconductor film, semiconductor film in the plan view.
(12)
According to the liquid crystal display device of (11), wherein photomask is made of metal or metal silicide.
(13)
According to (1) to the liquid crystal display device of any one of (12), including in the source/drain region of semiconductor film and semiconductor film
Channel region between LDD (lightly doped drain) area.
(14)
According to (1) to the liquid crystal display device of any one of (13), wherein shading wall consists of metal.
(15)
According to (1) to the liquid crystal display device of any one of (14), wherein scan line consists of metal.
(16)
A kind of projection display device, comprising:
Light source；
Optic modulating device enters optic modulating device from the light of light source output；And
Projecting lens, the light exported from optic modulating device enter projecting lens,
Optic modulating device includes
Scan line has light-shielding characteristic,
Semiconductor film is arranged in face of scan line and has source/drain region and the channel region between source/drain region,
Gate electrode, in face of the channel region of semiconductor film,
First interlayer dielectric, covering grid electrode, and
Shading wall penetrates the first interlayer dielectric and gate electrode and scan line is electrically coupled to each other, and shading wall is transverse to half
The channel region of electrically conductive film and the source/drain region of semiconductor film are upright.
This application claims the Japanese Priority Patent Application 2016- submitted on October 18th, 2016 to Japanese Patent Office
204441 equity, entire contents are incorporated herein by reference.
It should be appreciated that those skilled in the art can imagine various modifications, combination, son according to design requirement and other factors
Combination and change, as long as they are in the range of appended claims or its equivalent.
Claims (16)
1. a kind of liquid crystal display device, comprising:
Scan line has light-shielding characteristic；
Semiconductor film is arranged in face of the scan line and has source/drain region and the channel region between the source/drain region；
Gate electrode, in face of the channel region of the semiconductor film；
First interlayer dielectric covers the gate electrode；And
Shading wall penetrates first interlayer dielectric and the gate electrode and the scan line is electrically coupled to each other, the screening
Light wall is upright transverse to the channel region of the semiconductor film and the source/drain region of the semiconductor film.
2. liquid crystal display device according to claim 1 further includes substrate, wherein
The scan line, the semiconductor film, the gate electrode and first interlayer dielectric are successively set on the substrate
On.
3. liquid crystal display device according to claim 2, further includes:
Second interlayer dielectric, between the scan line and the semiconductor film；And
Gate insulating film, between the semiconductor film and the gate electrode, wherein
The shading wall is arranged in first interlayer dielectric, the gate insulating film and second interlayer dielectric.
4. liquid crystal display device according to claim 1, wherein the shading wall stands on the two sides of the semiconductor film
On.
5. liquid crystal display device according to claim 1, wherein the shading wall has to be contacted down with the scan line
End, and the shading wall contacts between the lower end and upper end with the gate electrode.
6. liquid crystal display device according to claim 5, wherein the upper end of the shading wall and first interlayer
The upper surface of insulating film constitutes same plane.
7. liquid crystal display device according to claim 1, wherein the scan line in the plan view than the gate electrode and
The semiconductor film is wide, and is arranged at the position Chong Die with the gate electrode and the semiconductor film.
8. liquid crystal display device according to claim 1 further includes the holding capacitor on first interlayer dielectric
Device, the holding capacitor device successively have lower electrode, dielectric layer and top electrode.
9. liquid crystal display device according to claim 8, wherein
The lower electrode, described top electrode or both have light-shielding characteristic, and
The holding capacitor device be set cover in the plan view the gate electrode, the semiconductor film the source/drain region and
At the position of the channel region of the semiconductor film.
10. liquid crystal display device according to claim 8, wherein the shading wall is also transverse to by the holding capacitor
The coupling aperture that device and the semiconductor film are coupled to each other is upright.
11. liquid crystal display device according to claim 1 further includes the photomask on first interlayer dielectric,
The photomask cover in the plan view the source/drain region of the semiconductor film, the semiconductor film the channel region and
The gate electrode.
12. liquid crystal display device according to claim 11, wherein the photomask is by metal or metal silicide structure
At.
13. liquid crystal display device according to claim 1, including in the source/drain region of the semiconductor film and described
LDD (lightly doped drain) area between the channel region of semiconductor film.
14. liquid crystal display device according to claim 1, wherein the shading wall consists of metal.
15. liquid crystal display device according to claim 1, wherein the scan line consists of metal.
16. a kind of projection display device, comprising:
Light source；
Optic modulating device, light output from light source output enter the optic modulating device；And
Projecting lens, the light exported from the optic modulating device enter the projecting lens,
The optic modulating device includes
Scan line has light-shielding characteristic,
Semiconductor film is arranged in face of the scan line and has source/drain region and the channel region between the source/drain region,
Gate electrode, in face of the channel region of the semiconductor film,
First interlayer dielectric covers the gate electrode, and
Shading wall penetrates first interlayer dielectric and the gate electrode and the scan line is electrically coupled to each other, the screening
Light wall is upright transverse to the channel region of the semiconductor film and the source/drain region of the semiconductor film.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016-204441 | 2016-10-18 | ||
| JP2016204441 | 2016-10-18 | ||
| PCT/JP2017/030301 WO2018074060A1 (en) | 2016-10-18 | 2017-08-24 | Liquid crystal display device and projection display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109804307A true CN109804307A (en) | 2019-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201780062196.9A Pending CN109804307A (en) | 2016-10-18 | 2017-08-24 | Liquid crystal display device and projection display device |
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| Country | Link |
|---|---|
| JP (1) | JP6961604B2 (en) |
| CN (1) | CN109804307A (en) |
| WO (1) | WO2018074060A1 (en) |
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| JP7409115B2 (en) | 2020-01-30 | 2024-01-09 | セイコーエプソン株式会社 | Electro-optical devices and electronic equipment |
| JP7322727B2 (en) | 2020-01-30 | 2023-08-08 | セイコーエプソン株式会社 | electro-optical devices and electronic devices |
| JP7327184B2 (en) | 2020-01-30 | 2023-08-16 | セイコーエプソン株式会社 | electro-optical devices and electronic devices |
| JP7409236B2 (en) * | 2020-06-26 | 2024-01-09 | セイコーエプソン株式会社 | Electro-optical devices and electronic equipment |
| JP7396223B2 (en) | 2020-07-28 | 2023-12-12 | セイコーエプソン株式会社 | Electro-optical devices and electronic equipment |
| JP2022055921A (en) * | 2020-09-29 | 2022-04-08 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
| JP2022057172A (en) | 2020-09-30 | 2022-04-11 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
| JP2022070450A (en) | 2020-10-27 | 2022-05-13 | セイコーエプソン株式会社 | Electro-optical device, and electronic apparatus |
| CN113451332B (en) * | 2021-06-21 | 2023-10-27 | 昆山国显光电有限公司 | Array substrate and display panel |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499459A (en) * | 2002-10-31 | 2004-05-26 | 精工爱普生株式会社 | Electrooptical device and electronic appliance |
| US20090065780A1 (en) * | 2007-09-10 | 2009-03-12 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
| JP2012108407A (en) * | 2010-11-19 | 2012-06-07 | Seiko Epson Corp | Electro-optic device, method of manufacturing electro-optic device, and electronic apparatus |
| CN103116237A (en) * | 2011-11-16 | 2013-05-22 | 索尼公司 | Liquid crystal display panel and liquid crystal projector |
| CN105140294A (en) * | 2015-08-11 | 2015-12-09 | 武汉华星光电技术有限公司 | Low temperature poly silicon thin film transistor and fabrication method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3356429B2 (en) * | 2000-04-11 | 2002-12-16 | 日本電気株式会社 | Liquid crystal display device and liquid crystal projector device |
| JP4233307B2 (en) * | 2002-11-05 | 2009-03-04 | シャープ株式会社 | Active matrix substrate and display device |
| JP4654675B2 (en) * | 2004-12-14 | 2011-03-23 | ソニー株式会社 | LCD panel |
-
2017
- 2017-08-24 WO PCT/JP2017/030301 patent/WO2018074060A1/en active Application Filing
- 2017-08-24 CN CN201780062196.9A patent/CN109804307A/en active Pending
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499459A (en) * | 2002-10-31 | 2004-05-26 | 精工爱普生株式会社 | Electrooptical device and electronic appliance |
| US20090065780A1 (en) * | 2007-09-10 | 2009-03-12 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
| JP2012108407A (en) * | 2010-11-19 | 2012-06-07 | Seiko Epson Corp | Electro-optic device, method of manufacturing electro-optic device, and electronic apparatus |
| CN103116237A (en) * | 2011-11-16 | 2013-05-22 | 索尼公司 | Liquid crystal display panel and liquid crystal projector |
| CN105140294A (en) * | 2015-08-11 | 2015-12-09 | 武汉华星光电技术有限公司 | Low temperature poly silicon thin film transistor and fabrication method thereof |
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| JPWO2018074060A1 (en) | 2019-08-08 |
| JP6961604B2 (en) | 2021-11-05 |
| WO2018074060A1 (en) | 2018-04-26 |
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