JP2013246358A - Liquid crystal panel, method for manufacturing liquid crystal panel, and liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal panel capable of easily and effectively preventing light from entering a transistor, a method for manufacturing a liquid crystal panel and a liquid crystal display device.SOLUTION: There is provided a liquid crystal panel which comprises: a TFT substrate on which a transistor is formed; a counter substrate facing the TFT substrate; and a liquid crystal layer sandwiched by the TFT substrate and the counter substrate, wherein the TFT substrate comprises: a wiring pattern as a scan line connected to the transistor; a semiconductor layer provided on a first interlayer insulating film for covering the wiring pattern; a gate electrode provided on the semiconductor layer in a state of crossing along a direction vertical to the extending direction of the scan line through the gate insulating film; and an auxiliary capacitance which is laminated on a second interlayer insulating film for covering a channel region and the upper part of an LED region on the output side of the transistor and is connected to the transistor through a connection hole formed on the longitudinal axis on the output side of the transistor.

Description

  The present technology relates to a liquid crystal panel, a method for manufacturing a liquid crystal panel, and a liquid crystal display device, and more particularly to a technology for shielding light incident on a transistor formed in the liquid crystal panel.

  Conventionally, a liquid crystal using a liquid crystal panel comprising a TFT substrate on which transistors and pixel electrodes are formed, a counter substrate disposed opposite to the TFT substrate, and a liquid crystal sandwiched between the TFT substrate and the counter substrate Display devices are known.

  In such a liquid crystal display device, when strong light is incident on the transistor, a light leakage current is generated, causing image quality defects such as flicker. Therefore, it is important to suppress light leakage current by blocking light incidence on the transistor (see, for example, Patent Document 1).

  Patent Document 1 discloses a technique for realizing light shielding to a channel region by integrally surrounding a channel region in a semiconductor layer constituting a transistor with a gate electrode and a wiring pattern arranged with the channel region interposed therebetween. Has been.

JP 2006-171136 A

  However, the technique disclosed in Patent Document 1 has a problem that light shielding from above the transistor, that is, light shielding from the counter substrate side is incomplete. In particular, carriers generated in the LDD region on the output side constituting the transistor greatly contribute to the light leakage current. For this reason, light shielding from above the LDD portion on the output side is necessary, but such light shielding has not been sufficiently studied.

  In the technique disclosed in Patent Document 1, a signal wiring or a relay wiring to the pixel electrode is arranged as a light shielding film above the transistor. However, in order to secure the light shielding property with such a configuration, it is necessary to form the wiring width larger than the minimum processing dimension, which has been a barrier to reducing the pixel pitch. In addition, the transistor and the auxiliary capacitor are formed in the same layer. Therefore, in order to reduce the pixel pitch, it is necessary to reduce the area of the auxiliary capacitor, and there is a concern about the occurrence of image quality defects.

  The present technology has been made in view of the above problems, and is to provide a liquid crystal panel, a method for manufacturing a liquid crystal panel, and a liquid crystal display device that can easily and effectively suppress light incidence to a transistor.

  A liquid crystal panel according to an embodiment of the present technology includes a TFT substrate on which a transistor is formed, a counter substrate facing the TFT substrate, and a liquid crystal layer sandwiched between the TFT substrate and the counter substrate. A wiring pattern as a scanning line connected to the transistor, a semiconductor layer provided on a first interlayer insulating film covering the wiring pattern, and a gate insulating film on the semiconductor layer via the gate insulating film. A gate electrode provided so as to cross along a direction perpendicular to the extending direction, and a second interlayer insulating film covering the channel region of the transistor and the LDD region on the output side; And an auxiliary capacitor connected to the transistor through a connection hole formed on the long axis on the output side.

  In the liquid crystal panel according to the present technology, preferably, a light-shielding film is formed on at least one electrode of the auxiliary capacitor.

  In the liquid crystal panel according to the present technology, preferably, a light-shielding film is formed on at least a part of the gate electrode.

  In the liquid crystal panel according to the present technology, it is preferable that the auxiliary capacitor is formed so as not to be above the LDD region on the input side of the transistor.

  In the liquid crystal panel according to the present technology, preferably, the first interlayer insulating film is planarized by a CMP process.

  A liquid crystal panel manufacturing method according to the present technology includes a TFT substrate on which a transistor is formed, a counter substrate facing the TFT substrate, and a liquid crystal layer sandwiched between the TFT substrate and the counter substrate. A method for manufacturing a panel, the step of forming a wiring pattern as a scanning line on a support substrate of the TFT substrate, the step of forming a semiconductor layer on a first interlayer insulating film covering the wiring pattern, A step of providing a gate electrode on the semiconductor layer through a gate insulating film along a direction perpendicular to the extending direction of the scanning line, and covering the channel region of the transistor and the LDD region on the output side Providing an auxiliary capacitor connected to the transistor via a connection hole formed on the long axis on the output side of the transistor on the second interlayer insulating film. That.

  A liquid crystal display device according to an embodiment of the present technology includes a TFT substrate on which a transistor is formed, a counter substrate facing the TFT substrate, and a liquid crystal layer sandwiched between the TFT substrate and the counter substrate, and the TFT substrate A wiring pattern as a scanning line connected to the transistor, a semiconductor layer provided on a first interlayer insulating film covering the wiring pattern, and the scanning line on the semiconductor layer via a gate insulating film A gate electrode provided so as to cross along a direction perpendicular to the extending direction of the transistor and a second interlayer insulating film that covers the channel region of the transistor and the upper side of the LDD region on the output side. And an auxiliary capacitor connected to the transistor through a connection hole formed on the long axis on the output side of the transistor.

  According to the present technology, light incidence on the transistor can be easily and effectively suppressed.

The top view which shows the structural example of the TFT substrate of the liquid crystal panel which concerns on this technique. FIG. 2 is a cross-sectional view taken along line A-A ′ in the plan view of FIG. 1. B-B 'sectional drawing in the top view of FIG. FIG. 2 is a C-C ′ sectional view in the plan view of FIG. 1. The figure which shows the 1st modification of the B-B 'cross section in the top view of FIG. The figure which shows the 2nd modification of the B-B 'cross section in the top view of FIG. The figure which shows the 3rd modification of the B-B 'cross section in the top view of FIG. The figure which shows the 4th modification of the B-B 'cross section in the top view of FIG. The figure which shows the structure of the liquid crystal panel for simulation which concerns on this technique. The figure which shows the structure of the liquid crystal panel for simulation which concerns on a reference example. The figure which shows the simulation result of the light intensity distribution of the TFT substrate of the liquid crystal panel which concerns on this technique. The figure which shows the simulation result of the light intensity distribution of the TFT substrate of the liquid crystal panel which concerns on a reference example. The figure which shows the measurement result of the leakage current in the liquid crystal panel which concerns on this technique. The figure which shows an example of the manufacturing method of the liquid crystal panel which concerns on this technique. The figure which shows an example of the manufacturing method of the liquid crystal panel which concerns on this technique. The figure which shows an example of the manufacturing method of the liquid crystal panel which concerns on this technique. The figure which shows the structural example of the liquid crystal display device which concerns on this technique.

  In the present technology, in a liquid crystal panel, a semiconductor layer provided on a wiring pattern as a scanning line via an interlayer insulating film, and a direction perpendicular to the extending direction of the scanning line on the semiconductor layer via a gate insulating film And stacked on an interlayer insulating film covering the upper part of the channel region of the transistor and the LDD region on the output side, and formed on the long axis on the output side of the transistor. With the configuration including the auxiliary capacitor connected to the transistor through the connection hole, light incidence to the transistor is easily and effectively prevented, and image quality deterioration due to light incidence is prevented. Hereinafter, embodiments of the present technology will be described.

[Configuration of TFT substrate of liquid crystal panel]
FIG. 1 is a plan view showing a configuration example of a TFT substrate of a liquid crystal panel according to the present technology. FIG. 2 is a cross-sectional view taken along the line AA ′ in the plan view of FIG. 3 is a cross-sectional view taken along the line BB ′ in the plan view of FIG. 4 is a cross-sectional view taken along the line CC ′ in the plan view of FIG. Only the TFT substrate 101 and the counter substrate 102 and the liquid crystal layer 103 are shown in FIG. 4 alone.

  In the TFT substrate of the liquid crystal panel 100 according to the present technology, the wiring pattern 1 is provided on the support substrate 31 (hereinafter also referred to as “substrate 31”), and the interlayer insulating film 11 (see FIG. 2 to FIG. (Shown only in FIG. 4). A thin film transistor (hereinafter also referred to as “TFT”) in which a semiconductor layer 2 including a channel, a gate insulating film 12 (shown only in FIGS. 2 to 4), and a gate electrode 7 are stacked in this order on the interlayer insulating film 11. ) 32 is formed. The wiring pattern 1 is a so-called scanning line. The TFT 32 is formed on the wiring pattern 1 via the interlayer insulating film 11, and the major axis direction of the TFT 32 is parallel to the extending direction of the wiring pattern 1.

  The wiring pattern 1 provided on the substrate 31 also serves as a light shielding film for preventing a malfunction of the TFT 32 and is formed in a shape covering the TFT 32. The wiring pattern 1 is composed of a low reflectance material film such as a tungsten silicide (WSi) film, and has a thickness of 200 nm, for example. The wiring pattern 1 has a predetermined width and extends in the left-right direction on the plan view.

  The interlayer insulating film 11 covering the wiring pattern 1 is made of, for example, a silicon oxide film, and is provided on the entire surface of the substrate 31. The interlayer insulating film 11 is preferably planarized by CMP (Chemical Mechanical Polishing) processing. The unevenness on the surface of the substrate 31 is reduced by the planarization treatment, the workability in forming the upper layer pattern is improved, and the yield can be improved.

  The semiconductor layer 2 provided on the interlayer insulating film 11 is made of a semiconductor thin film such as amorphous silicon or polycrystalline silicon, and is formed on the wiring pattern 1 via the interlayer insulating film 11. In the semiconductor layer 2, the portion where the gate electrode 7 is stacked is the channel region 4 in the TFT 32. In addition, low-concentration regions (Lightly Doped Drain, hereinafter also referred to as “LDD regions”) 3, 5 provided on both sides of the semiconductor layer 2 with the channel region 4 interposed therebetween, respectively. Is formed. Outside the LDD regions 3 and 5 are source / drain regions (hereinafter also referred to as “S / D regions”) 3a and 5a in which carrier impurities are diffused at a high concentration to reduce resistance.

  The gate insulating film 12 covering the semiconductor layer 2 is made of a thermal oxide film or a silicon oxide film or a silicon nitride film formed by a CVD (Chemical Vapor Deposition) method.

  Further, the gate electrode 7 is formed by patterning a laminated film of a polysilicon film to which an impurity such as phosphorus (P) is added and a tungsten silicide film, and is perpendicular to the extending direction of the wiring pattern 1 through the gate insulating film 12. It is provided so as to cross over the central portion of the semiconductor layer 2 along a certain direction. The central portion of the semiconductor layer 2 on which the gate electrode 7 is stacked is used as a channel region 4. The gate electrode 7 has two connection holes 6 formed in the lower interlayer insulating film 11 (including the gate insulating film 12) on both sides of the semiconductor layer 2 with the channel region 4 and the output LDD region 5 interposed therebetween. It is connected to the wiring pattern 1 via The interlayer insulating film 13 covering the gate electrode 7 is made of, for example, a silicon oxide film, and is provided on the entire surface of the substrate 31.

  On the interlayer insulating film 13, an auxiliary capacitor (storage capacitor) 33 is formed by laminating the semiconductor layer 16, the dielectric film layer 17, and the semiconductor layer 18 in this order. The semiconductor layers 16 and 18 are made of a polysilicon film to which an impurity such as phosphorus (P) is added, for example, and are a lower electrode and an upper electrode of the auxiliary capacitor 33, respectively. On the other hand, the dielectric film layer 17 is made of an insulating film having a dielectric constant higher than that of a silicon oxide film such as a silicon nitride film. The auxiliary capacitor 33 is patterned in the shape of the auxiliary capacitor pattern 9 (shown only in FIG. 1). At least a part of the auxiliary capacitance pattern 9 is stacked above the channel region 4 and the LDD region 5 on the output side via an interlayer insulating film 13.

  The semiconductor layer 16 that forms the lower electrode of the auxiliary capacitor 33 is connected to the semiconductor layer 2 through a connection hole 8 formed in the interlayer insulating film 13. The connection hole 8 is on the long axis on the output side of the TFT 32. At least a part thereof is formed.

  The interlayer insulating film 14 covering the auxiliary capacitor 33 is made of, for example, a silicon oxide film, and is provided on the entire surface of the substrate 31.

  As shown in FIG. 2, the semiconductor layer 2 from the lower side and the side in FIG. 2, specifically, by the wiring pattern 1 formed on the substrate 31 and the gate electrode 7 formed in the connection hole 6. Suppresses stray light entering the channel region 4 where the photoexcited carriers contributing to the light leakage are generated and the LDD region 5 on the output side. Further, the auxiliary capacitance 33 patterned in the shape of the auxiliary capacitance pattern 9 can effectively suppress stray light entering from the upper side in FIG. 2 to the semiconductor layer 2, specifically, the LDD region 5 on the output side. it can.

  As shown in FIG. 3, the auxiliary capacitance 33 formed in the connection hole 8 can block stray light from entering the LDD region 5 on the output side from the right side direction in FIG. 3. Thereby, generation | occurrence | production of the light leakage current by light leakage can be prevented further effectively. As a result, the switching characteristics of the TFT 32 can be improved.

  As described above, in the liquid crystal panel 100 according to the present technology, the TFT 32 formed on the wiring pattern 1 via the interlayer insulating film 11 and having a major axis direction parallel to the extending direction of the wiring pattern 1, and the TFT 32 Are formed above the TFT 32 via a connection hole 6 connecting the wiring pattern 1 and the gate electrode 7 on both sides of the TFT and a connection hole 8 formed at least partially on the long axis on the output side of the TFT 32. And an auxiliary capacity 33.

  With the configuration as described above, in the liquid crystal panel 100 according to the present technology, the vicinity of the LDD region 5 on the output side, which is a light leak occurrence site, can be completely shielded, and leakage image quality defects can be improved. In addition, this makes it possible to form the TFT 32 and the auxiliary capacitor 33 in separate layers. Compared to the case where the TFT 32 and the auxiliary capacitor 33 are formed in the same layer, patterns arranged in the same plane are formed in a plurality of layers. By being dispersed, the degree of freedom for reducing the pixel pitch can be improved. Furthermore, compared with the case where the TFT 32 and the pixel potential wiring 34 are connected by one connection hole 8, the auxiliary capacitor 33 is arranged as a relay layer, so that the vertical aspect of the connection hole 8 is reduced, and the plane of the connection hole 8 is reduced. It is also possible to reduce the general dimension, and the degree of freedom for reducing the pixel pitch can be improved.

  As shown in FIG. 4, the semiconductor layer 16 constituting the auxiliary capacitor 33 is connected to the pixel electrode 35 on the surface of the TFT substrate 101 via the pixel potential wiring 34 which is a relay metal wiring layer. As a result, a signal potential (hereinafter also referred to as “pixel potential”) written in the auxiliary capacitor 33 is supplied to the pixel electrode 35 on the surface of the TFT substrate 101. The semiconductor layer 18 constituting the auxiliary capacitor 33 is connected to a constant voltage source for supplying a fixed potential via a fixed potential wiring 36 which is a relay metal wiring layer.

  Also, as shown in FIG. 4, above the TFT substrate 101 is a substrate that is disposed opposite to the substrate with a certain gap, and is disposed with a counter substrate 102 supplied with a fixed potential. The TFT substrate 101 and the counter substrate 102 sandwich a liquid crystal layer 103 in which liquid crystal is sealed. As described above, by using the TFT substrate 101 including the TFT 32 with improved switching characteristics, the liquid crystal panel 100 capable of controlling the potential applied to the liquid crystal layer 103 is configured.

  FIG. 5 is a diagram showing a first modification of the B-B ′ cross section in the plan view of FIG. 1. Hereinafter, a first modification of the B-B ′ cross section will be described.

  As shown in FIG. 5, in the BB ′ cross section according to the first modification, unlike the above-described BB ′ cross section, light shielding films 19 and 20 are formed on the gate electrode 7 and the semiconductor layer 18, respectively. Has been. The light shielding films 19 and 20 are films having a wider absorption wavelength range than the polysilicon film, such as a tungsten silicide (WSi) film. By adopting such a configuration, it becomes possible to block stray light in a wider wavelength range, and a higher light leakage suppression effect can be obtained. Note that only one of the light-shielding films 19 and 20 may be provided according to the required light leakage suppression capability.

  FIG. 6 is a diagram illustrating a second modification of the B-B ′ cross section in the plan view of FIG. 1. Hereinafter, a second modification of the B-B ′ cross section will be described.

  As shown in FIG. 6, in the BB ′ section according to the second modification, the auxiliary capacitor 33 is arranged in a manner to avoid the upper side of the LDD region 3 on the input side, unlike the BB ′ section described above. . The auxiliary capacitor 33 having such a configuration can be realized by making the shape of the auxiliary capacitor pattern 9 (see FIG. 1) away from the upper side of the LDD region 3 on the input side. By adopting such a configuration, the influence of the potential from the member disposed above the LDD region 3 on the input side is mitigated, and the leakage current generated due to the electric field concentration in the depletion region generated in the LDD region 3 Can be effectively suppressed.

  FIG. 7 is a view showing a third modification of the B-B ′ cross section in the plan view of FIG. 1. Hereinafter, a third modification of the B-B ′ cross section will be described.

  As shown in FIG. 7, in the BB ′ cross section according to the third modification, unlike the BB ′ cross section shown in FIGS. 3, 5, and 6, the signal line is located above the LDD region 3 on the input side. A pattern 38 is arranged. With this configuration, the potential placed above the input side LDD region 3 becomes equal to the input potential to the TFT 32, and the influence of the potential from the member placed above the input side LDD region 3 is affected. And an increase in leakage current generated due to electric field concentration in the depletion region generated in the LDD region 3 can be effectively suppressed.

  FIG. 8 is a view showing a fourth modification of the B-B ′ cross section in the plan view of FIG. 1. Hereinafter, a fourth modification of the B-B ′ cross section will be described.

  As shown in FIG. 8, the BB ′ cross section according to the fourth modification differs from the BB ′ cross section shown in FIGS. 3, 5, 6, and 7 and above the LDD region 3 on the input side. A fixed potential is arranged in the. By adopting such a configuration, the influence of the potential from the member disposed above the input side LDD region 3 becomes constant, and the leakage current generated due to the electric field concentration in the depletion region generated in the LDD region 3 Can be effectively suppressed.

[Simulation result by FDTD method]
Next, a simulation result of the light intensity distribution in the vicinity of the semiconductor layer 2 when light is incident from above the TFT 32 in the liquid crystal panel 100 of the present technology will be described. Note that the simulation here is performed by FDTD (Finite Difference Time Domain).

  First, prior to the description of the simulation results, the structure of the liquid crystal panel 100 of the present technology used in the present simulation will be described.

  FIG. 9 is a diagram illustrating a structure of a liquid crystal panel for simulation according to the present technology. FIG. 10 is a diagram illustrating a structure of a simulation liquid crystal panel according to a reference example.

  The liquid crystal panel 100 shown in FIG. 9 shows the structure of the liquid crystal panel 100 shown in FIG. In the liquid crystal panel 100 shown in FIG. 9, an auxiliary capacitor 33 is provided.

  On the other hand, the liquid crystal panel 100a shown in FIG. 10 shows the structure of a conventional liquid crystal panel, and is different from the liquid crystal panel 100 shown in FIG. 9 in that the auxiliary capacitor 33 is not provided. Hereinafter, simulation results will be described.

  FIG. 11 is a diagram illustrating a simulation result of the light intensity distribution of the TFT substrate of the liquid crystal panel according to the present technology. FIG. 12 is a diagram illustrating a simulation result of the light intensity distribution of the TFT substrate of the liquid crystal panel according to the reference example.

  11 and 12, the light intensity distribution when light is incident from above the TFT 32 in the AA ′ cross section of FIG. 2, the light energy reaching each part when the light energy of the light source is 1. Shown according to size.

In the simulation result shown in FIG. 11, that is, the simulation result of the liquid crystal panel 100 according to the present technology, the light energy in the vicinity of the semiconductor layer 2 is about 5.00 × 10 ⁻⁴ to 1.39 × 10 ⁻⁴ . On the other hand, in the simulation result shown in FIG. 12, that is, the simulation result of the liquid crystal panel 100a according to the reference example, the light energy in the vicinity of the semiconductor layer 2 is about 6.46 × 10 ⁻³ to 1.80 × 10 ⁻³ . Thus, it is shown that the liquid energy of the liquid crystal panel 100 according to the present technology is about one-tenth of the light energy in the vicinity of the semiconductor layer 2 as compared with the conventional liquid crystal panel 100a.

  From the above, it is possible to prevent stray light from entering the vicinity of the semiconductor layer 2, that is, the channel region 4 and the LDD regions 3, 5 by the structure in which the auxiliary capacitor 33 is provided as in the liquid crystal panel 100 according to the present technology. is there. By using such a TFT 32 having a small light leakage current as a switching element of a pixel electrode, a liquid crystal panel having high display quality and suitable for use as a light valve of a liquid crystal display device can be provided.

[Leak current measurement results]
Subsequently, a measurement result of leakage current in the liquid crystal panel 100 of the present technology will be described.

  FIG. 13 is a diagram illustrating a measurement result of leakage current in the liquid crystal panel according to the present technology. Here, on the right side and the left side of FIG. 13, the measurement results of the leakage current when the auxiliary capacitor 33 is arranged above the LDD region 3 and when the auxiliary capacitor 33 is not arranged are shown. According to the measurement results shown in the figure, it can be seen that the leakage current increases when the wiring pattern is provided and a voltage lower than the drain voltage is applied to the pattern.

  According to the studies so far, this phenomenon occurs when the voltage applied to the wiring interferes with the depletion region formed in the off-state LDD region and promotes electric field concentration in the depletion region. Conceivable.

  Here, the drain side LDD portion in the off state is in an extremely depleted state, and the potential is likely to fluctuate due to the influence of the peripheral electric field. Therefore, when the wiring potential is increased, the potential at the LDD site is lowered and the electric field concentration at the drain end is reduced. On the other hand, when the wiring potential is lowered, the potential at the LDD site is increased and the electric field concentration at the drain end is increased. Become.

  Therefore, in order to avoid such a phenomenon, it is desirable that a pattern having a voltage lower than the drain voltage applied to the drain does not exist above the LDD. In addition, it has been found that the carriers generated at the output side LDD part greatly contribute to the light leakage current, and it is important to surround the output side LDD part three-dimensionally with a light shielding film in order to suppress the light leakage current. It becomes.

  Also from the above consideration, the configuration as in the embodiment shown in FIG. 5 reduces the influence from the voltage applied to the wiring pattern as shown in the measurement result shown in FIG. It is proved that the leakage current can be reduced more effectively.

  The leak current is measured by so-called reverse current measurement. That is, the leakage current is measured in an n-type transistor used for pixel switching by applying a voltage between the source and drain and applying a negative bias to the gate in a pixel transistor in a pixel potential holding state. This is done by measuring the current.

[Liquid crystal panel manufacturing method]
14 to 16 are diagrams illustrating an example of a method for manufacturing a liquid crystal panel according to the present technology. Here, a manufacturing method for manufacturing each element on the substrate 31 in the liquid crystal panel 100 according to the present technology will be described. A description of parts that are the same as the conventional ones is omitted.

  First, as shown in FIG. 14A, a wiring pattern 1 made of a silicide film such as tungsten silicide (WSi) or a metal film is formed on a substrate 31 which is a transparent insulating substrate such as synthetic quartz, for example, to a thickness of 200 nm. Form with. The wiring pattern 1 has a function as a scanning line. The wiring pattern 1 also has a function as a light shielding film.

Next, as shown in FIG. 14B, an interlayer insulating film 11 made of, for example, a silicon oxide (SiO ₂ ) film is formed on the entire surface of the substrate 31 by the CVD method or the like on the wiring pattern 1. The interlayer insulating film 11 is desirably flattened by CMP after film formation. By the planarization process, it is possible to avoid problems such as an etching residue due to a step of the lower layer when forming each upper layer in the subsequent processes.

  Thereafter, as shown in FIG. 14C, the semiconductor layer 2 made of polycrystalline silicon, which becomes the active layer of the pixel transistor and the peripheral transistor, is formed on the interlayer insulating film 11 by the CVD method. The film thickness of the semiconductor layer 2 is desirably adjusted between 20 nm and 80 nm.

  Thereafter, as shown in FIG. 14D, the semiconductor layer 2 is patterned into the shape of the element region of each transistor by photolithography and dry etching. Note that impurities are introduced into the semiconductor layer 2 by an ion implantation method, and the channel region 4, the S / D regions 3 a and 5 a, and the LDD regions 3 and 5 are appropriately formed.

Thereafter, as shown in FIG. 14E, a gate insulating film 12 made of SiO ₂ or the like is formed on the semiconductor layer 2 by a CVD method. The film thickness of the gate insulating film 12 is about 80 nm.

  Thereafter, as shown in FIG. 15F, in the interlayer insulating film 11 and the gate insulating film 12, a connection hole 6 for interlayer connection is formed by a dry etching method.

  Thereafter, as shown in FIG. 15G, the gate electrode 7 is disposed via the gate insulating film 12, and the basic structure of the TFT 32 and the peripheral transistor is formed. The gate electrode 7 is connected to the wiring pattern 1 through the connection hole 6 on both sides of the semiconductor layer 2 with the channel region 4 and the LDD region 5 on the output side interposed therebetween. The gate electrode 7 is made of a silicide compound such as polycrystalline silicon or tungsten silicide (WSi).

  Thereafter, as shown in FIG. 15H, an interlayer insulating film 13 made of SiO 2 or the like is formed on the gate electrode 7 and the gate insulating film 12 by the CVD method. The film thickness of the interlayer insulating film 13 is, for example, 300 nm. From the viewpoint of light shielding properties, the thickness of the interlayer insulating film 13 is preferably 500 nm or less. Thereafter, connection holes 8 (see FIG. 2 and the like) for interlayer connection are formed in the interlayer insulating film 13 by dry etching.

  Thereafter, as shown in FIG. 15I, the semiconductor layer 16, the dielectric film 17, and the semiconductor layer 18 are formed in this order on the interlayer insulating film 13 by the CVD method. The semiconductor layers 16 and 18 are made of polysilicon or a silicide compound such as tungsten silicide (WSi). On the other hand, the dielectric film layer 17 is made of an insulating film having a dielectric constant higher than that of the silicon oxide film, such as a silicon nitride film.

  Thereafter, as shown in FIG. 16J, the semiconductor layer 16, the dielectric film 17, and the semiconductor layer 18 are patterned into the shape of the element region of the auxiliary capacitor 33 by photolithography and dry etching.

  Thereafter, as shown in FIG. 16K, a connection hole 39 is formed in a part of the semiconductor layer 16 and the dielectric film layer 17 by photolithography and dry etching.

  Thereafter, as shown in FIG. 16L, an interlayer insulating film 14 is formed by a CVD method. The film thickness of the interlayer insulating film 14 is, for example, 300 nm. Thereafter, connection holes 40 and 41 are formed in the interlayer insulating film 14 and connected to the pixel potential wiring 34 and the fixed potential wiring 36 (see FIG. 4), which are upper layer wirings, through the formed connection holes 40 and 41, respectively. . Thereafter, wiring film deposition / wiring film patterning, interlayer insulating film deposition / connection hole formation are repeated as appropriate in this order to form the final shape of the TFT substrate 101 as shown in FIG.

[Configuration of liquid crystal display device]
FIG. 17 is a diagram illustrating a configuration example of a liquid crystal display device according to the present technology. A configuration of a liquid crystal projector device 110 as an example of a liquid crystal display device according to the present technology will be described with reference to FIG.

  The liquid crystal projector 110 includes a light source 111, a multi-lens array 112, a PbS array 113, a focus lens 114, a mirror 115, dichroic mirrors 116 and 117, liquid crystal panels 118a to 118c corresponding to the liquid crystal panel 100, a dichroic prism 119, and A projection lens 120 is provided.

  The light source 111 emits the light emitted by the light emitting unit 111a to the multi-lens array 112 by the reflector 111b. The multi-lens array 112 has a structure in which a plurality of lens elements are provided in an array, and condenses light emitted from the light source 111. The PbS array 113 polarizes the light collected by the multi-lens array 112 into light having a predetermined polarization direction, for example, a P-polarized wave. The focus lens 114 collects the light converted into light having a predetermined polarization direction by the PbS array 113.

  The dichroic mirror 116 transmits red light R out of light incident through the focus lens 114 and the mirror 115 and reflects green light G and blue light B. The red light R transmitted by the dichroic mirror 116 is guided to the liquid crystal panel 118a through the mirror 115.

  The dichroic mirror 117 transmits the blue light B out of the light reflected by the dichroic mirror 116 and reflects the green light G. The green light G reflected by the dichroic mirror 117 is guided to the liquid crystal panel 118b. On the other hand, the blue light B transmitted by the dichroic mirror 117 is guided to the liquid crystal panel 118c through the mirror 115.

  Each of the liquid crystal panels 118a to 118c optically modulates each incident color light, and enters each light color modulated into the dichroic prism 119. The dichroic prism 119 synthesizes each color light that is incident after being light-modulated into one optical axis. Each synthesized color light is projected onto a screen or the like via the projection lens 120.

  As described above, the liquid crystal projector device 110 according to the present technology displays all colors by combining the three liquid crystal panels 118a to 118c corresponding to the three primary colors of red, green, and blue. This is a projector device having a structure called a three-plate type.

  As described above, in the present embodiment, the liquid crystal display device is described as an example of the liquid crystal display device. However, as long as the liquid crystal display device is configured to include a liquid crystal panel, other devices (television devices, desktop personal computers) Needless to say, the present invention can be applied to a monitor device, a notebook personal computer, an imaging device such as a video camera or a digital still camera having a liquid crystal display device, a PDA, a mobile phone), and a liquid crystal configured with a liquid crystal panel. It can be widely used in various electronic devices having a display device.

In addition, this technique can take the following structures.
(1) A TFT substrate having a transistor formed thereon, a counter substrate facing the TFT substrate, and a liquid crystal layer sandwiched between the TFT substrate and the counter substrate, the TFT substrate being connected to the transistor A wiring pattern as a scanning line, a semiconductor layer provided on a first interlayer insulating film covering the wiring pattern, and a vertical direction of the scanning line on the semiconductor layer via a gate insulating film And a gate electrode provided so as to cross a certain direction and a second interlayer insulating film that covers the channel region of the transistor and the LDD region on the output side, and is stacked on the output side of the transistor. And a storage capacitor connected to the transistor through a connection hole formed on an axis.
(2) The liquid crystal panel according to (1), wherein a light-shielding film is formed on at least one electrode of the auxiliary capacitor.
(3) The liquid crystal panel according to (1) or (2), wherein a light-shielding film is formed on at least a part of the gate electrode.
(4) The liquid crystal panel according to any one of (1) to (3), wherein the auxiliary capacitor is formed so as not to be above an LDD region on an input side of the transistor.
(5) The liquid crystal panel according to any one of (1) to (4), wherein the first interlayer insulating film is planarized by a CMP process.
(6) A method of manufacturing a liquid crystal panel, comprising: a TFT substrate on which a transistor is formed; a counter substrate facing the TFT substrate; and a liquid crystal layer sandwiched between the TFT substrate and the counter substrate. Forming a wiring pattern as a scanning line on a supporting substrate of the TFT substrate; forming a semiconductor layer on a first interlayer insulating film covering the wiring pattern; and forming a gate insulating film on the semiconductor layer A step of providing a gate electrode across a direction perpendicular to the direction in which the scanning line extends through the second interlayer insulating film covering the channel region of the transistor and the LDD region on the output side, Providing a storage capacitor connected to the transistor through a connection hole formed on the long axis on the output side of the transistor.
(7) A TFT substrate on which a transistor is formed, a counter substrate facing the TFT substrate, and a liquid crystal layer sandwiched between the TFT substrate and the counter substrate, the TFT substrate being connected to the transistor A wiring pattern as a scanning line, a semiconductor layer provided on a first interlayer insulating film covering the wiring pattern, and a vertical direction of the scanning line on the semiconductor layer via a gate insulating film And a gate electrode provided so as to cross a certain direction and a second interlayer insulating film that covers the channel region of the transistor and the LDD region on the output side, and is stacked on the output side of the transistor. And a storage capacitor connected to the transistor through a connection hole formed on an axis.

1 wiring pattern 2 semiconductor layer 3 input side LDD region 4 channel region 5 output side LDD region 7 gate electrode 8 connection hole 11 interlayer insulating film (first interlayer insulating film)
12 Gate insulating film 13 Interlayer insulating film (second interlayer insulating film)
16 Semiconductor layer 17 Dielectric film layer 18 Semiconductor layer 31 Support substrate 32 Thin film transistor (TFT)
33 Auxiliary capacity 100 Liquid crystal panel 101 TFT substrate 110 Liquid crystal projector device (liquid crystal display device)

Claims (7)

A TFT substrate on which a transistor is formed;
A counter substrate facing the TFT substrate;
A liquid crystal layer sandwiched between the TFT substrate and the counter substrate,
The TFT substrate is
A wiring pattern as a scanning line connected to the transistor;
A semiconductor layer provided on a first interlayer insulating film covering the wiring pattern;
A gate electrode provided on the semiconductor layer so as to cross a direction perpendicular to an extending direction of the scanning line via a gate insulating film;
Provided by laminating on the second interlayer insulating film covering the channel region of the transistor and the LDD region on the output side, and connected to the transistor through a connection hole formed on the long axis on the output side of the transistor With auxiliary capacity,
A liquid crystal panel.   The liquid crystal panel according to claim 1, wherein a light-shielding film is formed on at least one electrode of the auxiliary capacitor.   The liquid crystal panel according to claim 1, wherein a light-shielding film is formed on at least a part of the gate electrode.   The liquid crystal panel according to claim 1, wherein the auxiliary capacitor is formed so as to avoid the upper side of the LDD region on the input side of the transistor.   The liquid crystal panel according to claim 1, wherein the first interlayer insulating film is planarized by a CMP process. A TFT substrate on which a transistor is formed;
A counter substrate facing the TFT substrate;
A liquid crystal panel comprising a liquid crystal layer sandwiched between the TFT substrate and the counter substrate,
Forming a wiring pattern as a scanning line on the support substrate of the TFT substrate;
Forming a semiconductor layer on a first interlayer insulating film covering the wiring pattern;
A step of providing a gate electrode on the semiconductor layer so as to cross a direction perpendicular to the extending direction of the scanning line via a gate insulating film;
An auxiliary capacitor connected to the transistor via a connection hole formed on the long axis on the output side of the transistor is formed on the second interlayer insulating film covering the channel region of the transistor and the LDD region on the output side. Providing, and
A method for producing a liquid crystal panel, comprising: A TFT substrate on which a transistor is formed;
A counter substrate facing the TFT substrate;
A liquid crystal layer sandwiched between the TFT substrate and the counter substrate,
The TFT substrate is
A wiring pattern as a scanning line connected to the transistor;
A semiconductor layer provided on a first interlayer insulating film covering the wiring pattern;
A gate electrode provided on the semiconductor layer so as to cross a direction perpendicular to an extending direction of the scanning line via a gate insulating film;
Provided by laminating on the second interlayer insulating film covering the channel region of the transistor and the LDD region on the output side, and connected to the transistor through a connection hole formed on the long axis on the output side of the transistor With auxiliary capacity,
A liquid crystal display device.