CN109801847B - SOI device structure and preparation method thereof - Google Patents
SOI device structure and preparation method thereof Download PDFInfo
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Abstract
The invention relates to the technical field of semiconductors, in particular to an SOI device structure and a preparation method thereof, wherein the SOI device structure comprises the following components: a first insulating layer; a device layer located above the first insulating layer, the device layer being used for preparing a plurality of target MOS devices; a first backing bottom layer is arranged below the first insulating layer and right opposite to the source electrode of each target MOS device, and a second backing bottom layer is arranged right opposite to the drain electrode of each target MOS device; a second insulating layer on the surface of each first backing bottom layer, the surface of each second backing bottom layer and the area between the two; a first contact hole communicated with the second insulating layer is arranged below each first back lining bottom layer, and a second contact hole communicated with the second insulating layer is arranged under each second back lining bottom layer; each first contact hole and each second contact hole are filled with conductive materials; and a conductive structure of each contact hole is formed on the surface of the second insulating layer, so that the design and manufacturing cost of the chip is reduced, the process is simplified, and the anti-irradiation performance of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an SOI (silicon on insulator) device structure and a preparation method thereof.
Background
Silicon On Insulator (SOI) refers to a semiconductor device fabrication method in which a semiconductor device is formed in a semiconductor thin film (device layer) over an Insulator (insulating layer), and the material under the insulating layer is referred to as a backing underlayer. Advantages of devices fabricated by SOI processes compared to bulk silicon processes: the subthreshold slope is steeper, the transconductance and the current driving capability are higher, the irradiation resistance is stronger, the latch-up effect is avoided, the source/drain parasitic capacitance is smaller, and the like, so that the device manufactured by the SOI process is also called the microelectronic technology of the twenty-first century.
In order to further improve the radiation resistance of the SOI device, the following method is often adopted:
the radiation resistance is improved by adopting a local oxygen injection method.
However, the manufacturing difficulty of the process is high, the production cost is high, all control electric signals are led out from the upper part of the chip, the wiring is difficult, and the occupied area of the chip is large.
Therefore, how to improve the radiation-proof performance of the SOI device through a preparation process with convenient operation is a technical problem to be solved urgently at present.
Disclosure of Invention
In view of the above, the present invention has been made to provide a photodetector and a method of fabricating the same that overcome or at least partially solve the above problems.
In one aspect, an embodiment of the present invention provides a method for manufacturing an SOI device structure, where the SOI device structure includes, from bottom to top, a back substrate layer, a first insulating layer, and a device layer, and the method includes:
etching the backing bottom layer, reserving a first backing bottom layer region, opposite to the source electrode of each target MOS device of the device layer, in the backing bottom layer and a second backing bottom layer region, opposite to the drain electrode of each target MOS device, in the backing bottom layer, and etching away other regions except the first backing bottom layer region and the second backing bottom layer region in the backing bottom layer to form an isolation region;
forming a second insulating layer on the first backing underlying region and the second backing underlying region so as to fill the isolation region;
and forming a first contact hole communicated with the first backing bottom layer region from the surface of the second insulating layer and a second contact hole communicated with the second backing bottom layer region from the surface of the second insulating layer, filling each first contact hole and each second contact hole with a conductive material, and forming a conductive structure of each contact hole on the surface of the second insulating layer.
Preferably, the first backing underlying region completely covers a region of the target MOS device in a direction opposite to the source, and the second backing underlying region completely covers a region of the target MOS device in a direction opposite to the drain.
Preferably, before etching the backing underlayer, the method further comprises:
thinning the backing bottom layer.
Preferably, before etching the backing underlayer, the method further comprises:
preparing a target MOS device on the device layer; or
Forming a first contact hole communicating each of the first backing underlying regions from the surface of the second insulating layer and forming a second contact hole communicating each of the second backing underlying regions from the surface of the second insulating layer, filling each of the first contact holes and each of the second contact holes with a conductive material, and after forming a conductive structure of each contact hole on the surface of the second insulating layer, further comprising:
and preparing a target MOS device on the device layer.
Preferably, the first insulating layer and the second insulating layer are made of any one of the following insulating materials:
silicon dioxide, silicon nitride, glass.
Preferably, the device layer and the first and second backing underlying regions are made of any one of the following semiconductor materials:
silicon, gallium arsenide, gallium nitride, silicon carbide.
On the other hand, an embodiment of the present invention further provides an SOI device structure, including:
a first insulating layer;
a device layer located above the first insulating layer, the device layer being used for preparing a plurality of target MOS devices;
a first backing substrate is provided below the first insulating layer for the source electrode of each target MOS device, and a second backing substrate is provided below the first insulating layer for the drain electrode of each target MOS device;
a second insulating layer is isolated on the surface of each first backing bottom layer, the surface of each second backing bottom layer and the adjacent first backing bottom layer, the adjacent second backing bottom layer and the adjacent first backing bottom layer and the adjacent second backing bottom layer;
a first contact hole communicated with the second insulating layer is arranged below each first back lining bottom layer, and a second contact hole communicated with the second insulating layer is arranged under each second back lining bottom layer;
each first contact hole and each second contact hole are filled with conductive materials;
and forming a conductive structure of each contact hole on the surface of the second insulating layer.
Preferably, the first backing bottom layer completely covers the region of the target MOS device in the direction facing the source electrode, and the second backing bottom layer completely covers the region of the target MOS device in the direction facing the drain electrode.
Preferably, the first insulating layer and the second insulating layer are made of any one of the following insulating materials:
silicon dioxide, silicon nitride, glass.
Preferably, the first backing bottom layer, the second backing bottom layer and the device layer are made of any one of the following semiconductor materials:
silicon, gallium arsenide, gallium nitride, silicon carbide.
One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:
the invention provides a preparation method of an SOI device structure, the SOI device structure comprises a back substrate layer, a first insulating layer and a device layer from bottom to top, and the preparation method comprises the following steps: etching the backing bottom layer, reserving a first backing bottom layer region which is over against a source electrode of each target MOS device of the device layer and a second backing bottom layer region which is over against a drain electrode of each target MOS device in the backing bottom layer, and etching away other regions except the first backing bottom layer region and the second backing bottom layer region in the backing bottom layer to form an isolation region; forming a second insulating layer on the first backing underlying region and the second backing underlying region so as to fill the isolation region; forming a first contact hole communicated with the first backing bottom layer area from the surface of the second insulating layer and a second contact hole communicated with the second backing bottom layer area from the surface of the second insulating layer, filling each first contact hole and each second contact hole with a conductive material, and forming a conductive structure of each contact hole on the surface of the second insulating layer, wherein the structure of the original device is completely reserved in the preparation process, only the first backing bottom layer area in the direction opposite to the source electrode and the second backing bottom layer area in the direction opposite to the drain electrode of each device of the device structure are respectively isolated by an isolation etching method on the backing bottom layer, so as to form an independent conductive structure connecting the bottom of the first backing bottom layer area and the bottom of the independent second backing bottom layer area with the outside, leading out a lead wire from the back of the device, and regulating and controlling the voltage of the backing bottom layer by two ports (the conductive structure at the bottom of the first backing bottom layer and the conductive structure at the bottom of the second backing bottom layer, the method is more flexible, greatly reduces the design and manufacturing cost of the chip, simplifies the process, and can also improve the radiation resistance of the device.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a flow chart illustrating the steps of a method for fabricating an SOI device structure in an embodiment of the present invention;
FIGS. 2 a-2 g are schematic structural diagrams corresponding to various steps in a method for fabricating an SOI device structure according to an embodiment of the present invention;
fig. 3 shows a schematic structural diagram of an SOI device structure in an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Example one
A first embodiment of the present invention provides a method for manufacturing an SOI device structure, where the SOI device structure includes, from bottom to top, a back substrate layer, a first insulating layer, and a device layer, as shown in fig. 1, the method specifically includes: s11, etching the backing bottom layer, reserving a first backing bottom layer area, opposite to the source electrode of each target MOS device of the device layer, in the backing bottom layer and a second backing bottom layer area, opposite to the drain electrode of each target MOS device, in the device layer, and etching away other areas except the first backing bottom layer area and the second backing bottom layer area in the backing bottom layer to form an isolation area; s12, forming a second insulating layer on the first and second backing underlying regions so as to fill the isolation region; and S13, forming a first contact hole communicated with each first backing bottom layer region from the surface of the second insulating layer and a second contact hole communicated with each second backing bottom layer region from the surface of the second insulating layer, filling each first contact hole and each second contact hole with a conductive material, and forming a conductive structure of each contact hole on the surface of the second insulating layer.
Some MOS devices on the device layer need to adjust the voltage of the backing substrate layer so as to realize the radiation resistance, and some MOS devices do not need to be protected by the radiation resistance, and the MOS devices needing to be protected by the radiation resistance are defined as target MOS devices. The source and drain of the target MOS device are located on both sides of a channel region of the MOS device, and a gate is located above the channel region.
The invention also comprises a process for preparing the target MOS device on the device layer, which can be specifically carried out before etching the backing bottom layer, or can be carried out after forming a first contact hole communicated with the first backing bottom layer region from the surface of the second insulating layer and a second contact hole communicated with the second backing bottom layer region from the surface of the second insulating layer, filling each first contact hole and each second contact hole with a conductive material, and forming a conductive structure of each contact hole on the surface of the second insulating layer. Therefore, the preparation method of the whole SOI device structure does not influence the preparation of the active region of the target MOS device on the device layer, and the process is more flexible because the structure of the prepared active region of the device or the structure of the unfinished active region of the device can be prepared by the preparation method in the invention.
In a specific embodiment, taking the preparation of the active region of the target MOS device on the device layer as an example, before S11, as shown in fig. 2a, the prepared device structure is a structure in which the active region of the target MOS device is prepared, and specifically includes: a device layer, a first insulating layer 106 and a backing bottom layer 107 from top to bottom, wherein active regions on the device layer are prepared, the device layer specifically includes a plurality of groups of MOS device active regions, taking two groups of target MOS transistors as an example, the target MOS transistor 1 includes an active region 100-1, 102-1 and a gate 101-1, a channel region 111-1 between the active regions 100-1, 102-1 and below the gate 101-1; the set of target MOS transistors 2 adjacent to the target MOS transistor 1 also includes active regions 100-2, 102-2 and a gate 101-2, a channel region 111-2 between the active regions 100-2, 102-2 and below the gate 101-2. Between the two sets of target MOS transistors there is a field region 104, i.e. an insulating material region. Of course, there is also a field 103 between the target MOS transistor 1 and the other target MOS transistor i for isolation from the other target MOS transistor i, and a field 105 between the target MOS transistor 2 and the other target MOS transistor j for isolation from the other target MOS transistor j.
The device layer has a thickness of 80nm-500 μm, the first insulating layer has a thickness of 100nm-100 μm, and the backing substrate has an initial thickness of 100 μm-2000 μm
On the basis of the prepared device structure, before S11, the method further includes: this backing base layer 107 was thinned to obtain a structure as shown in fig. 2 b. The thinning is to improve the heat dissipation effect of the wafer.
The specific thinning method specifically adopts at least one of the following methods:
smart Cut technology (Smart Cut), and mechanical grinding and polishing technology.
In the process of thinning the backing bottom layer 107, the backing bottom layer of the wafer is upwards operated, the backing bottom layer 107 is thinned and polished to 50 nm-200 μm, and the specific thickness after thinning depends on the maximum depth of deep groove isolation which can be realized in the process.
After the backing bottom layer 107 is thinned, S11 is executed, the backing bottom layer 107 is etched, specifically, as shown in fig. 2c, a first backing bottom layer region facing the source of each target MOS device of the device layer and a second backing bottom layer region facing the drain of each target MOS device in the backing bottom layer 107 are reserved, specifically, as shown in the figure, a first backing bottom layer region facing the source 100-1 of the target MOS transistor 1, i.e. 109-1 region in the figure, and a second backing bottom layer region facing the drain 102-1 of the target MOS transistor 1, i.e. 119-1 region in the figure, and a first backing bottom layer region facing the source 100-2 of the target MOS transistor 2, i.e. 109-2 region in the figure, and a second backing bottom layer region facing the drain 102-2 of the target MOS transistor 2, region 119-2 in the illustration; and etching away other areas of the backing bottom layer except the first backing bottom layer area and the second backing bottom layer area to form the isolation area. In particular a first area between adjacent first and second backing underlying areas, a second area between adjacent first backing underlying areas, a third area between adjacent second backing underlying areas. Shown in the figure are specifically the regions of the backing underlying in the direction opposite to the channel regions 111-1 of field region 103 and target MOS transistor 1, field regions 104 and 105, and channel region 111-2 of MOS transistor 2, respectively.
After etching, the first backing bottom layer region completely covers the region of the target MOS device in the direction opposite to the source electrode, and the second backing bottom layer region completely covers the region of the target MOS device in the direction opposite to the drain electrode.
In the embodiment of the present invention, the first backing underlying region and the second backing underlying region are appropriately widened, so as to avoid that the first contact hole and the second contact hole cannot be prepared due to insufficient widths of the first backing underlying region and the second backing underlying region, and further, to ensure that the first contact hole can be prepared on the widened first backing underlying region and the second contact hole can be prepared on the second backing underlying region.
The etching method adopted is specifically any one of the following etching methods:
wet etching, plasma etching, reactive ion etching, electron cyclotron resonance etching, and inductively coupled plasma etching. Of course, these etching methods are not limited.
In a specific etching process, after depositing a photoresist, exposing and developing, reserving a first backing bottom layer region 109-1 in the backing bottom layer 107 in the direction opposite to the source of the target MOS transistor 1 of the device layer, a second backing bottom layer region 119-1 in the direction opposite to the drain of the target MOS transistor 1, a first backing bottom layer region 109-2 in the direction opposite to the source of the target MOS transistor 2, and a second backing bottom layer region 119-2 in the direction opposite to the drain of the target MOS transistor 2, so as to expose other regions of the backing bottom layer 107 except the first backing bottom layer regions 109-1 and 109-2 and the second backing bottom layer regions 119-1 and 119-2, thereby etching the exposed regions, and etching to the first insulating layer 106, so that the backing bottom layer 107 forms a plurality of independent first backing bottom layer regions and second backing bottom layer regions, specifically, 109-1 and 109-2 regions and 119-1 and 119-2 regions.
After etching, a first backing bottom layer region right opposite to the source electrode of each target MOS device and a second backing bottom layer region right opposite to the drain electrode of each target MOS device are reserved, so that the performance is effectively adjusted, the heat dissipation of a channel region is promoted, the parasitic capacitance of the source electrode and the drain electrode of each target MOS device can be reduced, and the response speed of each target MOS device is improved.
After etching the backing underlying layer, S12 is performed, as shown in fig. 2d, a second insulating layer 107-1 is formed on the first backing underlying regions 109-1, 109-2 and the second backing underlying regions 119-1, 119-2 so as to fill the isolation regions.
A deposition method may be adopted, which is to deposit the second insulating layer 107-1 on the surface of the first backing underlying region and the surface of the second backing underlying region by using any one of the following deposition methods:
low Pressure Chemical Vapor Deposition (LPCVD), plasma chemical vapor deposition (PECVD), and Atmospheric Pressure Chemical Vapor Deposition (APCVD), although the methods are not limited thereto.
The process of forming the second insulating layer 107-1 further includes planarizing the second insulating layer 107-1, which may be reflow, spin coating, or reactive etching planarization or chemical mechanical planarization, so that all dielectric electrical isolation is formed between the remaining regions of the underlying first backing, but is not limited to the above planarization methods.
Finally, S13 is performed, as shown in fig. 2e, 2f, and 2g, to form first contact holes communicating with the first backing underlying regions 109-1 and 109-2 from the surface of the second insulating layer 107-1, to form second contact holes communicating with the second backing underlying regions 119-1 and 119-2 from the surface of the second insulating layer 107-1, to fill each of the first contact holes and each of the second contact holes with a conductive material, and to form a conductive structure of each of the contact holes on the surface of the second insulating layer 107-1.
And filling conductive materials in the first contact hole and the second contact hole by adopting a deposition method, specifically, regions 110-1, 110-2, 111-1 and 111-2 shown in fig. 2f and fig. 2g, forming a conductive structure of each contact hole on the surface of the second insulating layer 107-1, and realizing adjustment and control of the voltage of the first backing bottom layer region and the second backing bottom layer region through the conductive structures.
Specifically, first contact holes are etched from the second insulating layer 107-1 to the positions right under the first backing underlying regions 109-1, 109-2, respectively, to deposit conductive materials 110-1, 111-1, 110-2, 111-2 (such as tungsten), and if the doping concentrations of 109-1 and 119-1, 109-2, and 119-2 are low and ohmic contact cannot be formed with the conductive materials 110-1, 111-1, 110-2, 111-2, then the first backing underlying regions 109-1, 109-2 and the second backing underlying regions 119-1, 119-2 need to be heavily doped through the contact holes before depositing the conductive materials 110-1, 111-1, 110-2, 111-2, so as to realize the first backing underlying regions and the conductive materials, ohmic contacts to the second back substrate and the conductive material.
Etching second contact holes from the second insulating layer 107-1 to the positions right under the second backing underlying regions 119-1 and 119-2, respectively, then, photoetching the first contact holes and the second contact holes, depositing conductive material on the first contact holes, depositing conductive material on the second contact holes, specifically forming regions 110-1, 110-2, 111-1 and 111-2 as shown in FIG. 2g, depositing passivation layer and PAD window, forming ohmic contact of the first backing underlying region and the conductive material, and ohmic contact of the second backing underlying region and the conductive material, and forming conductive structures of each contact hole on the surface of the second insulating layer 107-1, specifically, a conductive layer, which is correspondingly connected with the conductive material 110-1, and a conductive layer which is correspondingly connected with the conductive material 110-2, the third conducting layer is correspondingly connected with the conducting material 111-1, the fourth conducting layer is correspondingly connected with the conducting material 111-2, the first backing bottom layer area and the second backing bottom layer area can be respectively connected with electric signals outside the chip through the conducting structure, and the voltage of the first backing bottom layer area and the voltage of the second backing bottom layer area are adjusted and controlled through the conducting structure. Of course, each conductive structure can be connected with each other, and simultaneously, after depositing a passivation layer material, the electrical parameters of the two can be led out to the outside of the chip to be electrically connected through the PAD groove of the passivation layer.
Specifically, the conductive material and the conductive structure can be any one of the following materials:
metals, alloys, inorganic non-metals.
The voltage value of each first backing bottom layer region and the second backing bottom layer region are adjusted through the conductive structure, so that the threshold voltage of the MOS device above the conductive structure is controlled, parameters of the MOS device are optimized and adjusted, adverse effects of irradiation on the SOI semiconductor are counteracted, and the irradiation resistance of the device is improved.
And the second insulating layers are adopted between the adjacent first backing bottom layer regions and the second backing bottom layer regions, between the adjacent first backing bottom layer regions and between the adjacent second backing bottom layer regions for full-dielectric isolation, so that the breakdown voltage of the full-dielectric isolation is higher. Therefore, the back substrate voltage value range of the SOI device structure is larger, the regulation and control force on the device performance is larger, and the irradiation resistance of the device is stronger.
Moreover, signal lines are led out from the first backing bottom layer just below the source electrode of each MOS device through the conducting structure, and signal lines are led out from the second backing bottom layer just below the drain electrode of each MOS device through the conducting structure, and the mode that the signal lines are led out from the chip top through wires is different from the mode that other device chips are led out through wires, so that the wire pressure above the chip is effectively reduced, the area of the chip is reduced, and the cost of the chip is reduced.
In the embodiment of the present invention, the first insulating layer and the second insulating layer are made of any one of the following insulating materials:
silicon dioxide, silicon nitride, glass. Of course, these materials are not limited.
The device layer, the first backing bottom layer region and the second backing bottom layer region are made of any one of the following semiconductor materials:
silicon, gallium arsenide, gallium nitride, silicon carbide. Of course, these materials are not limited.
And the backing bottom layer material is a highly doped semiconductor material, so that the first backing bottom layer region material and the second backing bottom layer region material are highly doped semiconductor materials, and the doping concentration of the materials can enable the backing bottom layer to form ohmic contact with the conductive material at the contact hole.
If the backing substrate material is a low-doped semiconductor material, photolithography and diffusion may be used to form local high-doped regions, specifically, regions 108-1, 118-1, 108-2 and 118-2 shown in fig. 2f, at positions where contact holes are respectively formed in the first backing substrate region and the second backing substrate region, so as to achieve ohmic contact between the first backing substrate region and the conductive material, and ohmic contact between the second backing substrate region and the conductive material.
Example two
In a first embodiment of the present invention, there is provided an SOI device structure, as shown in fig. 3, comprising:
a first insulating layer 301;
a device layer located above the first insulating layer 301, the device layer being used for preparing a plurality of target MOS devices;
under the first insulating layer 301 there is a first backing floor 304 for the source 302 of each target MOS device, and under the first insulating layer 301 there is a second backing floor 305 for the drain 303 of each target MOS device;
a second insulating layer 306 is isolated on the surface of each first backing bottom layer 304, the surface of each second backing bottom layer 305 and between the adjacent first backing bottom layers 304, the adjacent second backing bottom layers 305 and between the adjacent first backing bottom layers 304 and second backing bottom layers 305;
a first contact hole communicating with the second insulating layer 306 is formed under each of the first backing base layers 304, and a second contact hole communicating with the second insulating layer 306 is formed under each of the second backing base layers 305;
each of the first contact holes and each of the second contact holes are filled with a conductive material 307;
and forming a conductive structure 308 of each contact hole on the surface of the second insulating layer.
In a specific embodiment, the first backing substrate layer completely covers a region in a source-facing direction of the target MOS device, and the second backing substrate layer completely covers a region in a drain-facing direction of the target MOS device.
In a specific embodiment, the first insulating layer 301 and the second insulating layer 305 both use any one of the following insulating materials:
silicon dioxide, silicon nitride, glass.
The first backing underlayer 304 and the device layer are made of any one of the following semiconductor materials:
silicon, gallium arsenide, gallium nitride, silicon carbide.
The materials of the first backing bottom layer and the second backing bottom layer are high-doped semiconductor materials, and the doping concentration of the materials is such that the first backing bottom layer 304 and the conductive material 307 at the first contact hole and the second backing bottom layer and the conductive material at the second contact hole form ohmic contact.
If the backing substrate material is a low-doped semiconductor material, photolithography and diffusion may be used to form local high-doped regions, specifically region 308 shown in fig. 3, at positions where contact holes are formed in the first backing substrate and the second backing substrate, respectively, for realizing ohmic contact between the first backing substrate and the conductive material and ohmic contact between the second backing substrate and the conductive material.
One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:
the invention provides a preparation method of an SOI device structure, the SOI device structure comprises a back substrate layer, a first insulating layer and a device layer from bottom to top, and the preparation method comprises the following steps: etching the backing bottom layer, reserving a first backing bottom layer region which is over against a source electrode of each MOS device of the device layer and a second backing bottom layer region which is over against a drain electrode of each MOS device in the backing bottom layer, and etching off a first region between adjacent first backing bottom layer regions and adjacent second backing bottom layer regions, a second region between adjacent first backing bottom layer regions and a third region between adjacent second backing bottom layer regions in the backing bottom layer under the multiple MOS devices over against to form an isolation region; forming a second insulating layer on the first backing base layer and the second backing base layer so as to fill the isolation region; the preparation process includes forming the first contact holes communicated with the first back lining bottom layers from the surface of the second insulating layer and the second contact holes communicated with the second back lining bottom layers from the surface of the second insulating layer, filling the first contact holes and the second contact holes with conducting material, and forming the conducting structure of each contact hole on the surface of the second insulating layer, wherein the structure of the original device is completely reserved, the first back lining bottom layers in the direction opposite to the source electrode and the second back lining bottom layers in the direction opposite to the drain electrode of each device of the device structure are respectively isolated only on the back lining bottom layers through an isolation etching method, so that the bottom of each first back lining bottom layer and the bottom of each second back lining bottom layer are connected with the conducting structure outside, the conducting wires are led out from the back of the device, the voltage of the back lining is adjusted and controlled through two ports, and the design and the manufacturing cost of the chip are more flexible and greatly reduced, the process is simplified, and the radiation resistance of the device can be improved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A preparation method of an SOI device structure, the SOI device structure comprises a back substrate layer, a first insulating layer and a device layer from bottom to top, and is characterized by comprising the following steps:
etching the backing bottom layer, reserving a first backing bottom layer region, opposite to the source electrode of each target MOS device of the device layer, in the backing bottom layer and a second backing bottom layer region, opposite to the drain electrode of each target MOS device, in the backing bottom layer, and etching away other regions except the first backing bottom layer region and the second backing bottom layer region in the backing bottom layer to form an isolation region;
forming a second insulating layer on the first backing underlying region and the second backing underlying region so as to fill the isolation region;
and forming a first contact hole communicated with the first backing bottom layer region from the surface of the second insulating layer and a second contact hole communicated with the second backing bottom layer region from the surface of the second insulating layer, filling each first contact hole and each second contact hole with a conductive material, and forming a conductive structure of each contact hole on the surface of the second insulating layer.
2. The method of claim 1, wherein the first backing floor region completely covers a source-facing direction region of the target MOS device and the second backing floor region completely covers a drain-facing direction region of the target MOS device.
3. The method of claim 1, further comprising, prior to etching the backing underlayer:
thinning the backing bottom layer.
4. The method of claim 1, further comprising, prior to etching the backing underlayer:
preparing a target MOS device on the device layer; or
Forming a first contact hole communicating each of the first backing underlying regions from the surface of the second insulating layer and forming a second contact hole communicating each of the second backing underlying regions from the surface of the second insulating layer, filling each of the first contact holes and each of the second contact holes with a conductive material, and after forming a conductive structure of each contact hole on the surface of the second insulating layer, further comprising:
and preparing a target MOS device on the device layer.
5. The method of claim 1, wherein the first insulating layer and the second insulating layer are made of any one of the following insulating materials:
silicon dioxide, silicon nitride, glass.
6. The method of claim 1, wherein the device layer and the first and second backing underlying regions each comprise a semiconductor material selected from any one of:
silicon, gallium arsenide, gallium nitride, silicon carbide.
7. An SOI device structure, comprising:
a first insulating layer;
a device layer located above the first insulating layer, the device layer being used for preparing a plurality of target MOS devices;
a first backing substrate is provided below the first insulating layer for the source electrode of each target MOS device, and a second backing substrate is provided below the first insulating layer for the drain electrode of each target MOS device;
a second insulating layer is isolated on the surface of each first backing bottom layer, the surface of each second backing bottom layer and the adjacent first backing bottom layer, the adjacent second backing bottom layer and the adjacent first backing bottom layer and the adjacent second backing bottom layer;
a first contact hole communicated with the second insulating layer is arranged below each first back lining bottom layer, and a second contact hole communicated with the second insulating layer is arranged under each second back lining bottom layer;
each first contact hole and each second contact hole are filled with conductive materials;
and forming a conductive structure of each contact hole on the surface of the second insulating layer.
8. The SOI device structure of claim 7, in which the first backing floor completely covers a source-facing direction region of the target MOS device, and the second backing floor completely covers a drain-facing direction region of the target MOS device.
9. The SOI device structure of claim 7 wherein the first and second insulating layers are made of any one of the following materials:
silicon dioxide, silicon nitride, glass.
10. The SOI device structure of claim 7 wherein the first, second, and device layers are specifically made of any one of the following semiconductor materials:
silicon, gallium arsenide, gallium nitride, silicon carbide.
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| CN102361031A (en) * | 2011-10-19 | 2012-02-22 | 电子科技大学 | Semiconductor device used for SOI (silicon-on-insulator) high-voltage integrated circuit |
| CN102437087A (en) * | 2011-12-14 | 2012-05-02 | 中国科学院微电子研究所 | SOI structure with radiation resistance and reinforcement and manufacturing method thereof |
| CN103022139A (en) * | 2012-12-28 | 2013-04-03 | 上海集成电路研发中心有限公司 | Semiconductor structure with insulating buried layer and manufacturing method thereof |
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| CN102361031A (en) * | 2011-10-19 | 2012-02-22 | 电子科技大学 | Semiconductor device used for SOI (silicon-on-insulator) high-voltage integrated circuit |
| CN102437087A (en) * | 2011-12-14 | 2012-05-02 | 中国科学院微电子研究所 | SOI structure with radiation resistance and reinforcement and manufacturing method thereof |
| CN103022139A (en) * | 2012-12-28 | 2013-04-03 | 上海集成电路研发中心有限公司 | Semiconductor structure with insulating buried layer and manufacturing method thereof |
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