CN109787593B

CN109787593B - Digital pulse width modulation circuit

Info

Publication number: CN109787593B
Application number: CN201811608677.8A
Authority: CN
Inventors: 赵茂; 刘玉敬; 缪瑜; 吴倩雯
Original assignee: Nanjing Ruihe Electronics Co ltd
Current assignee: Nanjing Ruihe Electronics Co ltd
Priority date: 2018-12-27
Filing date: 2018-12-27
Publication date: 2023-04-07
Anticipated expiration: 2038-12-27
Also published as: CN109787593A

Abstract

The invention discloses a digital pulse width modulation circuit, comprising: a Delay Locked Loop (DLL) circuit for generating a plurality of delayed clock signals sequentially delayed by a fixed time according to a clock signal, the clock signal having a first period; a control signal generating circuit for generating a control signal; a main modulation circuit, connected to the DLL circuit and the control signal generation circuit, for generating a Digital Pulse Width Modulated (DPWM) signal according to a plurality of the delayed clock signals and the control signal, and the DPWM signal having a second adjustable period. The invention enables the period of the DPWM signal to be adjustable, thereby improving the adjustment flexibility of the digital pulse width modulation circuit.

Description

Digital pulse width modulation circuit

Technical Field

The present invention relates to a signal generating technology in the field of integrated circuits, and in particular, to a Digital Pulse Width Modulation (DPWM) circuit.

Background

Pulse-Width Modulation (PWM) is widely used in power supply regulation and communication systems. The pulse width modulation technique can be divided into analog pulse width modulation and digital pulse width modulation. The existing DPWM in the form of a counter usually comprises a counter and a comparator, and in order to achieve a higher modulation accuracy, the clock frequency needs to be increased. The delay line DPWM can avoid simply increasing the clock frequency to achieve a higher modulation rate, but still requires more delay units.

The hybrid DPWM combines the design of a counter mode and a Delay line mode, and comprises a group of counting logics and a Delay-locked Loop (DLL), wherein a plurality of Delay units in the DLL divide a clock signal into a group of low-speed Delay clock signals with different phases, and the counting logics can generate a control signal to select the clock signals with different phases according to the requirement of the DPWM. For a low speed clock (i.e., a low frequency clock), since the time interval of the delay can be much smaller than its period, a DPWM signal of higher accuracy can be output without using a high speed clock.

However, in the process of implementing the hybrid DPWM, the inventors found that although the duty ratio of the existing hybrid DPWM is adjusted more accurately, the adjustment target of the existing hybrid DPWM is single and the flexibility is low.

Disclosure of Invention

In view of this, the present invention provides a digital pwm circuit to solve the problems of single adjustment object and low flexibility of the DPWM modulation signal output by the prior art.

The technical scheme adopted by the invention for solving the technical problems is as follows: a digital pulse width modulation circuit comprising:

a delay phase-locked loop circuit for generating a plurality of delayed clock signals sequentially delayed by a fixed time according to a clock signal, the clock signal having a first period;

a control signal generating circuit for generating a control signal;

and the main modulation circuit is connected with the delay phase-locked loop circuit and the control signal generation circuit and is used for generating a digital pulse width modulation signal according to a plurality of delay clock signals and the control signal, and the digital pulse width modulation signal has an adjustable second period.

Optionally, with the first period being T, the delay phase-locked loop circuit generates M delay clock signals with sequential delay time intervals being T according to the clock signals in N periods, that is, M × T = N × T, where M and N are positive integers;

the control signal comprises a period coarse adjustment value, and the main modulation circuit determines the second period according to the M delayed clock signals and the period coarse adjustment value, wherein the period coarse adjustment value is period _ set, and the adjusted second period is period _ set × T.

Optionally, with the first period being T, the delay phase-locked loop circuit generates M delay clock signals with sequential delay time intervals being T according to the clock signals in N periods, that is, M × T = N × T, where M and N are positive integers; the main modulation circuit determines the second period according to the M delayed clock signals, the periodic coarse tuning value and the periodic fine tuning value, wherein the periodic coarse tuning value is period _ set, the periodic fine tuning value is period _ clock, and the adjusted second period is (period _ set + period _ clock × N/M) × T.

Optionally, the control signal further includes a coarse duty ratio adjustment value and a fine duty ratio adjustment value, and the main modulation circuit is further configured to generate the digital pwm signal with an adjustable duty ratio according to the M delayed clock signals, the coarse duty ratio adjustment value, and the fine duty ratio adjustment value, where the coarse duty ratio adjustment value is duty _ set, the fine duty ratio adjustment value is duty _ clock, and the duty ratio of the adjusted digital pwm signal is (duty _ set + duty _ clock × N/M)/(period _ set + period _ clock × N/M).

Optionally, the main modulation circuit comprises a periodic modulation circuit and an SR latch (305), the periodic modulation circuit comprising:

a first multiplexer (301) and a second multiplexer (302) respectively connected to the dll circuit, the first multiplexer (301) selecting a first periodic modulation clock signal clka from the M delayed clock signals output from the dll circuit according to a first phase selection signal, the second multiplexer (302) selecting a second periodic modulation clock signal clkb from the M delayed clock signals according to a second phase selection signal;

a first clock selector (303) connected to the first multiplexer (301) and the second multiplexer (302), for performing a switching selection on the first periodic modulation clock signal clka and the second periodic modulation clock signal clkb to obtain a third periodic modulation clock signal clkp;

a regular counter (304) connected to the first clock selector (303) for counting the third period modulated clock signal clkp and outputting a set signal S to the SR latch (305) when the count reaches the coarse period value period _ set, the set signal S being used for the SR latch (305) to generate the digital pulse width modulated signal.

Optionally, the main modulation circuit further includes a duty cycle modulation circuit, and the duty cycle modulation circuit includes:

a third multiplexer (306) coupled to the delay phase-locked loop circuit for selecting a first duty cycle modulated clock signal clkc from the M delayed clock signals in accordance with a third phase selection signal;

a second clock selector (307) connected to the first clock selector (303) and the third multiplexer (306), for performing switching selection on the third periodic modulation clock signal clkp and the first duty ratio modulation clock signal clkc to obtain a second duty ratio modulation clock signal clkd;

an SR enable counter (308) connected to said regular counter (304), a second clock selector (307) and said SR latch (305) for counting said second duty cycle modulated clock signal clkd and outputting a reset signal R to said SR latch (305) when said count reaches said coarse duty cycle value of duty _ set, said reset signal R being for said SR latch (305) to generate said digital pulse width modulated signal.

Optionally, the control signal generating circuit comprises:

a first accumulator (404) outputting the first phase selection signal psela according to the period tweak value for controlling the first multiplexer (301);

a second accumulator (405) outputting the second phase selection signal pselb according to the period fine-tuning value to control the second multiplexer (302);

a two-way selector (406) which is connected to the first accumulator (404) and the second accumulator (405) and switches between the first phase selection signal psela and the second phase selection signal pselb to output a first period selection signal psel;

a third accumulator (407) outputting the third phase selection signal pselc according to the duty cycle trim value and the first period selection signal psel for controlling the third multiplexer (306).

Optionally, the control signal generating circuit further comprises:

a first D flip-flop (401) that inputs the inverted output signal QB, inputs the digital pulse width modulation signal as a clock signal, and outputs a second period selection signal phasesel;

a second D flip-flop (402) that inputs the second periodic selection signal phasesel, inputs the third periodic modulation clock signal clkp as a clock signal, and outputs a Q0 signal, the Q0 signal being a signal that the second periodic selection signal phasesel delays to coincide with a falling edge of the third periodic modulation clock signal clkp;

a third D flip-flop (403) which inputs the Q0 signal, inputs the third periodic modulation clock signal clkp as a clock signal, and outputs a pdsel signal which is a signal of delaying the Q0 signal by one third periodic modulation clock signal clkp period, wherein the pdsel signal is input to the first accumulator (404) and the second accumulator (405) as a clock signal;

a fourth D flip-flop (408) that inputs a digital pulse width modulation signal, inputs the third periodic modulation clock signal clkp as a clock signal, and outputs a Q1 signal, the Q1 signal being a signal in which the digital pulse width modulation signal is delayed to coincide with a falling edge of the third periodic modulation clock signal clkp;

a fifth D flip-flop (409) that inputs the Q1 signal, inputs the third periodic modulation clock signal clkp as a clock signal, and outputs a Q2 signal, the Q2 signal being a signal in which the Q1 signal is delayed by one period of the third periodic modulation clock signal clkp;

a sixth D flip-flop (410) that inputs the Q2 signal, inputs the third periodic modulation clock signal clkp as a clock signal, and outputs a Q3 signal, the Q3 signal being a signal in which the Q2 signal is delayed by one period of the third periodic modulation clock signal clkp;

a seventh D flip-flop (411) that inputs the Q3 signal, inputs the third period modulation clock signal clkp as a clock signal, and outputs a dutysel signal that is a signal in which the Q3 signal is delayed by one period of the third period modulation clock signal clkp, wherein the dutysel signal is input to the third accumulator (407) as a clock signal.

Optionally, the first clock selector (303) and the second clock selector (307) are glitch-free clock selectors.

Optionally, the SR latch (305) is configured to enable and start counting when a rising edge of the set signal S occurs, and to reset the output to 0 and stop counting when a rising edge of the reset signal R occurs.

In the digital pulse width modulation circuit, the main modulation circuit generates the DPWM signal with adjustable period according to the plurality of delay clock signals generated by the DLL circuit and the control signal generated by the control signal generation circuit, namely, the period of the DPWM signal is adjustable, so that the flexibility of the adjustment of the digital pulse width modulation circuit can be improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is a basic circuit diagram of a DPWM circuit provided by the embodiment of the invention;

FIG. 2 is a schematic diagram of a DLL circuit provided by an embodiment of the present invention;

FIG. 3 is a timing diagram of clock delay signals according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a main modulation circuit provided by an embodiment of the present invention;

FIG. 5 is a timing diagram of clock selection according to an embodiment of the present invention;

FIG. 6 is a multi-cycle timing diagram of DPWM signal generation in accordance with an embodiment of the present invention;

FIG. 7 is a timing diagram of a single cycle of DPWM signal generation in accordance with an embodiment of the present invention;

FIG. 8 is a schematic diagram of a control signal generating circuit according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a glitch-free clock selection circuit according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are all embodiments of the present application, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The term "comprising" and any variations thereof in the description and claims of this application and the above-described drawings are intended to cover non-exclusive inclusions. For example, a process, method, or system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used to distinguish between different objects and are not used to describe a particular order.

Fig. 1 is a basic circuit diagram of a DPWM circuit according to an embodiment of the present invention. As shown in fig. 1, the digital pwm circuit mainly includes a DLL circuit 101, a main modulation circuit 102, and a control signal generation circuit 103. The input of the DLL circuit 101 is connected to a clock signal CLK, which provides a reference clock of period T to the entire digital pulse width modulation circuit. In the present embodiment, the period of the clock signal CLK is named a first period T. It should be noted that, in the present embodiment, the clock signal CLK can adopt a low-speed clock, as described later, through the design of the present invention, even if the low-speed clock is adopted, a relatively high DPWM signal accuracy can be achieved, thereby avoiding the high cost disadvantage caused by using a high-speed clock.

The DLL circuit 101, i.e., a Delay-locked Loop (Delay-locked Loop), has a plurality of Delay units, which can generate a plurality of delayed clock signals sequentially delayed by a fixed time according to a clock signal CLK, and more specifically, can decompose the clock signal CLK into a set of delayed clock signals with different phases or sequentially delayed time intervals t, which are called delayed clock signals. In this embodiment, as shown in fig. 2, there may be 8 delay units 201, each delay unit delays by 1/8 clock cycles, and outputs 8 delayed clock signals clk <0>, clk <1> \8230, clk <7>, denoted as clk <7 >. For example, if the frequency of the input clock signal CLK is 32MHz and the period is T =31.25ns, the signal delay T =3.90625ns after passing through the first delay unit is determined to be CLK <0>. By analogy, a set of delayed clock signals CLK <7> as shown in fig. 3 is derived from the clock signal CLK after passing through the delay circuit.

Before the main modulation circuit 102 is explained, the control signal generation circuit 103 will be briefly explained. It is a primary objective of the present invention to adjust the period (second period) of the output DPWM signal by the main modulation circuit 102, i.e. the second period is made adjustable based on the first period T, and the control signal or parameter for adjusting the second period is generated by the control signal generating circuit 103 and inputted to the main modulation circuit 102. These control signals may be a coarse period _ set or the like as described later.

As shown in fig. 1, the main modulation circuit 102 is commonly connected to the DLL circuit 101 and the control signal generation circuit 103. A set of delayed clock signals (e.g., clk <7 >. The control signal generated by the control signal generation circuit 103 is also input to the main modulation circuit 102. The main modulation circuit 102 may perform digital pulse width modulation according to a plurality of delayed clock signals and control signals to generate a DPWM signal. And as mentioned above, the DPWM signal has an adjustable second period that can be adjusted to be different from the first period T of the clock signal CLK.

Specifically, the DLL circuit 101 may use M delayed clock signals with sequential delay time intervals of T generated by clock signals within N cycles (N is a positive integer, and is not limited to 1 cycle, and may be 2 or 3, for example), that is, M × T = N × T is satisfied, and M is also a positive integer. The control signal generating circuit 103 generates a control signal including a coarse period _ set, and the coarse period _ set is an integer. At this time, the main modulation circuit 102 may determine or adjust the second period to be period _ set × T according to the M delayed clock signals and the coarse period adjustment value. It can thus be seen that the period coarse adjustment value period _ set is used to adjust the second period by a multiple. For example, still taking the period of the clock signal CLK as T =31.25ns as an example, the period coarse tuning value period _ set =32 is set, and let the number of the delay cells 201 in 1 period be M =8, that is, the delayed clock signal be CLK <7 >.

In addition to the coarse period adjustment value period _ set, the control signal may further include a fine period adjustment value period _ clock for fine adjustment of the second period, and the fine period adjustment value period _ clock is also an integer. At this time, the main modulation circuit 102 may determine or adjust the second period to (period _ set + period _ clock × N/M) × T according to the M delayed clock signals, the period coarse tuning value, and the period fine tuning value. Still taking the above example as an example, let M =8,n =1, that is, the number of delay units 201 in 1 cycle is 8, then the final second cycle is adjusted to (period _ set + period _ calval × N/M) × T = (32 + 2/8) × 31.25=1.007812us; if M =8,n =3, that is, the number of delay units 201 in 3 cycles is 8, the final second cycle is adjusted to (period _ set + period _ calval × N/M) × T = (32 +2 × 3/8) × 31.25=1.0234375us.

In the present invention, the main modulation circuit generates the DPWM signal with an adjustable period according to the plurality of delayed clock signals generated by the DLL circuit 101 and the control signal generated by the control signal generation circuit 103, that is, the period of the DPWM signal is made adjustable, thereby enabling to improve the flexibility of adjustment of the digital pulse width modulation circuit.

In this embodiment, in addition to the period of the DPWM signal, the duty cycle thereof may be set to be adjustable. Specifically, the control signal generated by the control signal generating circuit 103 may further include a duty coarse adjustment value duty _ set and a duty fine adjustment value duty _ calval, and the duty coarse adjustment value duty _ set and the duty fine adjustment value duty _ calval are integers and are respectively used for controlling the coarse adjustment and the fine adjustment of the duty ratio of the output DPWM signal. At this time, the main modulation circuit 102 may generate a DPWM signal with an adjustable duty ratio according to the M delayed clock signals, the coarse duty ratio adjustment value, and the fine duty ratio adjustment value, that is, the adjustable duty ratio of the DPWM signal is (duty _ set + duty _ clock × N/M)/(period _ set + period _ clock × N/M). Still taking the above example as an example, let M =8,n =1, the duty coarse adjustment value be duty _ set =10, the duty fine adjustment value be duty _ calval =2, that is, the number of delay units 201 in 1 cycle is 8, then the final second cycle is (period _ set + period _ calval × N/M) × T = (32 + 2/8) × 31.25=1.007812us, and the duty ratio is adjusted to (duty _ set + duty _ calval × N/M)/(period _ set + period _ calval × N/M) = (10 +2 × 1/8)/(32 +2 × 1/8) = 31.78295%). At this time, the adjustment accuracy of the period and the duty ratio of the DPWM signal is T = T/8=3.90625ns. It is understood that the accuracy of the adjustment and the range of adjustability are not limited to the examples given.

In the implementation, the DPWM signal is set to be both coarsely adjustable and finely adjustable in period and duty ratio, so that on one hand, the adjustment flexibility is increased; on the other hand, even in the case where the clock frequency does not need to be increased, the accuracy of the output DPWM signal can be improved.

A more specific embodiment of the digital pulse width modulation circuit according to the present invention will be described below with reference to fig. 4 to 7. It should be noted that although the following description refers to specific circuit diagrams, it will be appreciated by those skilled in the art that other alternative or preferred embodiments may be made from the specific circuit diagrams without departing from the spirit of the invention.

Fig. 4 is a schematic circuit diagram of the main modulation circuit 102 according to the present invention. In the present embodiment, the main modulation circuit 102 has both the duty cycle adjustment function and the duty cycle adjustment function, and therefore, may be referred to as the duty cycle and duty cycle modulation circuit 102. As shown in fig. 4, the period and duty cycle modulation circuit 102 mainly includes a period modulation circuit, a duty cycle modulation circuit, and an SR latch 305. The period modulation circuit is used for realizing coarse and fine adjustment of the period of the DPWM signal, and mainly includes a first multiplexer 301, a second multiplexer 302, a first clock selector 303, and a conventional counter 304.

The first multiplexer 301 and the second multiplexer 302 are specifically M:1 selectors, which are respectively connected to the DLL circuit 101, and M delayed clock signals clk < M-1 >. The first multiplexer 301 also receives a first phase selection signal psela, which will be described later, from the control signal generation circuit 103, and selects and outputs a first periodic modulation clock signal clka from among the M delayed clock signals clk < M-1 > based on the first phase selection signal psela. In this embodiment, still taking the example that the frequency of the input clock signal CLK is 32MHz, the first period T =31.25ns, m =8, and n =1 as an example, at this time, the first multiplexer 301 may gate different delayed clock signals CLK <7> at different times through the 3-bit first phase selection signal psela <2 >. Specifically, the clka strobe is clk <4> when psela <2> =100, clk <0> when psela <2> =000, and so on, ultimately generating a complete clka signal, as shown in fig. 5.

Similarly, the second multiplexer 302 also inputs a second phase selection signal pselb described later from the control signal generation circuit 103, and selects and outputs a second periodic modulation clock signal clkb from among the M delayed clock signals clk < M-1 > in accordance with the second phase selection signal pselb. Specifically, the clkb strobe is clk <2> when pselb <2> =010, the clkb strobe is clk <6> when pselb <2> =110, and so on, ultimately generating a complete clkb signal, as shown in fig. 5.

The first clock selector 303 may be a glitch-free clock selector, which is connected to the first multiplexer 301 and the second multiplexer 302, and receives the strobe signals clka and clkb output from the first multiplexer and the second multiplexer, respectively. In addition, the first clock selector 303 further inputs a corresponding second period selection signal phasesel from the control signal generating circuit 103, and the second period selection signal phasesel may be 1 bit. The first clock selector 303 gates different signals at different times through the second periodic selection signal phasesel, that is, performs switching selection on the first periodic modulation clock signal clka and the second periodic modulation clock signal clkb to obtain a third periodic modulation clock signal clkp. For example, as shown in fig. 6, clkp is gated as clka when phasesel =0, and clkp is gated as clkb when phasesel =1.

The conventional counter 304 is connected to the first clock selector 303, and is configured to count the third period modulation clock signal clkp, and output a set signal S (which is a set signal with respect to the SR latch 305 because it is input to a set terminal of the SR latch 305) to the SR latch 305 when the count reaches the period coarse value period _ set, the set signal S being used for the SR latch 305 to generate the DPWM signal. More specifically, the conventional counter 304 is a 5-bit counter that counts with the falling edge of clkp as a clock signal, and outputs the set signal S at a high level when the count is equal to period _ set, and continues counting at a low level otherwise. As shown in the above example, taking the period coarse adjustment value period _ set =32, the 5-bit regular counter 304 outputs a high level when the count binary number is 11111+1=00000, and thus the set signal S is a 32-division of the clkp signal.

In contrast, the duty cycle modulation circuit is used for implementing coarse and fine duty cycle adjustment of the DPWM signal, and mainly includes a third multiplexer 306, a second clock selector 307, and an SR enable counter 308.

The third multiplexer 306 is connected to the DLL circuit 101, and similarly to the first and

second multiplexers

301, 302, the first duty-cycle-modulated clock signal clkc can be selected from M (8 in the present embodiment) delayed clock signals clk <7> in accordance with a third phase selection signal pselc <2> from the control signal generation circuit 103 and output. Specifically, the clkc strobe is clk <4> when pselc <2> =100, clk <6> when pselc <2> =110, and so on, ultimately generating the complete clkc signal, as shown in fig. 5.

Similarly to the first clock selector 303, the second clock selector 307 may specifically be a glitch-free clock selector, is connected to the first clock selector 303 and the third multiplexer 306, and performs switching selection on the third periodic modulation clock signal clkp and the first duty modulation clock signal clkc according to a 1-bit duty selection signal dutysel from the control signal generation circuit 103, so as to obtain a second duty modulation clock signal clkd. For example, as shown in fig. 6, clkd is gated as clkp when dutysel =0, and clkp is gated as clkc when dutysel =1.

The SR enable counter 308 is connected to the regular counter 304, the second clock selector 307 and the SR latch 305, and is configured to count the second duty-modulated clock signal clkd and output a reset signal R to the SR latch 305 when the count reaches the coarse duty value duty _ set, the reset signal R being used for the SR latch 305 to generate the DPWM signal. As shown in fig. 4, the SR enable counter 308 inputs clkd, S, and R, and outputs R. More specifically, the SR enable counter 308 modulates the falling edge of the clock signal clkd at the second duty ratio as a clock signal, the counter 308 starts counting when the set signal S is at a high level and the reset signal R is at a low level, the output reset signal R flips to a high level when the value is accumulated to the set duty coarse _ set, the reset signal R flips to a low level when the next falling edge of clkd comes, and the above operation is repeated when the set signal S is again at a high level.

The SR latch 305 is used to finally output the DPWM signal, which is connected to both the period modulation circuit and the duty cycle modulation circuit, and more specifically, as described above and shown in fig. 4, the set terminal thereof is connected to the output terminal of the regular counter 304, the reset terminal thereof is connected to the output terminal of the SR enable counter 308, that is, the input signal of the SR latch 305 is S and R, and the output signal is the DPWM signal. As shown in fig. 6, the SR latch 305 outputs the DPWM signal at a high level when the set signal S is at a high level and the reset signal R is at a low level, outputs the DPWM signal at a low level when the set signal S is at a low level and the reset signal R is at a high level, and outputs the DPWM signal at a low level when the set signal S is at a low level and the reset signal R is at a low level while maintaining the DPWM signal.

Next, a method of adjusting the cycle and the duty ratio in the main modulation circuit 102 will be described in addition to the above-described circuit connection relationship. First, the method of coarse tuning the period and duty cycle is to adjust the values of the period coarse tuning value period _ set and the duty cycle coarse tuning value duty _ set. As shown in fig. 7, the 5-bit conventional counter 304 starts counting with reference to the falling edge of the first clkp signal, and outputs the S signal at high level when the count is 0; the SR enable counter 308 starts counting with reference to the falling edge of the first clkd signal, the count is 0, the output R signal is low, and the DPWM signal outputs high under the action of the high S signal and the low R signal. The conventional counter 304, which has a 5bit falling edge of the second clkp signal, counts to 1 and outputs the S signal as low, while the SR enable counter 308, which has a falling edge of the second clkd signal, counts to 1 and outputs the R signal as low, at which time the DPWM signal remains high under the low S signal and the low R signal. Until the falling edge of the eleventh clkd signal arrives, the SR enable counter 308 counts duty _ set =10 and outputs the R signal as high, at which time the DPWM signal outputs low under the action of the low S signal and the high R signal. When the falling edge of the twelfth clkd signal arrives, the SR enable counter 308 resets to zero and outputs the R signal as a low level, and the DPWM signal remains at a low level under the action of the low S signal and the low R signal. Until the falling edge of the thirty-third clkp signal comes, the 5-bit conventional counter 304 counts as period _ set =32, i.e. 31+1, and is converted into binary number of 11111+1=00000 by modulo operation of the 5-bit counter, so period _ set =0, the output S signal is high, at this time, the DPWM signal outputs high level under the action of the high S signal and the low R signal, and then the above actions are repeated.

Thus, the period coarse adjustment is implemented to period _ set × T =32 × 31.25ns =11 us, and the duty coarse adjustment is implemented to duty _ set/period _ set =10/32=31.25%.

On the other hand, the method for fine-tuning the period in the main modulation circuit 102 is to adjust the value of period _ calval. As shown in fig. 6 and 7, the initial time clka is selected as clk <4> by psela <2>; the clkp signal strobes clka when phasesel is low, i.e., clk <4>, when the clkp signal is delayed by period _ calval × t =7.8125ns. Therefore, the 5-bit conventional counter 304 under the control of the clkp signal will delay period _ calval × t =7.8125ns in counting every period, and likewise the period of the S signal will increase by 7.8125ns, and finally the period of the DPWM signal will also increase by 7.8125ns. With the phasesel signal toggling between high and low levels, the clkp signal toggles between clk <2>, clk <4>, clk <6>, and clk <0>, i.e. the clkp signal is delayed by 7.8125ns in each DPWM signal period, so the DPWM signal period is fixed to (period _ set + period _ calval × N/M) × T = (32 +2 × 1/8) × 31.25=32 × 31.25+7.8125=1.007812us, i.e. the period fine-tuning amount is 7.8125ns.

In yet another aspect, the method of fine-tuning the duty cycle in the main modulation circuit 102 is to adjust the value of duty _ calval. As shown in FIGS. 6 and 7, the initial time clkc is selected by pselc <2> as clk <4>, clkp is selected by phasesel as clkb, clk <2>, and the clkd signal is gated as clkp, clk <2>, when dutysel is low; when dutysel flips high, the clkd strobe is clkc, clk <4>, when the clkd signal is delayed by period _ calval × t =7.8125ns. Therefore, the SR enable counter 308 under the control of the clkd signal will delay duty _ calval × t =7.8125ns after the S signal starts counting high, and the time delay of the r signal turning high is 7.8125ns, i.e., the time of the DPWM signal high is increased by 7.8125ns. With the duty sel signal toggling between high and low levels, the clkd signal switches between clk <2>, clk <4>, clk <6>, and clk <0>, i.e. the clkd signal is delayed by 7.8125ns in each DPWM signal period, so the DPWM signal high level time is fixed to (duty _ set + duty _ calval × N/M) × T = (10 +2 × 1/8) × 31.25=10 × 31.25+7.8125=320.3125ns, the duty ratio is 320.3125ns/1.007812us =31.78295%, i.e. the duty ratio fine-tuning amount is (31.78295% -31.25%) =0.53295%.

In summary, the present invention can realize the coarse and fine adjustment of the period and duty ratio of the DPWM signal, thereby realizing more efficient and precise modulation.

Next, the control signal generation circuit 103, and particularly, the generation and adjustment of the period/duty selection signal will be described. Fig. 8 is a schematic diagram of the control signal generating circuit 103 according to the present invention. As shown in fig. 8, the control signal generating circuit 103 includes seven D flip-flops (401, 402, 403, 408, 409, 410, 411), three 3-bit accumulators (404, 405, and 407), and one 2: a 1 selector 406.

First D flip-flop 401 has an input signal of QB, a clock signal of DPWM, and an output signal of a second period selection signal phasesel, which is a divided-by-two signal of DPWM, as described above, and is output to first clock selector 303 so that clkp is periodically switched between clka and clkb.

The second D flip-flop 402 has phasesel as the input signal, clkp as the clock signal, and Q0 as the output signal, i.e., the Q0 signal is phasesel signal delayed to coincide with the falling edge of clkp signal.

The third D flip-flop 403 has Q0 as input signal, clkp as clock signal, and pdsel as output signal, i.e. pdsel delays one clkp period for Q0 signal.

The 3-bit first accumulator 404 inputs the period fine-tuning value period _ calval, the clock signal is pdsel, outputs a 3-bit first phase selection signal psela <2>, the addition is initialized to 0, and 2 × period _ calval is added at the rising edge of each pdsel and scaled to a binary magnitude to psela <0>, e.g. setting period _ calval =2, the rising edge of the first pdsel signal comes when psela <0> =100, the rising edge of the second pdsel signal comes when psela <2> =000, and so on. That is, the first accumulator 404 outputs the first phase selection signal psela to control the first multiplexer 301 according to the period fine _ clock.

The second accumulator 405 of 3 bits inputs the period fine-tuning value period _ calval, the clock signal is pdsel, and outputs a second phase selection signal pselb <2> of 3 bits, the initial value of the addition is period _ calval, and 2 × period _ calval is added at the falling edge of each pdsel, and is converted into a binary number amplitude to pselb <0>, for example, setting period _ calval =2, the falling edge of the first pdsel signal comes when pselb <0> =110, the falling edge of the second pdsel signal comes when pselb <2> =010, and so on. That is, the second accumulator 405 outputs the second phase selection signal pselb for controlling the second multiplexer 302 according to the period fine _ clock.

2:1 the input signals of the selector 406 (i.e. two-way selector) are psela <2> and pselb <2>, the clock signal is pdsel, the output signal is psel <2>, that is, when pdsel is high, psel <2> is gated as psela <0> and when pdsel is low, psel <2> is gated as pselb < 2). That is, 2: the 1 selector 406 is connected to the first accumulator 404 and the second accumulator 405, and switches the output psel between the first phase selection signal psela and the second phase selection signal pselb.

The fourth D flip-flop 408 has an input signal of DPWM, a clock signal of clkp, and an output signal of Q1, i.e., the Q1 signal is DPWM and delayed to coincide with the falling edge of clkp signal.

The fifth D flip-flop 409 has an input signal Q1, a clock signal clkp signal, and an output signal Q2, i.e., the Q2 signal delays the Q1 signal by one clkp signal period.

The sixth D flip-flop 410 has an input signal Q2, a clock signal clkp signal, and an output signal Q3, i.e., the Q3 signal delays the Q2 signal by one clkp signal period.

The seventh D flip-flop 411 has an input signal Q3, a clock signal clkp signal, and an output signal dutysel, i.e., the dutysel signal delays the Q3 signal by one clkp signal period.

The third accumulator 407 of 3 bits inputs the duty cycle adjustment value duty _ calval, inputs signal psel <0>, the clock signal is duty sel, outputs a third phase selection signal pselc <2> of 3 bits, the addition calculation initial value is 0, and the result at the falling edge of each duty sel is added duty _ calval and scaled to binary magnitude to pselc <0>, e.g. set duty _ calval =2, then the falling edge of the first duty sel signal comes when pselc <0> =010, the falling edge of the second duty sel signal comes when pselc <2> =010, and so on. That is, the third accumulator 407 outputs the third phase selection signal pselc according to the duty fine adjustment value to control the third multiplexer 306.

A method for adjusting the period/duty ratio selection signal by the control signal generation circuit 103 will be described on the basis of the circuit schematic diagram of the control signal generation circuit 103.

The method for adjusting the phase selection signal by the control signal generation circuit 103 is as follows: the given period adjustment value period _ calval is set, and may be set to an integer ranging from 0 to 7. The DPWM signal is divided by two to obtain a second period selection signal phasesel, which is delayed slightly to the clock signal pdsel of the two 3-bit accumulators 404, 405, so that both psela <2> and pselb <2> of its output have a period twice that of the DPWM signal. Since psela <2> and pselb <2> jump on the rising and falling edges, respectively, of the pdsel signal, pselb <2> is delayed by one DPWM period from psela <2 >. Meanwhile, the initial value of psela <2> is 0, while the initial value of pselb <2> is period _ calval, so pselb <2> is always ahead of psela <2> by the value of period _ calval, as shown in fig. 5 to 7.

On the other hand, the control signal generating circuit 103 adjusts the duty ratio selection signal by: the given duty cycle adjustment value duty _ calval is set, which may be an integer ranging from 0 to 7. The DPWM signal is delayed by about four clkp cycles to get the clock signal dutysel of the 3-bit accumulator 407. As each dutysel falling edge comes, pselc <2> adds the value of duty _ calval to the first period select signal psel <2 >.

In the above embodiment, the period and duty ratio modulation circuit 102 is controlled by outputting different control signals through the control signal generation circuit 103, so as to adjust the period and duty ratio of the DPWM signal.

In another embodiment, as described above, the first clock selector 303 and the second clock selector 307 may be glitch-free clock selectors, and fig. 9 is a schematic circuit diagram of the glitch-free clock selector, and as shown in fig. 9, the glitch-free clock selector may specifically include an eighth D flip-flop 501, a ninth D flip-flop 502, a tenth D flip-flop 503, a first nand gate 504, a second nand gate 505, and a fully symmetric nand gate 506. The eighth D flip-flop 501 inputs a selection signal sel, specifically, the selection signal sel input in the case of corresponding to the first clock selector 303 is the second period selection signal phasesel, and the selection signal sel input in the case of corresponding to the second clock selector 307 is the duty ratio selection signal dutysel. The ninth D flip-flop 502 and the tenth D flip-flop 503 respectively input a first clock signal clk1 and a second clock signal clk2, specifically, the first clock signal clk1 and the second clock signal clk2 input in the case of corresponding to the first clock selector 303 are a first periodic modulation clock signal clka and a second periodic modulation clock signal clkb, respectively, and the first clock signal clk1 and the second clock signal clk2 input in the case of corresponding to the second clock selector 307 are a first duty ratio modulation clock signal clkc and a third periodic modulation clock signal clkp, respectively. The first nand gate 504 and the second nand gate 505 are respectively inputted with signals as shown and then connected to the fully symmetric nand gate 506 to output a corresponding third clock signal clkout, specifically, the third clock signal clkout is the third periodic modulation clock signal clkp in the case of corresponding to the first clock selector 303, and the third clock signal clkout is the second duty cycle modulation clock signal clkd in the case of corresponding to the second clock selector 307.

Therefore, the output of the third periodic modulation clock signal clkp and the second duty ratio modulation clock signal clkd is realized through the specific setting of the glitch-free clock selector.

In the embodiments provided in the present application, it should be understood that the disclosed digital pulse width modulation circuit may be implemented in other manners. For example, the above-described embodiments of the digital pwm circuit are merely illustrative, and for example, the division of the units is only one logical function division, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted or not implemented. In addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some interfaces, and the indirect coupling or communication connection between the units may be in an electrical, mechanical or other form.

The above-mentioned embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A digital pulse width modulation circuit, comprising:

a control signal generating circuit for generating a control signal;

a main modulation circuit, connected to the delay phase-locked loop circuit and the control signal generation circuit, for generating a digital pulse width modulation signal according to a plurality of the delayed clock signals and the control signal, wherein the digital pulse width modulation signal has an adjustable second period;

taking the first period as T, the delay phase-locked loop circuit generates M delay clock signals with sequential delay time intervals of T according to the clock signals in N periods, that is, M × T = N × T, where M and N are positive integers;

the main modulation circuit determines the second period according to the M delayed clock signals, the coarse period adjustment value and the fine period adjustment value, wherein the coarse period adjustment value is period _ set, the fine period adjustment value is period _ clock, and the adjusted second period is (period _ set + period _ clock × N/M) × T.

2. The digital pulse width modulation circuit of claim 1,

the control signal further comprises a coarse duty ratio adjustment value and a fine duty ratio adjustment value, the main modulation circuit is further used for generating the digital pulse width modulation signal with the adjustable duty ratio according to the M delay clock signals, the coarse duty ratio adjustment value and the fine duty ratio adjustment value, the coarse duty ratio adjustment value is duty _ set, the fine duty ratio adjustment value is duty _ clock, and the duty ratio of the digital pulse width modulation signal after adjustment is (duty _ set + duty _ clock × N/M)/(period _ set + period _ clock × N/M).

3. The digital pulse width modulation circuit according to claim 2, wherein the master modulation circuit comprises a period modulation circuit and an SR latch (305), the period modulation circuit comprising:

a regular counter (304) connected to the first clock selector (303) for counting the third period modulation clock signal clkp and outputting a set signal S to the SR latch (305) when the count reaches the period coarse value period _ set, the set signal S being used for the SR latch (305) to generate the digital pulse width modulation signal.

4. The digital pulse width modulation circuit of claim 3, wherein the master modulation circuit further comprises a duty cycle modulation circuit comprising:

a second clock selector (307) connected to the first clock selector (303) and the third multiplexer (306), and configured to switch and select the third periodic modulation clock signal clkp and the first duty modulation clock signal clkc to obtain a second duty modulation clock signal clkd;

an SR enable counter (308) connected to the regular counter (304), the second clock selector (307) and the SR latch (305) for counting the second duty cycle modulated clock signal clkd and outputting a reset signal R to the SR latch (305) when the count reaches the duty coarse value duty _ set, the reset signal R being for the SR latch (305) to generate the digital pulse width modulated signal.

5. The digital pulse width modulation circuit of claim 4, wherein the control signal generation circuit comprises:

a first accumulator (404) outputting the first phase selection signal psela for controlling the first multiplexer (301) according to the period tweak value;

a second accumulator (405) outputting the second phase selection signal pselb for controlling the second multiplexer (302) according to the period fine-tuning value;

6. The digital pulse width modulation circuit of claim 5, wherein the control signal generation circuit further comprises:

a third D flip-flop (403) that inputs the Q0 signal, inputs the third period modulation clock signal clkp as a clock signal, and outputs a pdsel signal that is a signal of the Q0 signal delayed by one third period modulation clock signal clkp period, wherein the pdsel signal is input to the first accumulator (404) and the second accumulator (405) as a clock signal;

a sixth D flip-flop (410) that inputs the Q2 signal, inputs the third cycle modulation clock signal clkp as a clock signal, and outputs a Q3 signal, the Q3 signal being a signal in which the Q2 signal is delayed by one cycle of the third cycle modulation clock signal clkp;

a seventh D flip-flop (411) that inputs the Q3 signal, inputs the third cycle modulation clock signal clkp as a clock signal, and outputs a dutysel signal that is a signal in which the Q3 signal is delayed by one cycle of the third cycle modulation clock signal clkp, wherein the dutysel signal is input to the third accumulator (407) as a clock signal.

7. The digital pulse width modulation circuit of claim 4,

the first clock selector (303) and the second clock selector (307) are glitch-free clock selectors.

8. The digital pulse width modulation circuit of claim 4,

the SR latch (305) is configured to enable and start counting when a rising edge of the set signal S occurs, and to reset the output to 0 and stop counting when a rising edge of the reset signal R occurs.