CN109787593A - Digital pulse width modulation circuit - Google Patents
Digital pulse width modulation circuit Download PDFInfo
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- CN109787593A CN109787593A CN201811608677.8A CN201811608677A CN109787593A CN 109787593 A CN109787593 A CN 109787593A CN 201811608677 A CN201811608677 A CN 201811608677A CN 109787593 A CN109787593 A CN 109787593A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a kind of digital pulse width modulation circuits, comprising: delay PLL DLL circuit is used to generate multiple delay clock signals for successively postponing the set time according to clock signal, and the clock signal has the period 1；Signal generating circuit is controlled, is used to generate control signal；Main modulation circuit is connect with the DLL circuit and the control signal generating circuit, and for generating digital pulse width modulation DPWM signal according to multiple delay clock signals and the control signal, and the DPWM signal has adjustable second round.The invention enables the period of DPWM signal is adjustable, thus, it is possible to improve the flexibility of digital pulse width modulation circuit adjusting.
Description
Technical field
The present invention relates in integrated circuit fields signal generation technology more particularly to a kind of digital pulse width modulation circuit
(Digital Pulse Width Modulator, DPWM).
Background technique
Pulse modulation technology (Pulse-Width Modulation, PWM) is widely used in power supply adjusting and communication system
In.Pulse modulation technology can be divided into analog pulse width modulation and digital pulse width modulation.The DPWM of existing counter form is usually wrapped
It needs to improve clock frequency to reach higher modulation accuracy containing a counter and a comparator.Delay line mode
DPWM can be avoided simple raising clock frequency to reach higher modulation progress, but there is still a need for use more delay cell.
Mixing DPWM combines the design of counter form and delay line mode, includes one group of logical circuit of counter and a delay
Phase-locked loop (Delay-locked Loop, DLL), clock signal is decomposed into one group of out of phase by multiple delay cells in DLL
Low speed delay clock signals, logical circuit of counter, which can generate control signal behavior out of phase clock according to the demand of DPWM, believe
Number.Low-speed clock (i.e. low frequency clock) can be exported since the time interval of delay can be much smaller than its period
The DPWM signal of degree of precision, without using high-frequency clock.
However, during stating mixing DPWM in realization, although inventors have found that existing mixing DPWM is to duty ratio
Accurate adjusting is compared, however its controlled plant is more single, flexibility is lower.
Summary of the invention
In view of this, the present invention provides a kind of digital pulse width modulation circuit, to solve the DPWM modulation of prior art output
The problem that Signal Regulation object is single, flexibility is low.
The technical solution adopted by the present invention to solve the technical problems is: a kind of digital pulse width modulation circuit, comprising:
Delay PLL circuit is used to generate multiple delayed clocks for successively postponing the set time according to clock signal
Signal, the clock signal have the period 1；
Signal generating circuit is controlled, is used to generate control signal；
Main modulation circuit is connect with the delay PLL circuit and the control signal generating circuit, is used for root
Digital pulse width modulation signal, and the digital pulse width modulation are generated according to multiple delay clock signals and the control signal
Signal has adjustable second round.
It optionally, is T with the period 1, the delay PLL circuit is according to the clock in N number of period
Signal generates the M delay clock signals that successively delay time lag is t, that is, meets M × t=N × T, M, N are positive whole
Number；
The control signal includes period coarse adjustment value, and the main modulation circuit is according to the M delay clock signals and institute
It states period coarse adjustment value and determines the second round, wherein it with the period coarse adjustment value is period_set, described after adjusting
Two cycles are period_set × T.
It optionally, is T with the period 1, the delay PLL circuit is according to the clock in N number of period
Signal generates the M delay clock signals that successively delay time lag is t, that is, meets M × t=N × T, M, N are positive whole
Number；The control signal includes period coarse adjustment value and period fine tuning value, and the main modulation circuit is believed according to the M delayed clocks
Number, the period coarse adjustment value and the period fine tuning value determine the second round, wherein be with the period coarse adjustment value
Period_set, the period fine tuning value are period_calval, and the second round after adjusting is (period_set+
period_calval×N/M)×T。
Optionally, the control signal further includes duty ratio coarse adjustment value and duty ratio fine tuning value, and the main modulation circuit is also
It is adjustable for generating duty ratio according to the M delay clock signals, the duty ratio coarse adjustment value and the duty ratio fine tuning value
The digital pulse width modulation signal, wherein with the duty ratio coarse adjustment value be duty_set, be with the duty ratio fine tuning value
Duty_calval, the duty ratio of the digital pulse width modulation signal after adjusting are (duty_set+duty_calval × N/
M)/(period_set+period_calval×N/M)。
Optionally, the main modulation circuit includes periodic modulation circuit and S/R latch (305), the periodic modulation circuit
Include:
First multiple selector (301) and the second multiple selector (302), are connected respectively to the delay PLL
Circuit, first multiple selector (301) is according to first phase selection signal from the M of the delay PLL circuit output
Period 1 modulation clock signal clka, the second multiple selector (302) basis are selected in a delay clock signals
Second phase selection signal selects second round modulation clock signal clkb from the M delay clock signals；
First clock selector (303) is connected to first multiple selector (301) and second multi-path choice
Device (302) cuts the period 1 modulation clock signal clka and the second round modulation clock signal clkb
Selection is changed, period 3 modulation clock signal clkp is obtained；
Conventional counter (304) is connected to first clock selector (303), for the period 3 tune
Clock signal clkp processed is counted, and when counting reaches the period coarse adjustment value period_set, and Xiang Suoshu SR is latched
Device (305) exports set signal S, and the set signal S is used to generate the digital pulse width modulation for the S/R latch (305)
Signal.
Optionally, the main modulation circuit further includes duty ratio modulation circuit, and the duty ratio modulation circuit includes:
Third multiple selector (306) is connected to the delay PLL circuit, for selecting according to third phase
Signal selects the first duty ratio modulation clock signal clkc from the M delay clock signals；
Second clock selector (307) is connected to first clock selector (303) and the third multi-path choice
Device (306) carries out the period 3 modulation clock signal clkp and the first duty ratio modulation clock signal clkc
Switching selection, obtains the second duty ratio modulation clock signal clkd；
SR enablement count device (308) is connected to the conventional counter (304), second clock selector (307) and institute
S/R latch (305) are stated, for counting to the second duty ratio modulation clock signal clkd, and reach institute in counting
State duty ratio coarse adjustment value be duty_set when, Xiang Suoshu S/R latch (305) output reset signal R, the reset signal R are used for
The digital pulse width modulation signal is generated for the S/R latch (305).
Optionally, the control signal generating circuit includes:
First accumulator (404), according to the period fine tuning value export the first phase selection signal psela to
Control first multiple selector (301)；
Second accumulator (405), according to the period fine tuning value export the second phase selection signal pselb to
Control second multiple selector (302)；
Two-way selector (406) connects first accumulator (404) and second accumulator (405), and in institute
State switching output period 1 selection letter between first phase selection signal psela and the second phase selection signal pselb
Number psel；
Third accumulator (407) is exported according to the duty ratio fine tuning value and the period 1 selection signal psel
The third phase selection signal pselc is to control the third multiple selector (306).
Optionally, the control signal generating circuit further include:
First d type flip flop (401), inputs reversed output signal QB, and input digital pulse width modulation signal is believed as clock
Number, and export second round selection signal phasesel；
Second d type flip flop (402) inputs the second round selection signal phasesel, inputs the period 3
Modulation clock signal clkp exports Q0 signal as clock signal, and the Q0 signal is the second round selection signal
Phasesel is deferred to the signal being overlapped with the period 3 modulation clock signal clkp failing edge；
Third d type flip flop (403) inputs the Q0 signal, inputs the period 3 modulation clock signal clkp and makees
For clock signal, and pdsel signal is exported, the pdsel signal is one period 3 modulating clock of the Q0 signal delay
The signal in signal clkp period, wherein the pdsel signal is input into first accumulator (404) and described second tired
Add device (405) as clock signal；
Four d flip-flop (408) inputs digital pulse width modulation signal, inputs the period 3 modulation clock signal
Clkp exports Q1 signal as clock signal, and it is all with the third that the Q1 signal is that digital pulse width modulation signal delay is arrived
The signal that phase modulation clock signal clkp failing edge is overlapped；
5th d type flip flop (409) inputs the Q1 signal, inputs the period 3 modulation clock signal clkp and makees
For clock signal, and Q2 signal is exported, the Q2 signal is the period 3 modulating clock letter of the Q1 signal delay one
The signal in number clkp period；
6th d type flip flop (410) inputs the Q2 signal, inputs the period 3 modulation clock signal clkp and makees
For clock signal, and Q3 signal is exported, the Q3 signal is the period 3 modulating clock letter of the Q2 signal delay one
The signal in number clkp period；
7th d type flip flop (411) inputs the Q3 signal, inputs the period 3 modulation clock signal clkp and makees
For clock signal, and dutysel signal is exported, the dutysel signal is one period 3 of the Q3 signal delay
The signal in modulation clock signal clkp period, wherein the dutysel signal is input into the third accumulator (407) and makees
For clock signal.
Optionally, first clock selector (303) and the second clock selector (307) are burr-free clock choosing
Select device.
Optionally, the S/R latch (305) is configured as enabling and starting when rising edge occurs in the set signal S
It counts, when rising edge occurs in the reset signal R, output resets to 0 and stops counting.
In the above-mentioned digital pulse width modulation circuit that invention provides, main modulation circuit multiple prolongs according to what DLL circuit generated
The control signal that slow clock signal and control signal generating circuit generate, Lai Shengcheng period adjustable DPWM signal, that is, so that
The period of DPWM signal is adjustable, and thus, it is possible to improve the flexibility of digital pulse width modulation circuit adjusting.
Detailed description of the invention
It in order to more clearly explain the technical solutions in the embodiments of the present application, below will be to embodiment or description of the prior art
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some of the application
Embodiment for those of ordinary skill in the art without any creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the basic circuit schematic diagram of DPWM circuit provided by the embodiment of the present invention；
Fig. 2 is the schematic diagram of DLL circuit provided by the embodiment of the present invention；
Fig. 3 is the timing diagram of clock delay signal in the embodiment of the present invention；
Fig. 4 is the schematic diagram of main modulation circuit provided by the embodiment of the present invention；
Fig. 5 is clock selecting timing diagram in the embodiment of the present invention；
Fig. 6 is the multicycle timing diagram that DPWM signal generates in the embodiment of the present invention；
Fig. 7 is the monocycle timing diagram that DPWM signal generates in the embodiment of the present invention；
Fig. 8 is the schematic diagram of control signal generating circuit provided by the embodiment of the present invention；
Fig. 9 is the schematic diagram of burr-free clock selection circuit provided by the embodiment of the present invention.
Specific embodiment
In order to make those skilled in the art more fully understand application scheme, below in conjunction in the embodiment of the present application
Attached drawing, technical solutions in the embodiments of the present application are explicitly described, it is clear that described embodiment be the application all the way
Embodiment, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art are not making
Every other embodiment obtained, shall fall within the protection scope of the present application under the premise of creative work.
The description and claims of this application and term " includes " and their any deformations in above-mentioned attached drawing, meaning
Figure, which is to cover, non-exclusive includes.Such as process, method or system comprising a series of steps or units, product or equipment do not have
It is defined in listed step or unit, but optionally further comprising the step of not listing or unit, or optionally also wrap
Include the other step or units intrinsic for these process, methods, product or equipment.In addition, term " first ", " second " and
" third " etc. is for distinguishing different objects, not for description particular order.
Fig. 1 is the basic circuit schematic diagram of DPWM circuit provided by the embodiment of the present invention.As shown in Figure 1, digital pulse width
Modulation circuit mainly includes DLL circuit 101, main modulation circuit 102 and control signal generating circuit 103.DLL circuit 101 it is defeated
Enter end connection clock signal clk, clock signal clk provides the reference clock that the period is T for entire digital pulse width modulation circuit.?
In the present embodiment, the period of clock signal clk is named as period 1 T.It should be noted that in the present embodiment, clock letter
Low-speed clock can be used in number CLK, as described later, design through the invention, even if can also reach and compare using low-speed clock
High DPWM signal accuracy, to avoid using the high cost disadvantage of high-frequency clock bring.
DLL circuit 101, i.e. delay PLL (Delay-locked Loop) have multiple delay cells, can basis
Clock signal clk generates multiple delay clock signals for successively postponing the set time, more specifically, can be by clock signal clk point
Xie Weiyi group out of phase or successively delay time lag are the delay clock signals of t, referred to as delay clock signals.In this implementation
In example, as shown in Fig. 2, can be 8 delay cells 201, each unit be delayed 1/8 clock cycle, 8 delayed clocks of output
Signal clk<0>, clk<1>... clk<7>are expressed as clk<7:0>.For example, the frequency of the clock signal clk of order input is
32MHz, period T=31.25ns, then signal delay t=3.90625ns obtains clk < 0 after first delay cell
>.And so on, by clock signal clk by obtaining one group of delay clock signals clk < 7 as shown in Figure 3 after delay circuit:
0>。
Before main modulation circuit 102 is illustrated, first control signal generating circuit 103 is briefly described.This hair
A bright main purpose is to adjust the period (second round) of the DPWM signal of output by main modulation circuit 102, that is,
So that second round is adjustable on the basis of period 1 T, and adjust the control signal of second round or parameter then passes through control letter
Number generation circuit 103 is generated and is inputted to main modulation circuit 102.These control signals can be period coarse adjustment value as described later
Period_set etc..
As shown in Figure 1, main modulation circuit 102 is connect jointly with DLL circuit 101 and control signal generating circuit 103.DLL
One group of delay clock signals (such as clk<7:0>) that circuit 101 generates input main modulation circuit 102.Control signal generating circuit
The 103 control signals generated also input main modulation circuit 102.Main modulation circuit 102 can be according to multiple delay clock signals and control
Signal processed carries out digital pulse width modulation, generates DPWM signal.And as described above, the DPWM signal has adjustable second week
Phase, the second round can be adjusted to that different from the period 1 T of clock signal clk.
Specifically, DLL circuit 101 can be used in N number of period that (N is positive integer, is not limited to 1 period, may be, for example, 2
It is a or 3 etc.) the M delay clock signals that successively delay time lag is t that generate of clock signal, that is, meet equation M × t
=N × T, M are also positive integer.And controlling signal generating circuit 103 to generate control signal includes period coarse adjustment value period_set,
And period coarse adjustment value period_set is integer.At this point, main modulation circuit 102 can be thick according to M delay clock signals and period
Tone pitch is determining or adjusts second round as period_set × T.It can thus be seen that period coarse adjustment value period_set be used at
Second round is adjusted again.For example, still by taking the period of clock signal clk is T=31.25ns as an example, period coarse adjustment is set
Value period_set=32, and enabling the number of delay cell 201 in 1 period is M=8, i.e., delay clock signals are clk < 7:0
>, then final second round is adjusted to period_set+ × T=32 × 31.25ns=1us.
Other than above-mentioned period coarse adjustment value period_set, in order to more accurately meticulously adjust second round, signal is controlled
It may also include period fine tuning value period_calval, similarly, period fine tuning value period_calval is also integer.At this point,
Main modulation circuit 102 can be according to M delay clock signals, period coarse adjustment value and period fine tuning value is determining or adjusting second round is
(period_set+period_calval×N/M)×T.Still by taking above-mentioned example as an example, M=8, N=1 are enabled, is i.e. is prolonged in 1 period
The number of slow unit 201 is 8, then final second round is adjusted to (period_set+period_calval × N/M) × T=
(32+2/8) × 31.25=1.007812us；If enabling M=8, N=3, i.e. the number of delay cell 201 is 8 in 3 periods, then
Final second round is adjusted to (period_set+period_calval × N/M) × T=(32+2 × 3/8) × 31.25=
1.0234375us。
In invention, the multiple delay clock signals and control signal that main modulation circuit is generated according to DLL circuit 101 are generated
The control signal that circuit 103 generates, Lai Shengcheng period adjustable DPWM signal, that is, so that the period of DPWM signal is adjustable, thus
It can be improved the flexibility of digital pulse width modulation circuit adjusting.
In the present embodiment, other than the period of DPWM signal, its also settable duty ratio is adjustable.Specifically, control letter
The control signal that number generation circuit 103 generates may also include duty ratio coarse adjustment value duty_set and duty ratio fine tuning value duty_
Calval, and duty ratio coarse adjustment value duty_set and duty ratio fine tuning value duty_calval are integer, are respectively used to control defeated
The coarse adjustment and fine tuning of DPWM signal dutyfactor out.At this point, main modulation circuit 102 can be thick according to M delay clock signals, duty ratio
Tone pitch and duty ratio fine tuning value generate the adjustable DPWM signal of duty ratio, i.e. the adjustable duty cycle of DPWM signal is (duty_set+
duty_calval×N/M)/(period_set+period_calval×N/M).Still by taking above-mentioned example as an example, M=8, N=are enabled
1, duty ratio coarse adjustment value is duty_set=10, and duty ratio fine tuning value is duty_calval=2, i.e. delay cell in 1 period
201 number be 8, then final second round be (period_set+period_calval × N/M) × T=(32+2/8) ×
31.25=1.007812us duty ratio is adjusted to (duty_set+duty_calval × N/M)/(period_set+
Period_calval × N/M)=(10+2 × 1/8)/(32+2 × 1/8)=31.78295%.At this point, the period of DPWM signal
Degree of regulation with duty ratio is t=T/8=3.90625ns.It is understood that the precision and adjustable range that adjust are unlimited
In given example.
It in this embodiment, is that period and duty ratio can coarse adjustment and fine tunings by setting DPWM signal, on the one hand, increase
The flexibility of adjusting；On the other hand, even if without in the case where improving clock frequency, also can be improved output DPWM signal
Precision.
Hereinafter, being carried out referring to Fig. 4 to Fig. 7 to the more specific embodiment of digital pulse width modulation circuit provided by the present invention
Explanation.It should be noted that, although following be illustrated with physical circuit figure, it will be appreciated by persons skilled in the art that
It does not depart under spirit of the invention, following physical circuit figures can also have other substitutions or more preferably embodiment.
Fig. 4 is the circuit diagram of main modulation circuit 102 provided by the present invention.In the present embodiment, due to main modulation
Circuit 102 has periodic adjustment and duty cycle adjustment effect simultaneously, therefore can be described as period and duty ratio modulation circuit 102 again.
As shown in figure 4, period and duty ratio modulation circuit 102 mainly include that periodic modulation circuit, duty ratio modulation circuit and SR are latched
Device 305.Periodic modulation circuit for realizing DPWM signal period coarse adjustment and fine tuning, mainly include the first multiple selector 301,
Second multiple selector 302, the first clock selector 303 and conventional counter 304.
First multiple selector 301 and the second multiple selector 302 are specially M:1 selector, are connected respectively to DLL circuit
101, M delay clock signals clk<M-1:0>is inputted from DLL circuit 101.In addition, the first multiple selector 301 is also from control
Signal generating circuit 103 inputs aftermentioned first phase selection signal psela, and according to first phase selection signal psela
Period 1 modulation clock signal clka is selected from M delay clock signals clk<M-1:0>and is exported.Wherein, in this implementation
It is still 32MHz, period 1 T=31.25ns, M=8 with input clock signal CLK frequency in example, for N=1, at this point,
First multiple selector 301 can be gated in different times not by the first phase selection signal psela<2:0>of 3bit
Same delay clock signals clk<7:0>.Specifically, as psela<2:0>=100, clka is gated for clk<4>, when psela<
2:0>=000 when clka be gated for clk<0>, and so on, ultimately generate complete clka signal, as shown in Figure 5.
Similarly, the second multiple selector 302 also inputs aftermentioned second phase selection from control signal generating circuit 103
Signal pselb, and second week is selected from M delay clock signals clk<M-1:0>according to second phase selection signal pselb
Phase modulation clock signal clkb is simultaneously exported.Specifically, as pselb<2:0>=010, clkb is gated for clk<2>, when pselb<
2:0>=110 when clkb be gated for clk<6>, and so on, ultimately generate complete clkb signal, as shown in Figure 5.
First clock selector 303 concretely burr-free clock selector, be connected to the first multiple selector 301 and
Second multiple selector 302 receives gating signal clka and clkb that the two exports respectively.In addition, the first clock selector 303
Corresponding second round selection signal phasesel also is inputted from control signal generating circuit 103, the second round selection signal
Phasesel is 1bit.First clock selector 303 is by second round selection signal phasesel in different time
Different signals is gated, that is, carrying out to period 1 modulation clock signal clka and second round modulation clock signal clkb
Switching selection, obtains period 3 modulation clock signal clkp.Such as shown in Fig. 6, as phasesel=0, clkp is gated for
Clka, as phasesel=1, clkp is gated for clkb.
Conventional counter 304 is connected to the first clock selector 303, for period 3 modulation clock signal clkp into
Row counts, and when counting reaches period coarse adjustment value period_set, exports set signal S (opposite SR to S/R latch 305
It is set signal for latch 305, because of its set terminal for being input to S/R latch 305), set signal S is used for for SR
Latch 305 generates DPWM signal.More specifically, conventional counter 304 be 5bit counter, using the failing edge of clkp as when
Clock signal is counted, and the set signal S of high level is exported when counting and being equal to period_set, is otherwise low level continuation
It counts.As shown in above-mentioned example, take period coarse adjustment value period_set=32, then the conventional counter 304 of 5bit meter two into
Number processed exports high level when being 11111+1=00000, therefore set signal S is 32 frequency dividings of clkp signal.
In contrast, duty ratio modulation circuit mainly includes for realizing the duty ratio coarse adjustment and fine tuning of DPWM signal
Third multiple selector 306, second clock selector 307 and SR enablement count device 308.
Third multiple selector 306 is connected to DLL circuit 101, similar with first and second multiple selector 301,302
Ground, can be a (in the present embodiment from M according to the third phase selection signal pselc<2:0>from control signal generating circuit 103
In be 8) select the first duty ratio modulation clock signal clkc in delay clock signals clk<7:0>and export.Specifically, when
Clkc is gated for clk<4>when pselc<2:0>=100, and as pselc<2:0>=110, clkc is gated for clk<6>, with such
It pushes away, ultimately generates complete clkc signal, as shown in Figure 5.
Similarly with the first clock selector 303, the concretely burr-free clock selector of second clock selector 307,
It is connected to the first clock selector 303 and third multiple selector 306, and according to from control signal generating circuit 103
The duty ratio selection signal dutysel of 1bit believes period 3 modulation clock signal clkp and the first duty ratio modulation clock
Number clkc switches over selection, obtains the second duty ratio modulation clock signal clkd.Such as shown in Fig. 6, as dutysel=0
Clkd is gated for clkp, and as dutysel=1, clkp is gated for clkc.
SR enablement count device 308 is connected to conventional counter 304, second clock selector 307 and S/R latch 305, uses
It is counted in the second duty ratio modulation clock signal clkd, and when counting reaches duty ratio coarse adjustment value duty_set,
It is used to generate DPWM signal for S/R latch 305 to 305 output reset signal R of S/R latch, reset signal R.As shown in figure 4,
308 input signal of SR enablement count device is clkd, S and R, output signal R.More specifically, SR enablement count device 308 is with second
The failing edge of duty ratio modulation clock signal clkd is clock signal, when set signal S is high level and reset signal R is low electricity
Usually, counter 308 starts counting, and when numerical value is added to the duty ratio coarse adjustment value duty_set of setting, the reset of output is believed
Number R overturning is high level, and when next clkd failing edge comes interim, it is low level that reset signal R overturn again, and works as set
The above movement is repeated when signal S is high level again.
S/R latch 305 is used for final output DPWM signal, connects periodic modulation circuit and duty ratio modulation electricity simultaneously
Road, more specifically, set terminal connects the output end of conventional counter 304, reseting terminal as described above and shown in Fig. 4
Connect the output end of SR enablement count device 308, that is, the input signal of S/R latch 305 is S and R, and output signal is DPWM letter
Number.As shown in fig. 6, S/R latch 305 set signal S be high level and reset signal R be low level when export DPWM letter
Number be high level, the DPWM signal exported when set signal S is low level and reset signal R is high level is low level, when
Set signal S is low level and DPWM signal that reset signal R is exported when being low level remains unchanged, and is finally obtained complete
DPWM signal.
Then, on the basis of foregoing circuit connection relationship, to the side of regulating cycle and duty ratio in main modulation circuit 102
Method is illustrated.Firstly, the method for coarse adjustment period and duty ratio is regulating cycle coarse adjustment value period_set and duty ratio coarse adjustment
The value of value duty_set.As shown in fig. 7, the conventional counter 304 of 5bit is that reference is opened with the failing edge of first clkp signal
Begin to count, output S signal is high level when being counted as 0；SR enablement count device 308 is ginseng with the failing edge of first clkd signal
It examines and starts counting, being counted as 0 output R signal is low level, and DPWM signal exports under high S signal and the effect of low R signal at this time
High level.The conventional counter 304 that the failing edge of second clkp signal carrys out interim 5bit is counted as 1 and exports S signal to be low
Level, and the failing edge of second clkd signal carrys out interim SR enablement count device 308 to be counted as 1 output R signal to be low level, this
When DPWM signal low S signal and low R signal effect under remain high level.Until the failing edge of the 11st clkd signal comes
Temporarily, SR enablement count device 308 is counted as duty_set=10 and exports R signal to be high level, and DPWM signal is believed in low S at this time
Number and the effect of high R signal is lower exports low level.The failing edge of 12nd clkd signal arrives, and SR enablement count device 308 is zeroed
And exporting R signal is low level, DPWM signal remains low level under low S signal and the effect of low R signal at this time.Until third
The failing edge of 13 clkp signals comes temporarily, and the conventional counter 304 of 5bit is counted as period_set=32, i.e. 31+1,
Being converted to binary number through 5bit counter modulo operation is 11111+1=00000, therefore period_set=0, exports S signal
For high level, DPWM signal exports high level under high S signal and the effect of low R signal at this time, repeats the above movement later.
Hereby it is achieved that period coarse adjustment is period_set × T=32 × 31.25ns=1us, realize that duty ratio coarse adjustment is
Duty_set/period_set=10/32=31.25%.
On the other hand, the method in fine tuning period is to adjust the value of period_calval in main modulation circuit 102.Such as Fig. 6 and
Shown in Fig. 7, initial time clka is selected as clk<4>by psela<2:0>, and clkb is selected as clk<2>by pselb<2:0>,
Clkp signal is gated for clkb, i.e. clk<2>in phasesel high level；When phasesel is low level, clkp signal is selected
Lead to for clka, i.e. clk<4>, at this time clkp signal delay period_calval × t=7.8125ns.Therefore, believe in clkp
Number control lower each period of 5bit conventional counter 304 can postpone period_calval × t=7.8125ns in counting,
The period of same S signal will increase 7.8125ns, and the period of final DPWM signal also will increase 7.8125ns.With phasesel
Signal is overturn between low and high level, and clkp signal switches between<0>in clk<2>, clk<4>, clk<6>, clk, i.e., each DPWM
Clkp signal can all postpone 7.8125ns in signal period, so the DPWM signal period is fixed as (period_set+period_
Calval × N/M) × T=(32+2 × 1/8) × 31.25=32 × 31.25+7.8125=1.007812us, that is, the period is thin
Tune amount is 7.8125ns.
Another aspect, the method for fine tuning duty ratio is to adjust the value of duty_calval in main modulation circuit 102.Such as Fig. 6 and
Shown in Fig. 7, initial time clkc is selected as clk<4>by pselc<2:0>, and clkp is selected as clkb i.e. clk<2 by phasesel
>, clkd signal is gated for clkp i.e. clk<2>when dutysel is low level；When dutysel overturning is high level, clkd
It is gated for clkc i.e. clk<4>, at this time clkd signal delay period_calval × t=7.8125ns.Therefore, clkd signal
SR enablement count device 308 under control can be to postpone duty_calval × t=after high level starts counting in S signal
7.8125ns, R signal overturning are the time delay 7.8125ns of high level, i.e. the time of DPWM signal high level increases
7.8125ns.As dutysel signal is overturn between low and high level, clkd signal is in clk<2>, clk<4>, clk<6>, clk<0
> between switch, i.e., clkd signal can postpone 7.8125ns in each DPWM signal period, so DPWM signal high level time
It is fixed as (duty_set+duty_calval × N/M) × T=(10+2 × 1/8) × 31.25=10 × 31.25+7.8125=
320.3125ns, duty ratio 320.3125ns/1.007812us=31.78295%, that is, duty ratio fine tuning amount is
(31.78295%-31.25%)=0.53295%.
In conclusion setting through the invention, may be implemented the period of DPWM signal and the thickness tune of duty ratio, thus
It can be realized and more efficiently and accurately modulate.
Next control signal generating circuit 103 is illustrated, especially it is generated and regulating cycle/duty ratio selects
Signal is illustrated.Fig. 8 is the schematic diagram of control signal generating circuit 103 provided by the present invention.As shown in figure 8, control letter
Number generation circuit 103 includes the accumulator of seven d type flip flops (401,402,403,408,409,410,411), three 3bit
(404,405 and 407) and 2:1 selector 406.
First d type flip flop, 401 input signal is QB, and clock signal DPWM, output signal is second round selection signal
Phasesel, i.e. phasesel signal are signal obtained by DPWM two divided-frequency, as described above, the second round selection signal
Phasesel is output to the first clock selector 303, so that the period switches clkp between clka and clkb.
Second d type flip flop, 402 input signal is phasesel, clock signal clkp, output signal Q0, i.e. Q0 signal
It is overlapped for phasesel signal delay to clkp signal failing edge.
403 input signal of third d type flip flop is Q0, clock signal clkp, output signal pdsel, i.e. pdsel signal
For one clkp period of Q0 signal delay.
The first accumulator 404 of 3bit inputs period fine tuning value period_calval, clock signal pdsel, output
The first phase selection signal psela<2:0>of 3bit, additional calculation initial value is 0, and result adds 2 at the rising edge of each pdsel
× period_calval, and be scaled binary number amplitude and give psela<2:0>, such as setting period_calval=2, then
The rising edge of first pdsel signal carrys out interim psela<2:0>=100, and the rising edge of second pdsel signal comes interim
Psela<2:0>=000, and so on.That is, the first accumulator 404 is according to period fine tuning value period_calval output the
One phase selection signal psela is to control the first multiple selector 301.
The second accumulator 405 of 3bit inputs period fine tuning value period_calval, clock signal pdsel, output
The second phase selection signal pselb<2:0>of 3bit, additional calculation initial value are period_calval, and under each pdsel
Drop result at adds 2 × period_calval, and is scaled binary number amplitude and gives pselb<2:0>, such as setting period_
Calval=2, then the failing edge of first pdsel signal carrys out interim pselb<2:0>=110, under second pdsel signal
It drops along next interim pselb<2:0>=010, and so on.That is, the second accumulator 405 is according to period fine tuning value period_
Calval exports second phase selection signal pselb to control the second multiple selector 302.
(the i.e. two-way selector) input signal of 2:1 selector 406 is psela<2:0>and pselb<2:0>, clock signal are
Pdsel, output signal are psel<2:0>, i.e. psel<2:0>is gated for psela<2:0>when pdsel is high level, and pdsel is
Psel<2:0>is gated for pselb<2:0>when low level.That is, first accumulator of the connection of 2:1 selector 406 404 and second is tired
Add device 405, and the switching output psel between first phase selection signal psela and second phase selection signal pselb.
408 input signal of four d flip-flop is DPWM signal, and clock signal is clkp signal, output signal Q1, i.e. Q1
Signal is that DPWM signal delay is overlapped to clkp signal failing edge.
5th d type flip flop, 409 input signal is Q1, and clock signal is clkp signal, and output signal Q2, i.e. Q2 signal is
One clkp signal period of Q1 signal delay.
6th d type flip flop, 410 input signal is Q2, and clock signal is clkp signal, and output signal Q3, i.e. Q3 signal is
One clkp signal period of Q2 signal delay.
7th d type flip flop, 411 input signal be Q3, clock signal be clkp signal, output signal dutysel, i.e.,
Dutysel signal is one clkp signal period of Q3 signal delay.
Third accumulator 407 input duty cycle the regulated value duty_calval, input signal psel<2:0>of 3bit, clock
Signal is dutysel, exports the third phase selection signal pselc<2:0>of 3bit, and additional calculation initial value is 0, and each
The falling edge result of dutysel adds duty_calval, and is scaled binary number amplitude and gives pselc<2:0>, such as be arranged
Duty_calval=2, then the failing edge of first dutysel signal comes interim pselc<2:0>=010, second dutysel
The failing edge of signal carrys out interim pselc<2:0>=100, and so on.That is, third accumulator 407 is according to duty ratio fine tuning value
Third phase selection signal pselc is exported to control third multiple selector 306.
On the basis of the circuit diagram of above-mentioned control signal generating circuit 103, control signal generating circuit 103 is adjusted
Section period/duty ratio selection signal method is illustrated.
The method that control signal generating circuit 103 adjusts phase selection signal is: setting period demand regulated value period_
Calval, settable range are the integer between 0~7.DPWM signal two divided-frequency obtains second round selection signal phasesel,
Phasesel signal slightly postpones the clock signal pdsel as two 3bit accumulators 404,405, therefore its output
The period of psela<2:0>and pselb<2:0>twice DPWM signal.Since psela<2:0>and pselb<2:0>exist respectively
The rising edge and failing edge of pdsel signal jump, therefore pselb<2:0>postpones a DPWM period than psela<2:0>.
Meanwhile the initial value of psela<2:0>is 0, and the initial value of pselb<2:0>is period_calval, therefore pselb<2:0>is always
The numerical value of period_calval more advanced than psela<2:0>, as shown in Figures 5 to 7.
On the other hand, the method that control signal generating circuit 103 adjusts duty ratio selection signal is: given duty ratio is arranged
Regulated value duty_calval, settable range are the integer between 0~7.About four clkp periods of DPWM signal delay when
Between obtain the clock signal dutysel of 3bit accumulator 407.When each dutysel failing edge arrives, pselc<2:0>
The value of duty_calval will be added on the basis of period 1 selection signal psel<2:0>, therefore selected through pselc<2:0>
Gained clkc ratio clkp postpones the time of duty_calval × t always.
In the above specific embodiment, different control signals is exported by control signal generating circuit 103 to control week
Phase and duty ratio modulation circuit 102, to realize the period for adjusting DPWM signal and duty ratio.
In another embodiment, as described above, the first clock selector 303 and second clock selector 307 can be nothing
Burr clock selector, Fig. 9 is the circuit diagram of burr-free clock selector, as shown in figure 9, burr-free clock selects utensil
Body may include the 8th d type flip flop 501, the 9th d type flip flop 502, the tenth d type flip flop 503, the first NAND gate 504, the second NAND gate
505 and holohedral symmetry NAND gate 506.8th d type flip flop, 501 input select signal sel, specifically, in corresponding first clock selecting
The selection signal sel inputted in the case where device 303 is second round selection signal phasesel, and in corresponding second clock selection
The selection signal sel inputted in the case where device 307 is duty ratio selection signal dutysel.9th d type flip flop 502 and the tenth D touching
Hair device 503 inputs the first clock signal clk1 and second clock signal clk2 respectively, specifically, in corresponding first clock selector
The the first clock signal clk1 and second clock signal clk2 inputted in the case where 303 is respectively period 1 modulation clock signal
Clka and second round modulation clock signal clkb, and inputted in the case where corresponding second clock selector 307 first when
When clock signal clk1 and second clock signal clk2 is respectively the first duty ratio modulation clock signal clkc and period 3 modulation
Clock signal clkp.First NAND gate 504 and the second NAND gate 505 distinguish input signal as illustrated, are connected to holohedral symmetry
NAND gate 506, so that corresponding third clock signal clkout is exported, specifically, in the feelings of corresponding first clock selector 303
The third clock signal clkout exported under condition is period 3 modulation clock signal clkp, and in corresponding second clock selector
The third clock signal clkout exported in the case where 307 is the second duty ratio modulation clock signal clkd.
It can be seen that passing through the specific setting of burr-free clock selector, to realize period 3 modulation clock signal
The output of clkp and the second duty ratio modulation clock signal clkd.
In embodiment provided herein, it should be understood that disclosed digital pulse width modulation circuit can pass through
Other modes are realized.For example, the embodiment of digital pulse width modulation circuit described above is only schematical, for example,
The division of the unit, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple
Unit or assembly can be combined or can be integrated into another system, or some features can be ignored or not executed.It is another
Point, shown or discussed mutual coupling or direct-coupling or communication connection can be through some interfaces, unit
INDIRECT COUPLING or communication connection can be electrical property, mechanical or other forms.
Embodiment described above is only to illustrate the technical solution of the application, rather than its limitations；Although referring to aforementioned reality
Example is applied the application is described in detail, those skilled in the art should understand that: it still can be to aforementioned each
Technical solution documented by embodiment is modified or equivalent replacement of some of the technical features；And these are modified
Or replacement, the spirit and scope of each embodiment technical solution of the application that it does not separate the essence of the corresponding technical solution should all
Comprising within the scope of protection of this application.
Claims (10)
1. a kind of digital pulse width modulation circuit characterized by comprising
Delay PLL circuit is used to generate multiple delayed clock letters for successively postponing the set time according to clock signal
Number, the clock signal has the period 1；
Signal generating circuit is controlled, is used to generate control signal；
Main modulation circuit is connect with the delay PLL circuit and the control signal generating circuit, for according to more
A delay clock signals and the control signal generate digital pulse width modulation signal, and the digital pulse width modulation signal
With adjustable second round.
2. digital pulse width modulation circuit according to claim 1, which is characterized in that
It is T with the period 1, the delay PLL circuit generates M according to the clock signal in N number of period
Successively delay time lag is the delay clock signals of t, that is, meets M × t=N × T, M, N are positive integer；
The control signal includes period coarse adjustment value, and the main modulation circuit is according to the M delay clock signals and the week
Phase coarse adjustment value determines the second round, wherein it with the period coarse adjustment value is period_set, the second week after adjusting
Phase is period_set × T.
3. digital pulse width modulation circuit according to claim 1, which is characterized in that
It is T with the period 1, the delay PLL circuit generates M according to the clock signal in N number of period
Successively delay time lag is the delay clock signals of t, that is, meets M × t=N × T, M, N are positive integer；
The control signal includes period coarse adjustment value and period fine tuning value, and the main modulation circuit is according to the M delayed clocks
Signal, the period coarse adjustment value and the period fine tuning value determine the second round, wherein are with the period coarse adjustment value
Period_set, the period fine tuning value are period_calval, and the second round after adjusting is (period_set+
period_calval×N/M)×T。
4. digital pulse width modulation circuit according to claim 2 or 3, which is characterized in that
The control signal further includes duty ratio coarse adjustment value and duty ratio fine tuning value, and the main modulation circuit is also used to according to M
The delay clock signals, the duty ratio coarse adjustment value and the duty ratio fine tuning value generate the adjustable digital arteries and veins of duty ratio
Wide modulated signal, wherein with the duty ratio coarse adjustment value it is duty_set, is duty_calval with the duty ratio fine tuning value,
The duty ratio of the digital pulse width modulation signal after adjusting is (duty_set+duty_calval × N/M)/(period_set
+period_calval×N/M)。
5. digital pulse width modulation circuit according to claim 4, which is characterized in that the main modulation circuit includes period tune
Circuit and S/R latch (305) processed, the periodic modulation circuit include:
First multiple selector (301) and the second multiple selector (302) are connected respectively to the delay PLL electricity
Road, first multiple selector (301) is according to first phase selection signal from M of the delay PLL circuit output
Period 1 modulation clock signal clka is selected in the delay clock signals, second multiple selector (302) is according to
Two phase selection signal selects second round modulation clock signal clkb from the M delay clock signals；
First clock selector (303) is connected to first multiple selector (301) and second multiple selector
(302), the period 1 modulation clock signal clka and the second round modulation clock signal clkb are switched over
Selection, obtains period 3 modulation clock signal clkp；
Conventional counter (304) is connected to first clock selector (303), when for modulating to the period 3
Clock signal clkp is counted, and when counting reaches the period coarse adjustment value period_set, Xiang Suoshu S/R latch
(305) set signal S is exported, the set signal S is used to generate the digital pulse width modulation letter for the S/R latch (305)
Number.
6. digital pulse width modulation circuit according to claim 5, which is characterized in that the main modulation circuit further includes duty
Than modulation circuit, the duty ratio modulation circuit includes:
Third multiple selector (306) is connected to the delay PLL circuit, for according to third phase selection signal
The first duty ratio modulation clock signal clkc is selected from the M delay clock signals；
Second clock selector (307) is connected to first clock selector (303) and the third multiple selector
(306), the period 3 modulation clock signal clkp and the first duty ratio modulation clock signal clkc are cut
Selection is changed, the second duty ratio modulation clock signal clkd is obtained；
SR enablement count device (308) is connected to the conventional counter (304), second clock selector (307) and the SR
Latch (305) for counting to the second duty ratio modulation clock signal clkd, and reaches described in counting and accounts for
Sky than coarse adjustment value be duty_set when, Xiang Suoshu S/R latch (305) output reset signal R, the reset signal R be used for for institute
It states S/R latch (305) and generates the digital pulse width modulation signal.
7. digital pulse width modulation circuit according to claim 6, which is characterized in that the control signal generating circuit packet
It includes:
First accumulator (404) exports the first phase selection signal psela to control according to the period fine tuning value
First multiple selector (301)；
Second accumulator (405) exports the second phase selection signal pselb to control according to the period fine tuning value
Second multiple selector (302)；
Two-way selector (406), connects first accumulator (404) and second accumulator (405), and described the
Switching output period 1 selection signal between one phase selection signal psela and the second phase selection signal pselb
psel；
Third accumulator (407), according to the duty ratio fine tuning value and period 1 selection signal psel output
Third phase selection signal pselc is to control the third multiple selector (306).
8. digital pulse width modulation circuit according to claim 7, which is characterized in that the control signal generating circuit also wraps
It includes:
First d type flip flop (401) inputs reversed output signal QB, inputs digital pulse width modulation signal as clock signal, and
Export second round selection signal phasesel；
Second d type flip flop (402) inputs the second round selection signal phasesel, inputs the period 3 modulation
Clock signal clkp exports Q0 signal as clock signal, and the Q0 signal is the second round selection signal
Phasesel is deferred to the signal being overlapped with the period 3 modulation clock signal clkp failing edge；
Third d type flip flop (403) inputs the Q0 signal, input the period 3 modulation clock signal clkp as when
Clock signal, and pdsel signal is exported, the pdsel signal is one period 3 modulation clock signal of the Q0 signal delay
The signal in clkp period, wherein the pdsel signal is input into first accumulator (404) and second accumulator
(405) it is used as clock signal；
Four d flip-flop (408) inputs digital pulse width modulation signal, inputs the period 3 modulation clock signal clkp
As clock signal, and export Q1 signal, the Q1 signal be digital pulse width modulation signal delay to the period 3 tune
The signal that clock signal clkp failing edge processed is overlapped；
5th d type flip flop (409) inputs the Q1 signal, input the period 3 modulation clock signal clkp as when
Clock signal, and Q2 signal is exported, the Q2 signal is the period 3 modulation clock signal of the Q1 signal delay one
The signal in clkp period；
6th d type flip flop (410) inputs the Q2 signal, input the period 3 modulation clock signal clkp as when
Clock signal, and Q3 signal is exported, the Q3 signal is the period 3 modulation clock signal of the Q2 signal delay one
The signal in clkp period；
7th d type flip flop (411) inputs the Q3 signal, input the period 3 modulation clock signal clkp as when
Clock signal, and dutysel signal is exported, the dutysel signal is the period 3 modulation of the Q3 signal delay one
The signal in clock signal clkp period, wherein when the dutysel signal is input into the third accumulator (407) conduct
Clock signal.
9. digital pulse width modulation circuit according to claim 6, which is characterized in that
First clock selector (303) and the second clock selector (307) are burr-free clock selector.
10. digital pulse width modulation circuit according to claim 6, which is characterized in that
The S/R latch (305) is configured as enabling and starting counting when rising edge occurs in the set signal S, when described
When rising edge occurs in reset signal R, output resets to 0 and stops counting.
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