CN109783407B - Device and method for realizing PC and display card bridging based on FPGA - Google Patents
Device and method for realizing PC and display card bridging based on FPGA Download PDFInfo
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- CN109783407B CN109783407B CN201910032667.2A CN201910032667A CN109783407B CN 109783407 B CN109783407 B CN 109783407B CN 201910032667 A CN201910032667 A CN 201910032667A CN 109783407 B CN109783407 B CN 109783407B
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Abstract
The invention discloses a device and a method for realizing bridging between a PC and a display card based on an FPGA. The system comprises a PCIE EP module, a PCIE RP module and an ARM processor which are integrated on an FPGA, wherein the PCIE EP module is used for receiving and storing information of an internal register and BAR of a display card, analyzing a TLP sent by a PC to the display card and sending the analyzed data to the PCIE RP module; the PCIE RP module is used for carrying out power-on initialization on the display card and distributing BAR resources of the display card, and is used for packaging received data and sending the received data to the display card; the ARM processor is used for controlling the PCIE RP module to acquire information of a register and a BAR inside the display card and sending the information to the PCIE EP module. The invention carries out information simulation and data bridging on the FPGA, can simultaneously realize the functions of EP and RC, and has the advantages of no limitation of source-closed driving and strong universality.
Description
Technical Field
The invention belongs to the technical field of electronic information, and particularly relates to a device and a method for realizing bridging between a PC (personal computer) and a display card based on an FPGA (field programmable gate array).
Background
In the field of display panel testing, the market needs a portable miniaturized measuring device, and various video signals can be output through a device control display card only by inserting the display card into the device, so that the display panel can be measured. The test equipment can be miniaturized and integrated only by separating from a PC and adopting a mode based on the operation of an embedded ARM system.
To develop such a measurement device, a software engineer needs to port a graphics card driver running on a PC into an ARM. Currently, the major companies that design graphics cards (GPUs) globally, whether imperial labda (NVIDIA) or AMD, release drivers on PCs that are all closed source, which makes them impossible for software engineers to decipher and migrate to ARM.
At present, each measuring equipment manufacturer can only organize some open sources in order to solve the above problems, such as the open source display card driver that nuveau published transplants to the ARM, but this type of driver is not official release of display card manufacturer, and it can only accomplish most basic function, can't let the display card carry out complicated 3D figure and render, work such as high definition video rendering, so can't satisfy the panel manufacturer with increasing test demand.
Disclosure of Invention
The invention aims to solve the defects in the prior art, and provides a simple and effective device and method for realizing bridging between a PC and a display card based on an FPGA (field programmable gate array), so that the existence of the FPGA cannot be sensed when the PC operates the display card, and all operations performed on the display card by a closed-source display card driver on the PC can be captured by the FPGA at the bottom layer.
The technical scheme adopted by the invention is as follows: a device for realizing bridging between a PC and a display card based on an FPGA comprises a PCIE EP module integrated on the FPGA, a PCIE RP module, a PCIE EP module and a BAR module, wherein the PCIE EP module is used for receiving and storing information of an internal register and BAR of the display card, and is used for analyzing a TLP sent by the PC to the display card and sending the analyzed data to the PCIE RP module;
the PCIE RP module is used for carrying out power-on initialization on the display card and distributing BAR resources of the display card, and is used for packaging received data according to rules of the power-on initialization of the display card and sending the received data to the display card;
and the ARM processor is used for controlling the PCIE RP module to acquire the information of the internal register and the BAR of the display card and sending the information to the PCIE EP module.
The PCIE data storage module is used for analyzing data sent by the ARM processor, the PCIE EP module is used for sending the analyzed data to the DDR storage module, and the DDR storage module is used for storing the data.
Further, data transmission is performed between the PCIE EP module and the PCIE RP module through an AXI bus.
Furthermore, a first PCIE interface and a second PCIE interface are arranged on the FPGA, the first PCIE interface is used for being connected to a PC, and the second PCIE interface is used for being connected to a display card.
Further, the information of the internal register of the display card includes an ID, a manufacturer, and a model of the display card.
A method for realizing bridging between a PC and a display card based on an FPGA comprises information simulation and data bridging, wherein the information simulation comprises display card simulation and PC simulation, the display card simulation is realized by acquiring information of an internal register and a BAR of the display card, and the PC simulation is realized by editing a power-on initialization command and a BAR resource allocation command of the display card; the data bridging comprises address conversion and read-write request conversion, wherein the address conversion is used for converting the access of a PC to a video card BAR into the access of a fixed address, and the read-write request conversion is used for converting the read-write enabling signal of the PC to the video card into the read-write enabling signal of the FPGA internal bus.
The invention carries out information simulation and data bridging on the FPGA, can simultaneously realize the functions of EP and RC, and can ensure that the PC can not completely sense the existence of the FPGA by the method as if the display card is directly inserted on the PC mainboard. Therefore, all operations performed on the display card by the closed-source display card driver on the PC can be captured by the FPGA on the bottom layer, and only the captured binary data is provided for software engineers, so that the embedded display card driver with the same powerful function as the closed-source display card driver on the PC can be developed on the ARM chip.
The device and the method have the advantage of no limitation of a restricted source driver, and key data stream information can be provided for software engineers to develop high-quality video card drivers based on any CPU and any operating system.
The bridging method of the invention is transparent to PC, and can be used at any time by plugging; the method is not limited to the application scene, can be expanded to any scene with related requirements, and has strong universality.
Drawings
FIG. 1 is a schematic diagram of the apparatus of the present invention.
FIG. 2 is a schematic diagram of the method of the present invention.
Detailed Description
The invention will be further described in detail with reference to the following drawings and specific examples, which are not intended to limit the invention, but are for clear understanding.
Since the interface between the display card and the PC is PCIE, the technical scheme of the discovery is to abide by PCI
Base Specification Revision 3.0 Specification. PC is PCIE ROOT complete, RP for short, and video card is PCIE Endpoint, EP for short. In order to bridge a PC and a graphics card, it is necessary to simultaneously implement the functions of EP and RP inside an FPGA (field programmable gate array). Wherein the EP of the FPGA is used for communicating with the PC, and the RP of the FPGA is used for communicating with the display card. Inside the FPGA, a special bus is needed to bridge the EP and the RC, so that data intercommunication is realized.
Because the FPGA needs to implement the PCIE RC function, according to the PCIE specification, the FPGA needs to be responsible for performing power-on initialization and BAR resource allocation work on the display card, and this part of work is actually completed by the PC when there is no bridge connection, and needs to be completed by the FPGA after bridge connection. Since the part of the functions is software behavior, the part of the functions also needs to be completed by writing programs by using ARM inside the FPGA.
After the FPGA realizes all functional characteristics of the bridge and the data connectivity is correct, a display card driver can be installed on the PC, the relevant information of the display card can be seen in the device manager of Windows after the installation, and the PC cannot completely sense the existence of the FPGA.
And playing a video or drawing a 3D (three-dimensional) graph on the PC, and then sending an instruction to the display card by a driver on the PC to render the video and the 3D graph, wherein the instruction flows through the FPGA, is captured by logic inside the FPGA and is stored in the DDR. The data stored in the DDR is read and printed in a file, and then the file can be handed to a software engineer for compiling a driver running in the ARM, so that the function of the driver is the same as that of the driver on the PC.
Based on the principle, the device for realizing the bridge connection between the PC and the display card based on the FPGA of the present invention includes, as shown in fig. 1, a PCIE EP module integrated on one FPGA, configured to receive and store information of an internal register and a BAR of the display card, where the information of the register includes an ID, a vendor, and a model of the display card, and is configured to analyze a TLP sent from the PC to the display card, and send the analyzed data to a PCIE RP module through an AXI bus;
the TLP is a transaction layer packet defined by the PCIE protocol, and the PCIE EP module needs to resolve the following contents of the TLP, so as to perform the conversion from the TLP to the AXI bus:
a TLP packet type, the PCIE EP module identifies whether the TLP packet is a read MEM or a write MEM, and converts the read and write requests into read and write enable signals of the AXI bus.
A TLP packet address, where the TLP packet carries address information of the BAR to be read and written, and the PCIE EP module parses the address and places the address on an address line of the AXI bus
For the TLP packet data, for the write request TLP packet sent by the PC, the address is followed by the write data, and the PCIE EP module extracts the write data and places the write data on the data line of the AXI bus.
And in the direction from the PCIE EP module to the PCIE RP module, the AXI transmits the read-write enable initiated by the PC, the address and the data. And in the direction from the PCIE RP module to the PCIE EP module, the AXI transmits data returned to the PC by the display card.
The PCIE RP module is used for carrying out power-on initialization on the display card and distributing BAR resources of the display card, and is used for packaging received data according to rules of the power-on initialization of the display card and sending the received data to the display card;
and the ARM processor is used for controlling the PCIE RP module to acquire the information of the internal register and the BAR of the display card and sending the information to the PCIE EP module.
In the above scheme, in order to provide software engineers with all operation data performed on the display card by the closed-source display card driver on the PC, the device further includes a DDR storage module, the PCIE EP module is configured to send the analyzed data to the ARM processor, the ARM processor is configured to send the received data to the DDR storage module, and the DDR storage module is configured to store the data. The operation of the closed-source display card driver on the PC to the display card can flow through the FPGA, be captured by the logic inside the FPGA and be stored in the DDR storage module. The data stored in the DDR memory module is read and printed in a file, and then the data can be handed to a software engineer for compiling a driver running in the ARM, so that the function of the driver is the same as that of the driver on the PC.
In the above scheme, the FPGA is provided with a first PCIE interface and a second PCIE interface, the first PCIE interface is used for being connected to the PC, and the second PCIE interface is used for being connected to the display card.
Based on the device, the invention also provides a method for realizing the bridging between the PC and the display card based on the FPGA, which comprises information simulation and data bridging, wherein the display card simulation specifically comprises the following steps: reading register information in the display card, wherein the part of registers comprise key information such as the ID, manufacturer and model of the display card, and placing the key information into a PCIE EP module of the FPGA, so that the PC can identify the relevant information of the display card and is matched with a driven INF file, and relevant driving programs can be loaded; the information of the BAR inside the display card is acquired, the information of the BAR inside the display card can be known by utilizing an ARM processor inside the FPGA to access the BAR of the display card through the PCIE RP module, and the BAR information is copied into the PCIE EP module of the FPGA, so that an operating system on the PC can allocate base addresses to the BARs, and the base addresses are mapped into a memory space of the PC. The PC simulation specifically includes programming a PCIE RP module through an ARM processor inside the FPGA so as to realize power-on initialization and BAR resource allocation of the display card.
The data bridging includes PCIE TLP transaction conversion and FPGA internal bus transaction interconversion. The conversion process includes address conversion and read-write request conversion. The address conversion principle is to convert the access of PC to the display card BAR into the access of fixed address, and the read-write request conversion is to convert the read-write enable signal of PC to the display card into the read-write enable signal of FPGA internal bus (AXI). And writing the correct base address into the BAR of the display card according to the address conversion rule, so that the BAR operation of the FPGA EP by the PC can be converted into the BAR operation of the display card by the FPGA RP.
Detailed description of address translation:
for example, when power-on initialization is performed, the initialization base address of the PC to the BAR0 of the PCIE EP module is 0x00000000, and the initialization base address of the PCIE RP module to the display card BAR0 is 0x 20000000. Now the PC wants to read and write a register inside the BAR0 of the graphics card, assuming an offset address of 0x0000000 a.
The whole process is as follows:
an address carried in a TLP packet sent by the PC is 0x0000000a, the address may hit the BAR0 of the PCIE EP module, and after receiving the packet, the PCIE EP module may resolve the address and place the address on the AXI bus. The PCIE RP module converts the address 0x0000000a on the AXI into 0x2000000a, and encapsulates the address into a TLP packet and sends the TLP packet to the graphics card. In this way, the BAR0 of the graphics card can be hit finally, and the graphics card can be accessed.
Those not described in detail in this specification are within the skill of the art.
Claims (6)
1. The utility model provides a device based on FPGA realizes PC and display card bridging which characterized in that: including integration on an FPGA
The PCIE EP module is configured to receive and store information of an internal register and a BAR of the display card, and is configured to analyze a TLP sent by the PC to the display card and send analyzed data to the PCIE RP module;
the PCIE RP module is used for carrying out power-on initialization on the display card and distributing BAR resources of the display card, and is used for packaging received data according to rules of the power-on initialization of the display card and sending the received data to the display card;
and the ARM processor is used for controlling the PCIE RP module to acquire the information of the internal register and the BAR of the display card and sending the information to the PCIE EP module.
2. The device for realizing the bridging between the PC and the display card based on the FPGA according to claim 1, wherein: the data processing system further comprises a DDR storage module, the PCIE EP module is used for sending the analyzed data to the ARM processor, the ARM processor is used for sending the received data to the DDR storage module, and the DDR storage module is used for storing the data.
3. The device for realizing the bridging between the PC and the display card based on the FPGA according to claim 1, wherein: and the PCIE EP module and the PCIE RP module carry out data transmission through an AXI bus.
4. The device for realizing the bridging between the PC and the display card based on the FPGA according to claim 1, wherein: the FPGA is provided with a first PCIE interface and a second PCIE interface, the first PCIE interface is used for being connected with a PC, and the second PCIE interface is used for being connected with a display card.
5. The device for realizing the bridging between the PC and the display card based on the FPGA according to claim 1, wherein: the information of the internal register of the display card comprises the ID, the manufacturer and the model of the display card.
6. A method for realizing PC and display card bridging based on FPGA is characterized in that: the method comprises information simulation and data bridging, wherein the information simulation comprises display card simulation and PC simulation, the display card simulation is realized by acquiring information of a register and a BAR in a display card, and the PC simulation is realized by editing a power-on initialization command and a BAR resource allocation command of the display card; the data bridging comprises address conversion and read-write request conversion, wherein the address conversion is used for converting the access of a PC to a video card BAR into the access of a fixed address, and the read-write request conversion is used for converting the read-write enabling signal of the PC to the video card into the read-write enabling signal of the FPGA internal bus.
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| US8161209B2 (en) * | 2008-03-31 | 2012-04-17 | Advanced Micro Devices, Inc. | Peer-to-peer special purpose processor architecture and method |
| US9247179B2 (en) * | 2012-11-19 | 2016-01-26 | Nvidia Corporation | Reverse video playback in a data processing device |
| US9292414B2 (en) * | 2012-11-26 | 2016-03-22 | Nvidia Corporation | System, method, and computer program product for debugging graphics programs locally utilizing a system with a single GPU |
| US10216419B2 (en) * | 2015-11-19 | 2019-02-26 | HGST Netherlands B.V. | Direct interface between graphics processing unit and data storage unit |
| CN106844245B (en) * | 2017-02-17 | 2019-11-12 | 北京腾凌科技有限公司 | Data transmission method and device |
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| CN108234264B (en) * | 2017-12-29 | 2021-05-28 | 杭州迪普科技股份有限公司 | Data packet forwarding method and device based on PCIe signal interface expansion |
| CN108804376B (en) * | 2018-06-14 | 2021-11-19 | 山东航天电子技术研究所 | Small heterogeneous processing system based on GPU and FPGA |
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| CN103631326A (en) * | 2012-08-22 | 2014-03-12 | 成都爱斯顿测控技术有限公司 | Multi-interface embedded main board |
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