CN111209234A - Multi-serial port IP core based on Avalon-MM bus interface - Google Patents
Multi-serial port IP core based on Avalon-MM bus interface Download PDFInfo
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- CN111209234A CN111209234A CN201911350312.4A CN201911350312A CN111209234A CN 111209234 A CN111209234 A CN 111209234A CN 201911350312 A CN201911350312 A CN 201911350312A CN 111209234 A CN111209234 A CN 111209234A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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Abstract
The invention relates to a multi-serial port IP core based on an Avalon-MM bus interface, which is designed by adopting a hardware description language Verilog and comprises an Avalon-MM bus interface module for realizing data exchange from an ARM side to an FPGA side; the 8 serial ports are used for realizing data interaction between the external equipment and the storage unit; the 8 register modules respectively correspond to 8 serial ports of the serial data input and output interface unit; and the 3 global registers are respectively in communication connection with the 8 register modules through an FPGA internal bus. The Avalon-MM has independent write data lines, read data lines and address lines, has the advantages of reading effective signals, small resource occupation and the like, realizes 8 serial ports by an addressing mode, shares one interrupt by the 8 serial ports, and greatly saves interrupt resources.
Description
Technical Field
The invention relates to the technical field of serial port communication, in particular to a multi-serial port IP core based on an Avalon-MM bus interface.
Background
In the inertial navigation device, a serial port is a main interface for the device to communicate with the outside, and the number of the serial ports of one inertial navigation device is sometimes as many as more than ten. The serial ports are mostly realized by a navigation computer in the equipment, the core of the navigation computer is an SOC chip internally integrating an FPGA and an ARM, the serial ports are realized on the FPGA side, and the ARM realizes read-write and control operations on the serial ports on the FPGA side through an AXI bus.
When the device sends data to the outside, the ARM writes the sent data into each serial port in the FPGA through the AXI bus, and the FPGA serial port completes parallel-serial conversion of the data and sends the data to the outside; when the external sends data to the equipment, the FPGA serial port receives serial data input from the external, the serial-parallel conversion of the data is completed, meanwhile, an interrupt signal is generated and sent to the ARM, and after the ARM receives the interrupt signal, the data stored in the serial port register in the FPGA is read through the AXI bus.
The common mode of realizing the serial port on the FPGA side is to call a UART IP core provided by an SOC manufacturer, such as a UART 16550IP core of Xilinx company, wherein the UART 16550IP core is provided with an AXI interface and an interrupt output port and can be directly connected to an ARM, but the FIFO depth of the IP core is small (the depth is only 16 and the width is 8), and multiple interrupts can be generated when a large amount of data is received once; especially, when a plurality of serial port modules are used, a plurality of IP cores are required to be added into the system, the interrupt of each IP is connected to the ARM side, so that the interrupt resource of the ARM is wasted, and the progress of an application program is seriously influenced.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a multi-serial port IP core based on an Avalon-MM bus interface, an IP core (slave Avalon-MM equipment) conforming to the Avalon-MM bus is constructed by utilizing Avalon-MM bus interface resources, the IP core realizes the selection of serial ports through an address line, simultaneously, the IP core synthesizes interrupt signals of a plurality of serial ports into an externally output interrupt signal, and an interrupt position register is arranged, so that a master device can judge the serial port generated by interrupt, thereby realizing the processing of interrupt.
The technical scheme for solving the technical problems is as follows: a multi-serial port IP core based on an Avalon-MM bus interface is designed by adopting a hardware description language Verilog and comprises an ARM side communication interface unit, a storage unit and a serial data input and output interface unit;
the ARM side communication interface unit comprises an Avalon-MM bus interface module and an interrupt output interface module, the Avalon-MM bus interface module realizes data exchange from the ARM side to the FPGA side through a bus transfer interface, and the interrupt output interface module is used for outputting an interrupt signal to the ARM;
the serial data input and output interface unit comprises 8 serial ports and is used for realizing data interaction between external equipment and the storage unit;
the storage unit comprises 3 global registers and 8 register modules, and the 8 register modules respectively correspond to 8 serial ports of the serial data input and output interface unit; and the 3 global registers are respectively in communication connection with the 8 register modules through an FPGA internal bus.
The invention has the beneficial effects that: the Avalon bus is a bus structure for connecting a processor to on-chip and off-chip peripherals. The Avalon bus has two interfaces, namely an Avalon-MM (memory map) interface and an Avalon-st (stream) interface, wherein the Avalon-MM type interface reads and writes data through addresses, and is very suitable for a component for controlling functions. Avalon-MM has the following advantages:
1. independent write data line, read data line, address line;
2. has a read valid signal;
3. the resource occupation is less.
The IP core is designed by adopting a hardware description language Verilog, serial port realization codes are provided, the Avalon-MM bus interface specification is met, 8 serial ports are realized in an addressing mode, 8 serial ports share one interrupt, interrupt resources are greatly saved, meanwhile, the FIFO depth used in the IP core can be further expanded according to requirements, and the IP core can be applied to SOC of Xilinx company and SoC FPGA of Intel company, so that the design is flexible and convenient, and the multi-serial port design application requirements are met.
Further, the Avalon-MM bus interface module comprises: an Avalon-MM bus read enable signal interface PS2FPGA _ RD _ p;
an Avalon-MM bus write enable signal interface PS2FPGA _ WR _ p;
an Avalon-MM bus read valid signal interface ReadDataValid;
an Avalon-MM bus Data writing signal interface PS2FPGA _ WR _ Data;
and the Avalon-MM bus Data reading signal interface PS2FPGA _ RD _ Data.
Further, the 3 global registers are respectively a serial port switch register, a serial port reset register and an interrupt position register;
the serial port switch register is used for storing flag bits for marking the opening or closing of specified serial ports in the 8 serial ports;
the serial port reset register is used for storing functional data for resetting a specified serial port in the 8 serial ports;
and the interrupt position register is used for storing the serial port position generating the interrupt.
Furthermore, each register module comprises a serial port receiving register RHR, a serial port sending register THR, a low 8-bit parameter register DLL, a high 8-bit parameter register DLH, a check bit flag register LCR, an interrupt clear register ISR and a data flag register COUNT.
The serial port receiving register RHR is an FIFO register, the access type is read-only, the depth is 256, and the width is 8 bits.
The serial port sending register THR is an FIFO register, the access type is write-only, the depth is 1024, and the width is 8 bits.
The check bit flag register LCR is used to mark the number of stop bits and parity bits.
And the data flag register COUNT is used for marking the number of the data cached by the serial port receiving register RHR.
Drawings
FIG. 1 is a schematic diagram of a multi-serial port IP core structure based on an Avalon-MM bus interface according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an IP core encapsulation interface according to an embodiment of the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
Examples
As shown in fig. 1 and fig. 2, an embodiment of the present invention provides an Avalon-MM bus interface-based multi-serial port IP core, which is designed by using a hardware description language Verilog and includes an ARM side communication interface unit, a storage unit, and a serial data input/output interface unit;
the ARM side communication interface unit comprises an Avalon-MM bus interface module and an interrupt output interface module, the Avalon-MM bus interface module realizes data exchange from the ARM side to the FPGA side through a bus transfer interface, and the interrupt output interface module is used for outputting an interrupt signal to the ARM;
the serial data input and output interface unit comprises 8 serial ports and is used for realizing data interaction between external equipment and the storage unit;
the storage unit comprises 3 global registers and 8 register modules, and the 8 register modules respectively correspond to 8 serial ports of the serial data input and output interface unit; and the 3 global registers are respectively in communication connection with the 8 register modules through an FPGA internal bus.
All signals of the encapsulation interface of the IP core are clock synchronized and sampled on the rising edge of the clock. The IP core signal interface and the function are as follows:
PS _ Clk: inputting signals, an Avalon-MM bus clock and an IP core working clock;
SysRSst _ n: an input signal, a reset signal of an IP core, is low and effective;
UART _ Int _ p: the output signal is high effective, and the IP core interrupts the output signal;
UART _ RXD [7:0 ]: inputting signals, serial input data of 8 bits and 8 serial ports;
UART _ TXD [7:0 ]: output signal, serial output data of 8 bits and 8 serial ports
PS2FPGA _ RD _ p: the input signal, an Avalon-MM bus interface signal, read enable, is highly active;
ReadDataValid: outputting a signal, namely an Avalon-MM bus interface signal, reading an effective signal, and being high effective;
PS2FPGA _ WR _ Data [31:0 ]: inputting a signal, 32 bits, and writing data only by using a low 8 bits, Avalon-MM bus interface signal;
PS2FPGA _ Addr [31:0 ]: inputting signals, 32 bits, using only low 8 bits, Avalon-MM bus interface signals, address lines;
PS2FPGA _ RD _ Data [31:0 ]: outputting a signal, 32 bits, and reading data only by using a low 8 bits, Avalon-MM bus interface signal;
PS2FPGA _ WR _ p: input signal, Avalon-MM bus interface signal, write enable, high active.
The IP core comprises 3 global registers and 8 serial ports, and the functions of the 3 global registers are as follows:
(1) the interrupt register (UART _ INT0_ REG _ OFFSET), read-only register, the OFFSET address is 0x80, 8bit, used for storing the serial port position producing interrupt; if the 1 st serial port is interrupted, writing the 0 th bit into 1; and if the 2 nd serial port generates an interrupt, 1 is written into the 1 st bit, and so on.
(2) The RESET register (UART _ RESET _ REG _ OFFSET) is a write register, has an OFFSET address of 0x84 and 8 bits and is used for resetting a specified serial port in 8 serial ports; that is, the 0 th bit is 1, which represents that the 1 st serial port is reset; the 1 st bit is 1, which means that the 2 nd serial port is reset, and so on.
(3) A serial port switch register (UART _ CHAN _ REG _ OFFSET), a read/write register, an OFFSET address of 0x88, for opening or closing a designated serial port of 8 serial ports; that is, if the 0 th bit is 1, it represents that the 1 st serial port is opened, and if the 0 th bit is 0, it represents that the 1 st serial port is closed; the 1 st bit is 1, which means that the 2 nd serial port is opened, and 0, which means that the 2 nd serial port is closed, and so on.
The examples illustrate that: if the IP core is added to the system and the device BASE address is Avalon _ BASE _ ADDR, then reading the Avalon _ BASE _ ADDR + UART _ INT0_ REG _ OFFSET to know which serial port generates an interrupt, and if the read value is 0B000001011 (binary), representing that serial port 1, serial port 2, and serial port 4 generate an interrupt; writing 0B 01101101100 into the Avalon _ BASE _ ADDR + UART _ RESET _ REG _ OFFSET address, which represents that resetting operation is carried out on the serial ports 3, 4, 6 and 7; writing 0B00110010 to the address Avalon _ BASE _ ADDR + UART _ RESET _ REG _ OFFSET represents closing the serial ports 1, 3, 4, 7, and 8 and opening the serial ports 2, 5, and 6.
The offset addresses of the 8 serial ports are 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 and 0x8, the offset addresses of the serial ports are specified by [11:8] of the address line PS2FPGA _ Addr, namely when the PS2FPGA _ Addr [11:8] is equal to 0x03, the 3 rd serial port is selected; when PS2FPGA _ Addr [11:8] ═ 0x05, the 5 th serial port is selected. Each serial port has 7 registers, and the offset addresses and descriptions of the registers are shown in table 1.
Table 1 serial 7 register offset address and instruction list
When the IP core works, firstly, ARM (Avalon-MM master device) needs to initialize the IP core, namely, serial port reset and opening/closing of a specified serial port are completed through a global register, and configuration of baud rate and parity check bits of the serial port is completed through serial port registers DLL, DLH and LCR.
When the serial port receives data sent by the outside, serial data is converted into parallel data, the parallel data is written into a serial port receiving register (RHR), an interrupt signal of the serial port is generated at the same time, and the interrupt signal and interrupt signals generated by other serial ports are subjected to OR operation to be synthesized into an interrupt signal UART _ Int _ p and output to the main device.
When an interrupt signal is generated, the IP core writes the position of the serial port generating the interrupt in 8 serial ports in an interrupt position register, namely the 1 st serial port generates the interrupt, and writes the 0 th bit into 1; and if the 2 nd serial port generates an interrupt, 1 is written into the 1 st bit, and so on.
When the serial port in the IP core receives the reading signal for reading the serial port interrupt clearing register, the interrupt signal generated by the serial port is cleared.
Specifically, the IP core workflow is described as follows:
firstly, the Avalon-MM master device needs to initialize the IP core, complete serial port reset and open/close of a specified serial port through a global register, and complete configuration of baud rate and parity check bit of the serial port through serial port registers DLL, DLH and LCR.
(1) Read operation procedure (Avalon-MM master reads the IP core).
The IP core completes the following work:
a) receiving serial input data transmitted from the outside, converting the serial data into parallel data according to a set baud rate, and storing the parallel data into a serial port receiving register RHR;
b) when the serial port receiving register RHR stores data, the serial port generates an interrupt signal, and the interrupt signal is subjected to OR operation with interrupt signals generated by other serial ports to synthesize an interrupt signal UART _ Int _ p, and the interrupt signal UART _ Int _ p is output to the main equipment;
c) meanwhile, the interrupt generated by which serial port is written in the global register interrupt position register (UART _ INT0_ REG _ OFFSET);
d) the number of data stored in the RHR is written into the register COUNT;
e) after the serial port in the IP core receives the read operation signal of the serial port interrupt clearing register ISR, the clearing of the serial port interrupt of the path is realized.
The Avalon-MM master device does the following:
a) receiving an interrupt signal sent by the IP core;
b) reading the value of an interrupt position register (UART _ INT0_ REG _ OFFSET), judging which serial port generates interrupt, and jumping to an interrupt processing function inlet of the serial port;
c) reading the value of a serial port register ISR, wherein the fixed value is 0x04, and when the value is read, an interrupt clearing signal is generated inside the Avalon-MM IP core to clear the interrupt of the serial port;
d) reading the value of a serial port register COUNT to obtain the data number DataNum;
e) circularly reading the value in the register RHR according to the acquired data number DataNum until the reading is finished;
f) and the application program processes the read data.
(2) Write operation Process (Avalon-MM Master writes to the IP core)
The Avalon-MM master device does the following:
and circularly writing the data to be written into the IP core into the serial port register THR until the writing is finished.
The IP core completes the following work:
a) receiving parallel data written by the main Avalon-MM equipment, and storing the parallel data into a serial port sending register THR;
and reading out data from THR, converting the read-out parallel data into serial data at a set baud rate, adding a parity check bit, and sending out.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (8)
1. A multi-serial port IP core based on an Avalon-MM bus interface is designed by adopting a hardware description language Verilog and is characterized by comprising an ARM side communication interface unit, a storage unit and a serial data input and output interface unit;
the ARM side communication interface unit comprises an Avalon-MM bus interface module and an interrupt output interface module, the Avalon-MM bus interface module realizes data exchange from the ARM side to the FPGA side through a bus transfer interface, and the interrupt output interface module is used for outputting an interrupt signal to the ARM;
the serial data input and output interface unit comprises 8 serial ports and is used for realizing data interaction between external equipment and the storage unit;
the storage unit comprises 3 global registers and 8 register modules, and the 8 register modules respectively correspond to 8 serial ports of the serial data input and output interface unit; and the 3 global registers are respectively in communication connection with the 8 register modules through an FPGA internal bus.
2. The IP core of claim 1, wherein the Avalon-MM bus interface module comprises:
an Avalon-MM bus read enable signal interface PS2FPGA _ RD _ p;
an Avalon-MM bus write enable signal interface PS2FPGA _ WR _ p;
an Avalon-MM bus read valid signal interface ReadDataValid;
an Avalon-MM bus Data writing signal interface PS2FPGA _ WR _ Data;
and the Avalon-MM bus Data reading signal interface PS2FPGA _ RD _ Data.
3. The IP core according to claim 1, wherein the 3 global registers are a serial switch register, a serial reset register and an interrupt position register, respectively;
the serial port switch register is used for storing flag bits for marking the opening or closing of specified serial ports in the 8 serial ports;
the serial port reset register is used for storing functional data for resetting a specified serial port in the 8 serial ports;
and the interrupt position register is used for storing the serial port position generating the interrupt.
4. The IP core of claim 1, wherein each of the register modules comprises a serial receive register RHR, a serial transmit register THR, a low 8-bit parameter register DLL, a high 8-bit parameter register DLH, a check bit flag register LCR, an interrupt clear register ISR, and a data flag register COUNT.
5. The IP core of claim 4 wherein the serial port receive register RHR is a FIFO register with read-only access type, depth 256 and width 8 bits.
6. The IP core of claim 4, wherein the serial port transmission register THR is a FIFO register, and the access type is write only, depth is 1024, and width is 8 bits.
7. The IP core of claim 4 wherein the check bit flag register LCR is configured to flag the number of stop bits and the parity bits.
8. The IP core of claim 4 wherein the data flag register COUNT is used to mark the number of data buffered by the serial port receive register RHR.
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Cited By (1)
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