CN109783407A - A kind of device and method for realizing PC and video card bridge joint based on FPGA - Google Patents
A kind of device and method for realizing PC and video card bridge joint based on FPGA Download PDFInfo
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- CN109783407A CN109783407A CN201910032667.2A CN201910032667A CN109783407A CN 109783407 A CN109783407 A CN 109783407A CN 201910032667 A CN201910032667 A CN 201910032667A CN 109783407 A CN109783407 A CN 109783407A
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Abstract
The invention discloses a kind of device and methods that PC and video card bridge joint are realized based on FPGA.It includes PCIE EP module, PCIE RP module and the arm processor being integrated on a FPGA, PCIE EP module is for receiving the internal register of video card and the information of BAR and storage, for parsing PC to the transmission TLP of video card, the data of parsing are sent to PCIE RP module；PCIE RP module is used to carry out video card to be powered on and initialized and be allocated the BAR resource of video card, is used to analyze the received data and is packaged and is sent to video card；Arm processor is used to control PCIE RP module and obtains the information of video card internal register and BAR and be sent to PCIE EP module.The present invention can realize the function of EP and RC in the simulation of FPGA enterprising row information and Data Bridge simultaneously, have the advantages that not restricted to close limitation that source drives, versatile.
Description
Technical field
The invention belongs to electronic information technical fields, and in particular to a kind of device that PC and video card bridge joint are realized based on FPGA
And method.
Background technique
In display panel testing field, market needs a kind of portable miniaturization measuring device, need to only be inserted into video card
In equipment, video card can be controlled by equipment and export various vision signals, for measuring display panel.This test equipment needs
It is detached from PC, and by the way of based on the operation of embedded-type ARM system, it can just accomplish to minimize, it is integrated.
This measuring device is developed, software engineer needs the video driver that will be run on PC to be transplanted in ARM.And mesh
The dominant company of preceding whole world design video card (GPU), it is either tall and handsome to reach (NVIDIA) or AMD, the driving issued on PC
Program is entirely to close source, this decode software engineer can not to be transplanted in ARM.
Current each measuring device manufacturer to solve the above-mentioned problems, can only be by some open source tissues, as nouveau is issued
Open source video driver be transplanted on ARM, but this kind of driver is not that official, video card manufacturer issues, and be can be only done most
Basic function can not allow video card to carry out complicated 3D figure rendering, the work such as HD video rendering, therefore be unable to satisfy panel factory
Quotient's testing requirement growing day by day.
Summary of the invention
The object of the invention is to provide a kind of simple, effective base to solve deficiency existing for above-mentioned background technique
The device and method of PC and video card bridge joint are realized in FPGA, and perception is deposited less than FPGA when PC can be allowed to operate video card
In closing source video driver and can be grabbed by the FPGA of bottom to the every operation that video card carries out on PC.
The technical solution adopted by the present invention is that: a kind of device for realizing PC and video card bridge joint based on FPGA, including be integrated in
PCIE EP module on one FPGA, information and the storage of internal register and BAR for receiving video card, for by PC to
The transmission TLP of video card is parsed, and the data of parsing are sent to PCIE RP module；
PCIE RP module is used for for be powered on and initialized and be allocated the BAR resource of video card to video card
Received data are packaged according to the rule of video card power-up initializing and are sent to video card；
Arm processor, for controlling the information of PCIE RP module acquisition video card internal register and BAR and being sent to
PCIE EP module.
It further, further include DDR memory module, the data of parsing for being sent at ARM by the PCIE EP module
Device is managed, the arm processor is used to send received data to DDR memory module, and the DDR memory module is for storing number
According to.
Further, carried out data transmission between the PCIE EP module and PCIE RP module by AXI bus.
Further, the FPGA is equipped with the first PCIE interface and the 2nd PCIE interface, and the first PCIE interface is used
It is connect in PC, the 2nd PCIE interface with video card for connecting.
Further, the information of the video card internal register includes ID, manufacturer and the model of video card.
A method of realizing that PC and video card are bridged based on FPGA, including information simulation and Data Bridge, the information mould
Quasi- to simulate including video card simulation and PC, the video card simulation passes through the information realization for obtaining video card internal register and BAR, described
PC simulation PC simulation is by editing power-up initializing order and BAR resource allocation the order realization to video card；The data bridge
It connects including address conversion and read-write requests conversion, the address conversion is to be converted into PC the access of video card BAR to fixedly
The access of location, the read-write requests conversion is the read-write being converted into read-write enable signal of the PC to video card to FPGA internal bus
Enable signal.
The present invention can realize the function of EP and RC simultaneously, pass through the party in the enterprising row information simulation of FPGA and Data Bridge
Method can allow PC to perceive the presence less than FPGA completely, and just looking like is that video card is directly inserted on PC mainboard equally.In this way, on PC
The every operation that video card carries out can be grabbed by the FPGA of bottom by closing source video driver, it is only necessary to the binary system that will be grabbed
Data are supplied to software engineer, they can be developed on ARM chip with closed on PC it is powerful as the driving function of source
Embedded video driver.
The device of the invention and method have the advantages that the not restricted limitation for closing source driving, can be software by the method
The video driver that engineer develops the high quality based on any CPU and any operating system provides critical data stream information.
Bridging method of the invention be for PC it is transparent, can accomplish with insert with；And the method application without being limited thereto
Scene extends to any scene of related needs, versatile.
Detailed description of the invention
Fig. 1 is the schematic diagram of apparatus of the present invention.
Fig. 2 is the schematic diagram of the method for the present invention.
Specific embodiment
The following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments, convenient for this hair is well understood
It is bright, but they limiting the invention.
Since the interface of video card and PC is PCIE, so the technical solution of this discovery will abide by PCIBase
Specification Revision 3.0 is standardized.PC is the ROOT Complex of PCIE, and abbreviation RP, video card is PCIE
Endpoint, abbreviation EP.In order to bridge PC and video card, need FPGA (field-programmable gate array) it is internal realize simultaneously EP with
The function of RP.Wherein the EP of FPGA is used for and PC is communicated, and the RP of FPGA is used for and video card communication.Inside FPGA, benefit is needed
EP and RC are bridged with specific bus, thereby realize the intercommunication of data.
It since FPGA will realize the function of PCIE RC, is standardized according to PCIE, FPGA has to be responsible for powering on video card
Initialization and the work of BAR resource allocation, the work of this part when not bridging is that PC is completed in fact, needed after bridge joint by
FPGA is completed.Since this partial function is software action, so also needing to use the ARM inside FPGA, program is write to complete.
After FPGA realizes the repertoire characteristic of bridge and data association is errorless, so that it may which video card is installed on PC
Driver can see the relevant information of video card in the equipment manager of Windows after installing, and PC is then perceived completely
Presence less than FPGA.
Video is played on PC or draws 3D figure, then the driver on PC will issue a command to video card down and be regarded
The rendering of frequency and 3D figure, the instruction of this part can flow through FPGA, be grabbed and be stored in DDR by the logic inside FPGA.
In the data stored in DDR reading and Printing to File, so that it may give software engineer, be run for writing in ARM
Driver, realize function as driver on PC.
Based on the above principles, a kind of device that PC and video card bridge joint are realized based on FPGA of the present invention, as shown in Figure 1, including
The PCIE EP module being integrated on a FPGA, information and the storage of internal register and BAR for receiving video card, deposit
The information of device includes ID, manufacturer and the model of video card, for parsing PC to the transmission TLP of video card, by the data of parsing
PCIE RP module is sent to by AXI bus；
TLP packet is the transaction layer packet of PCIE protocol definition, and PCIE EP module needs to parse the class following content of TLP packet,
To carry out the conversion of TLP to AXI bus:
TLP Packet type, PCIE EP module identify that this TLP packet is to read MEM or write MEM, and reading and write request are converted
At the read-write enable signal of AXI bus.
TLP packet address, TLP packet carry the address information for the BAR to be written and read, and PCIE EP module parses this
Address is placed in the address wire of AXI bus
TLP bag data can be followed by behind address for the write request TLP packet that PC is sent and write data, PCIE EP module
Data will be write to extract, be placed on the data line of AXI bus.
It is enabled that the read-write that PC is initiated is transmitted from PCIE EP module to PCIE RP module direction, on AXI, address and data.
The data that video card is passed back to PC are transmitted from PCIE RP module to PCIE EP module direction, on AXI.
PCIE RP module is used for for be powered on and initialized and be allocated the BAR resource of video card to video card
Received data are packaged according to the rule of video card power-up initializing and are sent to video card；
Arm processor, for controlling the information of PCIE RP module acquisition video card internal register and BAR and being sent to
PCIE EP module.
In above scheme, for the ease of the every operation data that source video driver carries out video card of closing on PC are supplied to
Software engineer further includes DDR memory module, and the PCIE EP module is used to the data of parsing being sent to arm processor,
The arm processor is used to send DDR memory module for received data, and the DDR memory module is for storing data.PC
On close source video driver FPGA can be flowed through to the operation of video card, grabbed by the logic inside FPGA and be stored in DDR and deposit
Store up module.During data that DDR memory module is stored are read and are Printed to File, so that it may give software engineer, be used for
The driver run in ARM is write, realizes the function as driver on PC.
In above scheme, FPGA is equipped with the first PCIE interface and the 2nd PCIE interface, and the first PCIE interface is used for
It is connect with PC, the 2nd PCIE interface with video card for connecting.
Based on above-mentioned device, the present invention also provides a kind of methods for realizing PC and video card bridge joint based on FPGA, including letter
Breath simulation and Data Bridge, video card simulation specifically: read the register information in video card, this component register includes video card
These information are placed into the PCIE EP module of FPGA by ID, manufacturer, the key messages such as model, and such PC can recognize aobvious
The relevant information of card, and matched with the INF file of driving, so as to load relevant driver；It obtains inside video card
The information of BAR is passed through the BAR of PCIE RP module accesses video card using the arm processor inside FPGA, just can know that in video card
The information of portion BAR copies to these BAR information in the PCIE EP module of FPGA, and the operating system on such PC can give
These BAR distribute base address, to be mapped in the memory headroom of PC.PC simulation is handled specifically by the ARM inside FPGA
Device is programmed PCIE RP module, to realize power-up initializing and BAR resource allocation to video card.
Data Bridge includes that the conversion of PCIE TLP affairs and FPGA internal bus affairs are mutually converted.Conversion process includes ground
Location conversion and read-write requests conversion.The principle of address conversion is the visit being converted into PC to the access of video card BAR to fixing address
It asks, read-write requests conversion is that read-write enable signal of the PC to video card is converted into the read-write to FPGA internal bus (AXI) to enable
Signal.Correct base address is written in BAR according to address above mentioned transformation rule to video card, thus can be PC to FPGA EP's
BAR operation is converted into FPGA RP and operates to the BAR of video card.
Address conversion is described in detail:
Such as when power-up initializing, PC is 0x00000000, PCIE to the BAR0 initialization base address of PCIE EP module
RP module is 0x20000000 to video card BAR0 initialization base address.Present PC wants the deposit inside the BAR0 of read-write video card
Device, it is assumed that offset address 0x0000000a.
Whole process is as follows:
The address carried in the TLP packet that PC is issued is 0x0000000a, this address can hit PCIE EP module
After BAR0, PCIE EP module receive this packet, address will be parsed, and be placed into AXI bus.PCIE RP module can handle
Address 0x0000000a on AXI is converted into 0x2000000a, and is packaged into TLP packet again and is sent to video card.In this way, just
The BAR0 of video card can be finally hit, to access to video card.
The content being not described in detail in this specification belongs to the prior art well known to professional and technical personnel in the field.
Claims (6)
1. a kind of device for realizing PC and video card bridge joint based on FPGA, it is characterised in that: including being integrated on a FPGA
PCIE EP module, information and the storage of internal register and BAR for receiving video card, for the hair by PC to video card
It send TLP to be parsed, the data of parsing is sent to PCIE RP module；
PCIE RP module is used for basis for be powered on and initialized and be allocated the BAR resource of video card to video card
The rule of video card power-up initializing is packaged received data and is sent to video card；
Arm processor, for controlling the information of PCIE RP module acquisition video card internal register and BAR and being sent to PCIE EP
Module.
2. the device according to claim 1 for realizing PC and video card bridge joint based on FPGA, it is characterised in that: further include DDR
Memory module, the PCIE EP module are used to for the data of parsing being sent to arm processor, and the arm processor will be for that will connect
The data of receipts are sent to DDR memory module, and the DDR memory module is for storing data.
3. the device according to claim 1 for realizing PC and video card bridge joint based on FPGA, it is characterised in that: the PCIE
Carried out data transmission between EP module and PCIE RP module by AXI bus.
4. the device according to claim 1 for realizing PC and video card bridge joint based on FPGA, it is characterised in that: on the FPGA
Equipped with the first PCIE interface and the 2nd PCIE interface, the first PCIE interface with PC for connecting, the 2nd PCIE interface
For being connect with video card.
5. the device according to claim 1 for realizing PC and video card bridge joint based on FPGA, it is characterised in that: in the video card
The information of portion's register includes ID, manufacturer and the model of video card.
6. a kind of method for realizing PC and video card bridge joint based on FPGA, it is characterised in that: including information simulation and Data Bridge, institute
Stating information simulation includes video card simulation and PC simulation, and the video card simulation passes through the information for obtaining video card internal register and BAR
It realizes, the PC simulation PC simulation is by editing power-up initializing order and BAR resource allocation the order realization to video card；Institute
Stating Data Bridge includes address conversion and read-write requests conversion, and the address conversion is to be converted into PC to the access of video card BAR
Access to fixing address, read-write requests conversion be read-write enable signal of the PC to video card is converted into it is total to the inside FPGA
The read-write enable signal of line.
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| CN201910032667.2A CN109783407B (en) | 2019-01-14 | 2019-01-14 | Device and method for realizing PC and display card bridging based on FPGA |
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| CN201910032667.2A CN109783407B (en) | 2019-01-14 | 2019-01-14 | Device and method for realizing PC and display card bridging based on FPGA |
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| CN109783407B (en) | 2021-01-12 |
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