CN109782578A - A kind of high reliability deep-sea autonomous underwater vehicle control method - Google Patents

A kind of high reliability deep-sea autonomous underwater vehicle control method Download PDF

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Publication number
CN109782578A
CN109782578A CN201811582167.8A CN201811582167A CN109782578A CN 109782578 A CN109782578 A CN 109782578A CN 201811582167 A CN201811582167 A CN 201811582167A CN 109782578 A CN109782578 A CN 109782578A
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China
Prior art keywords
cpu
bus
control
host cpu
backup
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Pending
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CN201811582167.8A
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Chinese (zh)
Inventor
向伟
冯朝
胡庆玉
席晓犇
张建军
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China Shipbuilding Industry Corp 71 0 Research Institute
710th Research Institute of CSIC
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China Shipbuilding Industry Corp 71 0 Research Institute
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Priority to CN201811582167.8A priority Critical patent/CN109782578A/en
Publication of CN109782578A publication Critical patent/CN109782578A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a kind of high reliability deep-sea autonomous underwater vehicle control methods, and the high reliability deep-sea autonomous underwater vehicle control system of dual processors warm back-up is realized based on National Federation of Trade Unions's wire type control system framework, continuously control in real time when realizing CPU switching.Dual processors warm back-up is realized by using National Federation of Trade Unions's wire type control system framework, is overcome in existing double CPU for redundant AUV control system, and work CPU and backup CPU cannot achieve the deficiency of continuous real-time control when switching, improve the global reliability of AUV control system conscientiously.

Description

A kind of high reliability deep-sea autonomous underwater vehicle control method
Technical field
The present invention relates to autonomous underwater vehicle control technology fields, and in particular to a kind of high reliability deep-sea is autonomous under water Aircraft control method.
Background technique
When autonomous underwater vehicle (AUV) executes task under water, the most of the time is in AUTONOMOUS TASK state.Certainly Under major state, the control of autonomous underwater vehicle transfers to its control system to take over completely.Thus, as core group parts, under water The reliability of autonomous navigation device control system often decides the success or failure of entire autonomous underwater vehicle job task.Especially exist When needing to be implemented remote independent navigation job task, the reliability requirement of control system is just more harsh.And for control system Core --- for CPU and its peripheral components, design level and manufacturing process determine that its reliability and service life can not It can infinitely be promoted.For this purpose, in the case where existing individual devices reliability is unable to satisfy reliability control system demand, it is necessary to It, can for control system to meet autonomous underwater vehicle by system level solution come Lifting Control System global reliability By the requirement of property.
Currently, the method that the autonomous underwater vehicle control system of high reliability mostly uses greatly double CPU for redundant cold standby, i.e., When one CPU is worked normally, the state of spare CPU monitoring CPU and unsynchronized revolution, when detecting that work CPU occurs The just control of adapter tube whole system when abnormal.The difference of program is executed due to two CPU under this mode and information is grasped The factors such as asymmetry, the continuity of the real-time and control switching that necessarily lead to control system not can guarantee.In addition, part Collision avoidance mechanism is not formed also because its control system interface is various using the method for dual processors synchronous operation warm back-up The factors such as perfect bus architecture lead to not realize the seamless switching between dual processors.It can not achieve the double of continuous real-time control CPU redundancy, there is no the global reliabilities for truly improving autonomous underwater vehicle control system.
Summary of the invention
In view of this, being based on National Federation of Trade Unions the present invention provides a kind of high reliability deep-sea autonomous underwater vehicle control method Wire type control system framework realizes the high reliability deep-sea autonomous underwater vehicle control system of dual processors warm back-up, realizes CPU It is continuously controlled in real time when switching.
A kind of high reliability deep-sea autonomous underwater vehicle control method provided by the invention, this method are applicable in underwater Autonomous navigation device control system includes host CPU portion, the portion backup CPU, power module portion and adaptive ethernet interchanger, specific work Make process the following steps are included:
After step 1.1, the control system power on, controls default host CPU portion first by the power module and power on, be delayed After a period of time, starting is completed to host CPU portion, bus control right is obtained and starts to execute autonomous control program and bus monitoring journey After sequence, then controls the default portion backup CPU and power on;
Step 1.2, the portion backup CPU start operation after powering on, and execute bus monitoring program, certainly with the synchronous operation of host CPU portion Master control program, but instruction and status information are not sent to bus;
After step 1.3, the portion CPU to be backed up complete start-up course, host CPU portion powers on fortune by bus marco external equipment Row;
Step 1.4 actively discharges bus control right when host CPU portion monitors itself exception, when the portion backup CPU monitors Bus control right is then obtained when host CPU portion exception.
Further, the process that bus control right is obtained in the step 1.4, includes the following steps:
Step 2.1, the portion backup CPU judge whether bus is idle, show that host CPU portion does not work normally if bus free, The portion this CPU is then switched to host CPU portion operating mode, executes bus monitoring program and autonomous control program, according to the control period, Instruction or status frames are sent to bus;If bus is not idle, show that host CPU portion is in host CPU portion operating mode, and run just Often, then the portion this CPU maintains the portion backup CPU operating mode, executes bus monitoring program and autonomous control program, but does not send out to bus Send instruction and data;
Step 2.2, etc. the period to be controlled, circulation execute step 2.1.
Further, the power module portion using 18DC-36VDC lithium battery group power, and for the portion CPU output through every From with the 24VDC power supply after voltage transformation.
The utility model has the advantages that
The present invention realizes dual processors warm back-up by using National Federation of Trade Unions's wire type control system framework, overcomes existing double CPU for redundant In AUV control system, work CPU and backup CPU cannot achieve the deficiency of continuous real-time control when switching, and improve AUV control conscientiously The global reliability of system processed.
Detailed description of the invention
Fig. 1 is autonomous underwater vehicle control method schematic diagram in high reliability deep-sea provided by the invention.
Fig. 2 is high reliability deep-sea autonomous underwater vehicle control method flow chart provided by the invention.
Fig. 3 is the software flow that CPU is executed in high reliability deep-sea autonomous underwater vehicle control method provided by the invention Cheng Tu.
Specific embodiment
The present invention will now be described in detail with reference to the accompanying drawings and examples.
The basic idea of the invention is that: the high reliability of dual processors warm back-up is realized based on National Federation of Trade Unions's wire type control system framework Deep-sea autonomous underwater vehicle control system is successively powered on by controlling consistent two CPU of software and hardware configuration, first powers on and be Host CPU portion, after to power on be the portion backup CPU, each motor synchronizing execution autonomous control program in host CPU portion and the portion backup CPU, and to total Line is monitored, and to judge whether another CPU is in normal working condition, bus control right is obtained if operation irregularity, So that it is guaranteed that the high reliability of deep-sea autonomous underwater vehicle operation.
A kind of high reliability deep-sea autonomous underwater vehicle control method provided by the invention, this method are applicable in underwater Autonomous navigation device control system includes host CPU portion, the portion backup CPU, power module portion and adaptive ethernet interchanger, such as Fig. 1 It is shown.
Host CPU portion, including core cpu processor, host CPU portion memory on board, cpu clock, watchdog circuit, CAN bus Interface, industry ethernet interface and real time operating system and application program.
The portion backup CPU, including core cpu processor, the portion backup CPU memory on board, cpu clock, watchdog circuit, CAN Bus interface, industry ethernet interface and real time operating system and application program.
Wherein, host CPU portion is identical with backup CPU portion's hardware and software section, to guarantee entire AUV control system fortune Host CPU is synchronous within the control period with backup CPU autonomous control software implementing result during row.Simultaneously as the two is hard Part and software have interchangeability, then can be mutually backups both in entire control system actual moving process, i.e., as any CPU Another CPU can real-time seamless pipe bus when occurring abnormal.Pass through CAN bus and ether between host CPU portion and the portion backup CPU Network interface is connected.
Power module includes electrifying timing sequence control module and DC-DC isolated power supply module, wherein electrifying timing sequence control module For controlling two CPU time-sharing powers.
Host CPU in the autonomous underwater vehicle control system of high reliability deep-sea and backup CPU pass through CAN interface or Ethernet interface is connect with all external equipments, the communication with all external equipments and the control to external equipment is realized, to logical Letter requirement of real-time is high and the relatively small external equipment of data volume mostly uses greatly CAN interface, and amount of communication data is big or real When property external equipment of less demanding mostly uses greatly Ethernet interface.All CAN interface external equipments pass through high reliability The external CAN interface of deep-sea AUV control system and host CPU portion and the portion backup CPU interconnect.It is set outside all Ethernet interfaces The standby Ethernet switch portion external interface by high reliability deep-sea AUV control system is realized and host CPU portion and the portion backup CPU Ethernet interface interconnection, and it is inside Ethernet switch that all Ethernet interface input and output ports being connected with peripheral hardware are equal The P2 mouth for being mirrored to the P1 mouth being connected with host CPU portion and being connected with the portion backup CPU, host CPU portion and standby when ensuring system operation The processor in the portion part CPU can monitor identical external device data from Ethernet interface.
A kind of high reliability deep-sea autonomous underwater vehicle control method provided by the invention, workflow as shown in Fig. 2, Include the following steps:
After step 1.1, high reliability deep-sea AUV control system power on, by power module portion host CPU, on backup CPU Electric time-sequence control module gives the host CPU portion of default to power on first, then delay a period of time, to host CPU portion start completion, obtains Bus control right simultaneously starts to execute autonomous control program with after synchronous execution bus monitoring program, powers on to the default portion backup CPU. Wherein, can be selected meet 18DC-36VDC lithium battery group be power module portion power, power module to the portion CPU export through isolation with 24VDC power supply after voltage transformation.
Step 1.2, the portion backup CPU start operation after powering on, and monitor bus data, run simultaneously with host CPU portion from master control Processing procedure sequence, but instruction and status information are not sent to bus.
After step 1.3, the portion CPU to be backed up complete start-up course, host CPU portion is powered on by bus marco external equipment, whole A AUV control system starts to operate normally, until system cut-off.
In step 1.4, system operation, host CPU and backup the CPU synchronous circulating when executing autonomous control program are executed Bus monitoring program actively discharges bus control right when monitoring itself exception, monitors to obtain bus when another CPU exception The processor in control, i.e. host CPU portion and the portion backup CPU can realize that the real-time automatic seamless under redundancy backup state switches.
To guarantee that the portion active and standby part CPU software can be run simultaneously, software flow performed by the two is completely the same, such as Fig. 3 It is shown, include the following steps:
After step 2.1, CPU are powered on, boot loader is executed, and continues to monitor 1 control cycle time of bus.
Step 2.2 judges whether bus is idle, shows that another CPU is not worked normally if bus free, incite somebody to action this at this time CPU is switched to host CPU operating mode, begins listening for bus data, executes autonomous control program, and obtain bus control right, presses According to the control period, according to control program implementing result, instruction or status frames are sent to bus;If bus is not idle, show another One CPU is in host CPU operating mode, and normal operation, this CPU is switched to backup CPU operating mode at this time, monitors number of buses According to, execution control program, but instruction and data is not sent to bus.
Step 2.3, etc. the period to be controlled, circulation execute step 2.2.
In conclusion the above is merely preferred embodiments of the present invention, being not intended to limit the scope of the present invention. All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should be included in of the invention Within protection scope.

Claims (3)

1. a kind of high reliability deep-sea autonomous underwater vehicle control method, the autonomous underwater vehicle control that this method is applicable in System includes host CPU portion, the portion backup CPU, power module portion and adaptive ethernet interchanger, which is characterized in that specific works Process the following steps are included:
After step 1.1, the control system power on, controls default host CPU portion first by the power module and power on, be delayed one section After time, starting is completed to host CPU portion, bus control right is obtained and starts to execute autonomous control program and bus monitoring program Afterwards, then control default the portion backup CPU power on;
Step 1.2, the portion backup CPU start operation after powering on, and execute bus monitoring program, run simultaneously with host CPU portion from master control Processing procedure sequence, but instruction and status information are not sent to bus;
After step 1.3, the portion CPU to be backed up complete start-up course, host CPU portion passes through electricity operation on bus marco external equipment;
Step 1.4 actively discharges bus control right when host CPU portion monitors itself exception, when the portion backup CPU monitors to lead Bus control right is then obtained when the portion CPU exception.
2. control method according to claim 1, which is characterized in that obtain the mistake of bus control right in the step 1.4 Journey includes the following steps:
Step 2.1, the portion backup CPU judge whether bus is idle, show that host CPU portion does not work normally if bus free, will The portion this CPU is switched to host CPU portion operating mode, executes bus monitoring program and autonomous control program, according to the control period, to total Line sends instruction or status frames;If bus is not idle, show that host CPU portion is in host CPU portion operating mode, and normal operation, Then the portion this CPU maintains the portion backup CPU operating mode, executes bus monitoring program and autonomous control program, but does not send to bus Instruction and data;
Step 2.2, etc. the period to be controlled, circulation execute step 2.1.
3. control method according to claim 1, which is characterized in that the power module portion is using 18DC-36VDC lithium electricity The power supply of pond group, and be isolated and the 24VDC power supply after voltage transformation for the output of the portion CPU.
CN201811582167.8A 2018-12-24 2018-12-24 A kind of high reliability deep-sea autonomous underwater vehicle control method Pending CN109782578A (en)

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Application publication date: 20190521