CN109761190A - The method for forming alignment mark - Google Patents
The method for forming alignment mark Download PDFInfo
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- CN109761190A CN109761190A CN201910058762.XA CN201910058762A CN109761190A CN 109761190 A CN109761190 A CN 109761190A CN 201910058762 A CN201910058762 A CN 201910058762A CN 109761190 A CN109761190 A CN 109761190A
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- connecting column
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- oxide
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Abstract
The present invention provides a kind of methods for forming alignment mark, comprising: multiple first metal connecting columns and at least one second metal connecting column are formed on the substrate；Form the patterned oxide skin(coating) of the first alignment area and the patterned oxide skin(coating) of the second alignment area and the first oxide connecting column；The third metal connecting column being located on the first oxide connecting column and the 4th metal connecting column on the oxide skin(coating) of the second alignment area are formed, the ratio of upper surface to the spacing between the distance and adjacent third metal connecting column on the surface of the patterned oxide skin(coating) of the first alignment area of third metal connecting column is greater than 1:1；The second oxide skin(coating) is formed on patterned oxide skin(coating), third metal connecting column and the 4th connecting column, the second oxide layer surface forms groove as alignment mark.Compared with the existing technology, the application directly forms alignment mark while forming MEMS and CMOS interconnection layer, can save material and time.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of methods for forming alignment mark.
Background technique
CMOS is a part for forming digital circuit, and MEMS (MEMS) is to melt microelectric technique and mechanical engineering
A kind of industrial technology being combined together, its opereating specification is in micron range, nowadays, utilizes the anisotropic magnetoresistive of FeNi
(AMR) MEMS (AMR MEMS) of effect manufacture has high sensitivity, and thermal stability is good, and the cost of material is low, preparation process
Simply, it has been obtained and is widely applied, nowadays possible MEMS and CMOS can be combined, therefore be related to the mutual of MEMS and CMOS
Even, it interconnects and requires alignment mark as auxiliary.
In the prior art, there are two types of the alignment mark that method forms MEMS and CMOS interconnection, first method is that CMOS is certainly
Status is multilayer, and each layer has alignment mark, if MEMS device is formed in the plane of CMOS, and MEMS device need and
CMOS alignment, it is necessary to which additionally newly-increased one layer of through-hole and one layer of metal are connected with the alignment mark of itself, and simultaneously in newly-increased gold
Belong to layer and forms MEMS alignment mark.Second method is, directly the opening surface CMOS, expose CMOS it is original itself to fiducial mark
Note, MEMS will be using this alignment marks as the interconnection referring to the device and CMOS top-level metallic for realizing itself.
But in the first method of the prior art, need additionally to increase one layer of through-hole and one layer of metal newly, and be formed simultaneously
The alignment mark of subsequent level needs in second method newly-increased one not etch level, opens the alignment mark of CMOS, and this
Two methods require additional technique and form MEMS and CMOS interconnection alignment mark, cost of idleness and time.
Summary of the invention
The purpose of the present invention is to provide a kind of method for forming alignment mark, do not need additional technique formed MEMS and
CMOS interconnects alignment mark, saves cost and time.
In order to achieve the above object, the present invention provides a kind of methods for forming alignment mark, comprising:
One substrate is provided；
The first metal layer is formed over the substrate, is etched the first metal layer and is formed patterned the first metal layer,
The patterned the first metal layer includes the first alignment area and the second alignment area, and first alignment area includes multiple first gold medals
Belong to connecting column, second alignment area includes at least one second metal connecting column；
The first oxide skin(coating) is formed on the patterned the first metal layer, is etched first oxide skin(coating) and is formed figure
The oxide skin(coating) of case, the patterned oxide layer include the first metal connecting column interval in the first alignment area of removal
First oxide skin(coating), the first oxide connecting column on the first metal connecting column, and the second alignment area first of covering
First oxide skin(coating) of oxide skin(coating), etching the second alignment area of covering exposes the second metal connecting column, and it is logical to form multiple first
Hole；
Form second metal layer on the patterned oxide skin(coating), etch the second metal layer formed it is patterned
Second metal layer, the patterned second metal layer include removing the second metal layer at the first oxide connecting column interval,
On the third metal connecting column formed on first oxide connecting column, and removal second the first oxide skin(coating) of alignment area of covering
Part second metal layer, retain the 4th metal connecting column with the second metal connecting column corresponding position of the second alignment area, institute
State the upper surface of third metal connecting column to the first alignment area patterned oxide skin(coating) surface distance and adjacent institute
The ratio for stating the spacing between the left metal connecting column of third is greater than 1:1；
The second oxidation is formed on the patterned second metal layer, third metal connecting column and the 4th metal connecting column
Nitride layer, on the second oxide skin(coating) of third metal connecting column spacer region corresponding position formed groove as device to fiducial mark
Note；
Second oxide layer is etched to expose the 4th metal connecting column, forms the second through-hole, using as device
The through-hole of interconnection.
Optionally, in the method for the described formation alignment mark, the substrate is cmos device, in the cmos device
Containing contact hole, the first metal connecting column is located on the contact hole.
Optionally, in the method for the formation alignment mark, the patterned oxide skin(coating) of first alignment area
Thickness be less than the first metal connecting column height.
Optionally, in the method for the formation alignment mark, the first metal connecting column, first oxide
The shape and width of connecting column and the third metal connecting column are all the same.
Optionally, in the method for the formation alignment mark, the patterned oxide skin(coating) of second alignment area
Height it is identical as the sum of the height of the first metal connecting column and the second oxide connecting column.
Optionally, in the method for the formation alignment mark, after forming multiple first through hole, the formation alignment
The method of label further includes filling metal into the first through hole.
Optionally, in the method for the formation alignment mark, the alignment mark corresponds to downwards two adjacent institutes
State the middle position of third metal connecting column.
Optionally, in the method for the formation alignment mark, the lithographic method is all dry etching.
Optionally, in the method for the described formation alignment mark, the first metal layer and the second metal layer
Material includes aluminium.
Optionally, in the method for the formation alignment mark, first oxide layer and second oxide skin(coating)
Material include silica.
In the method provided by the invention for forming alignment mark, relative to prior technique one, the application can subtract
Few metal layer and metal contact hole layer, and relative to prior technique two, the application also can be reduced a layer open CMOS itself
Alignment mark, also, relative to prior technique one and relative to prior technique two, the application is directly being formed
Alignment mark is formed while MEMS and CMOS interconnection layer, material and time can be saved.
Detailed description of the invention
Fig. 1 is the flow chart for the method that the embodiment of the present invention forms alignment mark；
Fig. 2 to Fig. 8 is the structural schematic diagram for the method that the embodiment of the present invention forms alignment mark；
In figure: the first metal of 110- connecting column, the first metal of 111- connecting column, the second metal of 112- connecting column, 120- figure
The patterned oxidation of the oxide skin(coating) of case, the patterned oxide skin(coating) of the first alignment area of 121-, the second alignment area of 122-
Nitride layer, the first oxide of 130- connecting column, 140- first through hole, 150- second metal layer, 161- third metal connecting column, 162-
4th metal connecting column, the second oxide skin(coating) of 170-, 180- groove, the second through-hole of 190-, 200-MEMS device.
Specific embodiment
A specific embodiment of the invention is described in more detail below in conjunction with schematic diagram.According to following description and
Claims, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and
Using non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Referring to Fig.1, a method of forming alignment mark, comprising:
S11: a substrate is provided；
S12: forming the first metal layer over the substrate, etches the first metal layer and forms patterned first metal
Layer, the patterned the first metal layer include the first alignment area and the second alignment area, and first alignment area includes multiple the
One metal connecting column, second alignment area include at least one second metal connecting column；
S13: forming the first oxide skin(coating) on the patterned the first metal layer, etches the first oxide skin(coating) shape
At patterned oxide skin(coating), the patterned oxide layer includes the first metal connection intercolumniation in the first alignment area of removal
Every the first oxide skin(coating), the first oxide connecting column on the first metal connecting column, and the second alignment area of covering
First oxide skin(coating) of the first oxide skin(coating), etching the second alignment area of covering exposes the second metal connecting column, forms multiple the
One through-hole；
S14: forming second metal layer on the patterned oxide skin(coating), etches the second metal layer and forms pattern
The second metal layer of change, the patterned second metal layer include the second metal for removing the first oxide connecting column interval
Layer, the third metal connecting column formed on the first oxide connecting column, and removal second the first oxide of alignment area of covering
Part second metal layer on layer, reservation are connect with the 4th metal of the second metal connecting column corresponding position of the second alignment area
Column, the distance on the surface of the patterned oxide skin(coating) of the upper surface of the third metal connecting column to the first alignment area with it is adjacent
The left metal connecting column of the third between spacing ratio be greater than 1:1；
S15: second is formed on the patterned second metal layer, third metal connecting column and the 4th metal connecting column
Oxide skin(coating) is aligned with formation groove on the second oxide skin(coating) of third metal connecting column spacer region corresponding position as device
Label；
S16: etching second oxide layer forms the second through-hole to expose the 4th metal connecting column, using as
The through-hole of device interconnection.
Firstly, referring to figure 2., providing a substrate, the substrate is a cmos device, is connect in cmos device comprising multiple
The first metal layer is formed on the substrate in contact hole, and metal can select aluminium, and then etching first metal layer forms multiple first metals and connects
Connect column 111 and at least one second metal connecting column 112, the first metal connecting column 111 and the second metal connecting column 112 are by pattern
The first metal layer of change is divided into the first alignment area and the second alignment area.In the present embodiment, 3 the first metals positioned at left side are connected
Column 111 is used to form the subsequent alignment mark being aligned for CMOS and MEMS, this 3 the first metal connecting columns 111 are formed in
On the contact hole of CMOS.The second metal connecting column 112 positioned at right side is interconnected for subsequent CMOS and MEMS.
Then, referring to figure 3. and Fig. 4, on the first metal connecting column 111, the second metal connecting column 112 and the substrate
The first oxide skin(coating) is formed, the first oxide skin(coating) is etched, removes the part at the first metal connecting column interval in the first alignment area
First oxide skin(coating) forms the first oxide connecting column 130 being located on the first metal connecting column 111, and the first oxide
The shape and equivalent width of connecting column 130 and the first metal connecting column 111.Meanwhile etching the first oxide of the second alignment area
Layer forms multiple first through hole 140, and fills metal into first through hole 140, for example, filling aluminum.Wherein, the first alignment area
121 thickness of patterned oxide skin(coating) be lower than the first metal connecting column 111 thickness, second alignment area it is patterned
The upper surface of oxide skin(coating) 122 is aligned with the upper surface of the first oxide connecting column 130.
Then, referring to figure 4. and Fig. 5, depositing second metal layer 150 etches second metal layer 150, forms third metal
Connecting column 161 and the 4th metal connecting column 162, third metal connecting column 161 are aligned with the first oxide connecting column 130, and
Shape and width and the first oxide connecting column 130 are consistent, and the 4th metal connecting column 162 is located at 140 top of first through hole and the
The alignment of two metal connecting columns 112 and shape and width can be consistent with the second metal connecting column 112.In entire technical process,
The upper surface of third metal connecting column 161 is to the distance on 121 surface of patterned oxide skin(coating) of the first alignment area and adjacent
The ratio of the distance between third metal connecting column 161 is greater than 1:1.
Then, Fig. 6, depositing second oxide layer 170, covering third metal connecting column 161, the connection of the 4th metal are please referred to
Column 162 and patterned oxide skin(coating) 120, the surface of the second oxide skin(coating) 170 correspond to downwards between third metal connecting column 161
Septal area is formed with multiple cavities, forms groove 180, finally, entire second oxide skin(coating), 170 surface using chemical mechanical grinding
It will form multiple grooves 180, the alignment mark that multiple grooves 180 can be used for when subsequent MEMS and CMOS is aligned.Compared to existing
Technology, the present invention form the alignment mark of interconnection, reduce and be additionally formed alignment while making MEMS and CMOS interconnection layer
The technique of label, saves time and cost.
Then, please refer to Fig. 7 and Fig. 8, MEMS device 200 be will with a part of the CMOS MEMS device interconnected, with
Second oxide skin(coating), 170 surface fitting, using groove 180 as alignment mark.By the second oxidation on the 4th metal connecting column 162
Nitride layer 170 excavates to form the second through-hole 190 using dry etching, to realize the interconnection of cmos device and MEMS device.
In an embodiment of the present invention, lithographic method can use dry etching, the first oxide skin(coating) and the second oxidation
Nitride layer can selective oxidation silicon, the first metal layer and second metal layer can select aluminum to make.
To sum up, in the method provided in an embodiment of the present invention for forming alignment mark, relative to prior technique one, this
Application can reduce lithium metal layer and lithium metal contact hole, moreover it is possible to the alignment mark for using two layers of CMOS itself is reduced, and it is opposite
In art methods two, the application also can be reduced the alignment mark of one layer of CMOS itself, also, relative to prior technique
One and relative to prior technique two, the application directly forms alignment mark while forming MEMS and CMOS interconnection layer,
Material and time can be saved.
The above is only a preferred embodiment of the present invention, does not play the role of any restrictions to the present invention.Belonging to any
Those skilled in the art, in the range of not departing from technical solution of the present invention, to the invention discloses technical solution and
Technology contents make the variation such as any type of equivalent replacement or modification, belong to the content without departing from technical solution of the present invention, still
Within belonging to the scope of protection of the present invention.
Claims (10)
1. a kind of method for forming alignment mark characterized by comprising
One substrate is provided；
The first metal layer is formed over the substrate, is etched the first metal layer and is formed patterned the first metal layer, it is described
Patterned the first metal layer includes the first alignment area and the second alignment area, and first alignment area includes that multiple first metals connect
Column is connect, second alignment area includes at least one second metal connecting column；
The first oxide skin(coating) is formed on the patterned the first metal layer, is etched first oxide skin(coating) and is formed patterning
Oxide skin(coating), the patterned oxide layer include remove the first alignment area in the first metal connecting column interval first
Oxide skin(coating), the first oxide connecting column on the first metal connecting column, and covering the second alignment area first oxidation
First oxide skin(coating) of nitride layer, etching the second alignment area of covering exposes the second metal connecting column, forms multiple first through hole；
Second metal layer is formed on the patterned oxide skin(coating), the second metal layer is etched and forms patterned second
Metal layer, the patterned second metal layer includes removing the second metal layer at the first oxide connecting column interval, first
Portion on the third metal connecting column formed on oxide connecting column, and removal second the first oxide skin(coating) of alignment area of covering
Point second metal layer, retains the 4th metal connecting column with the second metal connecting column corresponding position of the second alignment area, and described the
The upper surface of three metal connecting columns to the first alignment area patterned oxide skin(coating) surface distance and adjacent described the
The ratio of spacing between three left metal connecting columns is greater than 1:1；
The second oxide is formed on the patterned second metal layer, third metal connecting column and the 4th metal connecting column
Layer, on the second oxide skin(coating) of third metal connecting column spacer region corresponding position formed groove as device alignment mark；
Second oxide layer is etched to expose the 4th metal connecting column, forms the second through-hole, using as device interconnection
Through-hole.
2. forming the method for alignment mark as described in claim 1, which is characterized in that the substrate is cmos device, described
Contain contact hole in cmos device, the first metal connecting column is located on the contact hole.
3. as described in claim 1 formed alignment mark method, which is characterized in that first alignment area it is patterned
The thickness of oxide skin(coating) is less than the height of the first metal connecting column.
4. forming the method for alignment mark as described in claim 1, which is characterized in that the first metal connecting column, described
The shape and width of first oxide connecting column and the third metal connecting column are all the same.
5. as described in claim 1 formed alignment mark method, which is characterized in that second alignment area it is patterned
The height of oxide skin(coating) is identical as the sum of the height of the first metal connecting column and the second oxide connecting column.
6. forming the method for alignment mark as described in claim 1, which is characterized in that after forming multiple first through hole, institute
Stating the method to form alignment mark further includes filling metal into the first through hole.
7. forming the method for alignment mark as described in claim 1, which is characterized in that the alignment mark corresponds to downwards adjacent
Two third metal connecting columns middle position.
8. forming the method for alignment mark as described in claim 1, which is characterized in that the lithographic method is all that dry method is carved
Erosion.
9. forming the method for alignment mark as described in claim 1, which is characterized in that the first metal layer and described second
The material of metal layer includes aluminium.
10. forming the method for alignment mark as described in claim 1, which is characterized in that first oxide layer and described the
The material of dioxide layer includes silica.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910058762.XA CN109761190B (en) | 2019-01-22 | 2019-01-22 | Method for forming alignment mark |
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| CN201910058762.XA CN109761190B (en) | 2019-01-22 | 2019-01-22 | Method for forming alignment mark |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766200A (en) * | 1993-08-24 | 1995-03-10 | Fujitsu Ltd | Fabrication of semiconductor device |
| US20050255666A1 (en) * | 2004-05-11 | 2005-11-17 | Miradia Inc. | Method and structure for aligning mechanical based device to integrated circuits |
| KR20080019922A (en) * | 2006-08-29 | 2008-03-05 | 동부일렉트로닉스 주식회사 | The semiconductor device and the manufacturing method thereof |
| CN103578968A (en) * | 2012-08-03 | 2014-02-12 | 上海华虹Nec电子有限公司 | Structure of comprehensive type silicon epitaxy process photoetching alignment mark and manufacturing method |
| CN104882436A (en) * | 2015-03-31 | 2015-09-02 | 上海华虹宏力半导体制造有限公司 | Preparation method for lithography alignment mark in two epitaxial processes |
| CN105645347A (en) * | 2014-11-18 | 2016-06-08 | 无锡华润上华半导体有限公司 | Locating method for bulk silicon micromachining process |
-
2019
- 2019-01-22 CN CN201910058762.XA patent/CN109761190B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766200A (en) * | 1993-08-24 | 1995-03-10 | Fujitsu Ltd | Fabrication of semiconductor device |
| US20050255666A1 (en) * | 2004-05-11 | 2005-11-17 | Miradia Inc. | Method and structure for aligning mechanical based device to integrated circuits |
| KR20080019922A (en) * | 2006-08-29 | 2008-03-05 | 동부일렉트로닉스 주식회사 | The semiconductor device and the manufacturing method thereof |
| CN103578968A (en) * | 2012-08-03 | 2014-02-12 | 上海华虹Nec电子有限公司 | Structure of comprehensive type silicon epitaxy process photoetching alignment mark and manufacturing method |
| CN105645347A (en) * | 2014-11-18 | 2016-06-08 | 无锡华润上华半导体有限公司 | Locating method for bulk silicon micromachining process |
| CN104882436A (en) * | 2015-03-31 | 2015-09-02 | 上海华虹宏力半导体制造有限公司 | Preparation method for lithography alignment mark in two epitaxial processes |
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