CN109754745B - Display panel driving method and display device - Google Patents
Display panel driving method and display device Download PDFInfo
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- CN109754745B CN109754745B CN201910231212.3A CN201910231212A CN109754745B CN 109754745 B CN109754745 B CN 109754745B CN 201910231212 A CN201910231212 A CN 201910231212A CN 109754745 B CN109754745 B CN 109754745B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The invention provides a driving method of a display panel, the display panel comprises a plurality of pixel units which are arranged in a plurality of rows and a plurality of columns, for any row of pixel units, starting from a first column of pixel units, every N pixel units form a pixel unit group, N is a positive integer and is more than or equal to 2, in any pixel unit group, each pixel unit comprises M sub-pixel units with different colors, M is a positive integer and is more than or equal to 3, and the driving method comprises the following steps: and writing data voltages into a plurality of sub-pixel units, wherein M sub-pixel units written with the data voltages in sequence belong to different pixel units for any pixel unit group. The invention also provides a display device, and the driving method of the display panel can improve and even eliminate gray-scale vertical moire when the display panel displays to a certain extent.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a driving method of a display panel, a driving apparatus for performing the driving method, and a display panel including the driving apparatus.
Background
In order to realize the narrow frame, in the prior art, a source driving circuit of the display panel writes data voltage into pixel units arranged in an array by using a multi-way gate so as to reduce the number of input data lines.
Two one-push-six multiplexers 110 are shown in FIG. 1, where one multiplexer 110 is electrically connected to the aggregate input Data1 and the other multiplexer 110 is electrically connected to the aggregate input Data 2. Each multi-path gate has six output ends, and the six output ends of the same multi-path gate are respectively and electrically connected with six columns of sub-pixel units. The six control terminals of the multiplexer 110 are electrically connected to the control signal line MUXR1, the control signal line MUXG1, the control signal line MUXB1, the control signal line MUXR2, the control signal line MUXB2, and the control signal line MUXG2, respectively. According to the timing sequence shown in fig. 2, effective signals are respectively provided for the control signal line MUXR1, the control signal line MUXG1, the control signal line MUXB1, the control signal line MUXR2, the control signal line MUXB2 and the control signal line MUXG2, six output ends of the multiplexer 110 can be controlled to be sequentially conducted with a master input end, data can be written into six different columns of sub-pixel units through one master input end, and therefore the setting of the master input end is reduced, and a narrow frame is achieved.
However, the above-described prior art has the following problems: when the display panel displays, gray-scale vertical moire (Mura) appears on an image, and the display quality is influenced.
Therefore, how to improve the prior art to eliminate the gray-scale vertical moire when the display panel displays becomes an urgent problem to be solved.
Disclosure of Invention
The invention aims to provide a driving method of a display panel and a display device, wherein gray-scale vertical moire generated when the display panel is driven by the driving method can be improved to a certain extent or even eliminated.
To solve the above technical problem, as an aspect of the present invention, a driving method of a display panel is provided, where the display panel includes a plurality of pixel units arranged in a plurality of rows and a plurality of columns, each N pixel units form a pixel unit group from a first column of pixel units, N is a positive integer and N ≧ 2, each pixel unit includes M sub-pixel units of different colors, M is a positive integer and M ≧ 3, the driving method includes:
and writing data voltages into a plurality of sub-pixel units, wherein M sub-pixel units written with the data voltages in time sequence belong to different pixel units for any one pixel unit group.
Preferably, for any two adjacent pixel units in the same pixel group, the sequence of writing data voltages by the sub-pixel units satisfies the following formula (1):
wherein e isiWriting the sequence number of the data voltage to the ith sub-pixel unit in the previous pixel unit;
ejthe sequence number of the data voltage written into the jth sub-pixel unit of the following pixel unit;
i、j、eiand ejIs a uniform positive integer, i is more than or equal to 1 and less than or equal to M, j is more than or equal to 1 and less than or equal to M, and e is more than or equal to 1 and less than or equal to ei≤2M，1≤ej≤2M；
Alpha is a preset threshold value.
Preferably, 0< α ≦ 3.
Preferably, N-2 and M-3.
Preferably, in the same pixel cell group, the sub-pixel cells of the same color are adjacent to each other by the sequence number of the write data voltage.
As a second aspect of the present invention, there is provided a display device, including a display panel and a source driving module, wherein the display panel includes a plurality of pixel units arranged in a plurality of rows and a plurality of columns, each N pixel units form a pixel unit group from a first column of pixel units, N is a positive integer and N is greater than or equal to 2, each pixel unit includes M sub-pixel units of different colors, M is a positive integer and M is greater than or equal to 3, wherein the display device further includes a gate control module and a multi-path gate module,
the source electrode driving module comprises (NxM)/2 signal output ends;
the multichannel gating module comprises (NxM)/2 total input ends and NxM output ends, wherein the NxM output ends are in one-to-one correspondence with the NxM column sub-pixel units, and the (NxM)/2 total input ends are in one-to-one correspondence with the (NxM)/2 signal output ends;
the gating control module is used for controlling the conduction of each total input end and each output end of the multi-path gating module according to the following rules:
for any one of the total input ends, M output ends which are sequentially and continuously conducted with the total input end correspond to the sub-pixel units of the pixel units in different columns respectively, so that for any one of the pixel unit groups, M sub-pixel units which are sequentially and continuously written with data voltages belong to different pixel units.
Preferably, for any two adjacent pixel units in the same pixel group, the sequence of writing data voltages by the sub-pixel units satisfies the following formula (1):
wherein e isiWriting the sequence number of the data voltage to the ith sub-pixel unit in the previous pixel unit;
ejthe sequence number of the data voltage written into the jth sub-pixel unit of the following pixel unit;
i、j、eiand ejIs a uniform positive integer, i is more than or equal to 1 and less than or equal to M, j is more than or equal to 1 and less than or equal to M, and e is more than or equal to 1 and less than or equal to ei≤2M，1≤ej≤2M；
Alpha is a preset threshold value.
Preferably, the multiple-path gating module includes multiple-path gating components, each of which includes two master input terminals and two multiple-path gating units, each of which includes M sub-input terminals, M output terminals, and M control terminals, the M input terminals correspond to the M output terminals one to one, the M sub-input terminals correspond to the M control terminals one to one, and when any one of the control terminals receives the first control signal, the corresponding sub-input terminal is connected to the corresponding output terminal;
each multi-path gating unit corresponds to one pixel unit group, and M output ends of the same multi-path gating unit are respectively used for providing data voltages for M sub-pixel units in the corresponding pixel unit groups;
each of the total input ends is electrically connected with 2M sub-input ends, and the sub-input ends electrically connected with the same total input end belong to different multi-path gating units.
Preferably, each multiplexing gating unit includes 2M gating transistors, gates of the gating transistors are formed as control terminals of the gating unit, first poles of the gating transistors are formed as sub-input terminals of the gating unit, and second poles of the gating transistors are formed as output terminals of the gating unit.
Preferably, the multiple gating component includes two of the total input terminals and two of the multiple gating units, N-2 and M-3.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a prior art multiplexer;
FIG. 2 is a timing diagram illustrating the writing of data voltages to sub-pixel units of the display panel according to the prior art;
FIG. 3 is a schematic diagram illustrating charging when data voltages are written into the sub-pixel units of the display panel according to the timing diagram shown in FIG. 2;
FIG. 4 is a waveform diagram illustrating a simulation performed when a display panel is driven according to the prior art;
FIG. 5 is a flow chart illustrating a driving method provided by the present invention;
FIG. 6 is a timing diagram illustrating an embodiment of a driving method for writing data voltages to sub-pixel units according to the present invention;
FIG. 7 is a schematic diagram of charging when writing data voltages to the sub-pixel units of the display panel according to the timing diagram shown in FIG. 6;
FIG. 8 is a weight analysis table corresponding to the timing sequence of the data voltage written into the sub-pixel unit in the driving method according to the present invention;
FIG. 9 is a circuit diagram of a multiple strobe assembly;
fig. 10 is a schematic view of a display device provided in the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
The inventor of the present invention repeatedly researches and discovers that the reason why the gray-scale vertical moire appears when the display panel displays in the prior art is as follows:
the valid control signals are sequentially supplied to the respective control terminals of the multiplexer according to the timing shown in fig. 1, and the data voltage can be written (charged) to the corresponding sub-pixel unit through the source driving unit. When the data voltages charged by the pixel units in two adjacent columns are the same, as shown in fig. 2, when the signal on the Gate line Gate of the nth row is a turn-on signal, the sub-pixel unit R1 in the nth row and the 1 st column is charged first in one period, and the pixel voltage coupling of the sub-pixel unit R1 is reduced at the moment when the control signal line MUXR1 receives an invalid control signal; then, the sub-pixel unit G1 in the nth row and the 2 nd column is charged, and meanwhile, since the signal on the gate line is the on signal, the input data line corresponding to the sub-pixel unit R1 in the nth row and the 1 st column leaks electricity to the sub-pixel unit R1 in the nth row and the 1 st column through the multiplexer, so that the gray scale voltage of the sub-pixel unit R1 in the nth row and the 1 st column gradually rises. By analogy, the data voltages are written into the 6 sub-pixel units successively, the output ends of the respective multi-channel gates are closed, the gray scale voltage rise time of the sub-pixel units written with the data voltages later is short, further, the coupling of the closed voltages of the multi-channel gates of the sub-pixel units in each row is reduced, the rise time of the leakage voltages is different, the charging time of the sub-pixel units written with the data voltages later in one period is short, the gray scale voltage is small, the pixel is dark, and the gray scale vertical moire appears in the picture when the display panel displays.
Further, when writing the data voltage to the sub-pixel units of the display panel, as shown in fig. 3, the data voltage is written to the sub-pixel units during the high level period of the gate output signal Gata out, and specifically, the multiplexer corresponding to each sub-pixel sequentially outputs the high level signal during each high level period of the gate output signal to selectively write the corresponding data voltage to the sub-pixel units.
In the process of writing the data voltage, when the gate output signal Gata out of one frame is at a high level, when the multiplexers corresponding to the individual sub-pixel cells are not turned on (e.g., MUXG2 has not reached a high level), due to frame flipping, the voltage on the data line corresponding to the sub-pixel unit is +5V, the pixel voltage in the sub-pixel unit is-5V, according to the data line coupling capacitance and the storage capacitance of the sub-pixel unit, the voltage is redistributed, the data line and the corresponding sub-pixel unit are all reduced, for example, sub-pixel cell G2 writes a data voltage later than R1 in fig. 3, so, after the control signal line MUXR1 receives a valid control signal, when the control signal line MUXG2 of the corresponding sub-pixel cell G2 receives an inactive control signal, the voltage values of the sub-pixel cell G2 and the corresponding control signal line MUXG2 are both about 2.6V. Therefore, the duration of the low voltage in the sub-pixel unit for writing the data voltage later is longer, and the duration is consistent with the duration of the low voltage of the corresponding data line, for example, the duration of the low voltage area a on G2_ source in the figure, so that the pixel unit appears as a dark pixel, and gray-scale vertical moire appears in the picture when the display panel displays.
For the above reasons, the inventor considers that the problem of gray-scale vertical moire occurring when the display panel displays can be solved to a certain extent by reducing the time interval between the writing of the data voltages into the adjacent pixel units.
In view of the above, as an aspect of the present invention, there is provided a driving method of a display panel, wherein the display panel includes a plurality of pixel units arranged in a plurality of rows and a plurality of columns, and for any row of the pixel units, starting from a first column of the pixel units, every N pixel units are formed as a pixel unit group, N is a positive integer and N ≧ 2, in any one of the pixel unit groups, each pixel unit includes M sub-pixel units of different colors, M is a positive integer and M ≧ 3, as shown in fig. 5, the driving method includes:
step S1, writing data voltages into a plurality of sub-pixel units, wherein for any one of the pixel unit groups, M sub-pixel units written with data voltages in time sequence belong to different pixel units.
As described above, when the display panel is driven by the driving method including step S1, M consecutive sub-pixel units written with data voltages in time sequence belong to different pixel units, in other words, the time sequence of writing data voltages into the sub-pixel units is adjusted, and no longer data voltages are written into the sub-pixel units according to the time sequence of the prior art, specifically, it is understood that, for any two adjacent pixel units in the same pixel unit group, after writing a data voltage into a first sub-pixel unit of one pixel unit and before writing a data voltage into a last sub-pixel unit of the pixel unit, a data voltage is written into at least one sub-pixel unit of the other pixel unit.
When data voltages are written into the sub-pixel units according to the time sequence, the time interval of writing the data voltages into the two adjacent pixel units can be shortened, and the difference of electric leakage rise time is further reduced; in addition, since the time for which the sub-pixel unit is turned on later to sustain the low voltage is long, when the data voltages are written into the plurality of sub-pixel units in the "time sequence", the absolute value of the difference between the sum of the times for which the sub-pixel units sustain the low voltages may be reduced for any two adjacent pixel units in the same pixel unit group. Thereby improving or even eliminating the gray scale vertical moire when the display panel displays to a certain extent.
Preferably, in the present invention, for any two adjacent pixel units, the sequence of writing data voltages by the sub-pixel units satisfies the following formula (1):
wherein e isiWriting the sequence number of the data voltage to the ith sub-pixel unit in the previous pixel unit; e.g. of the typejThe sequence number of the data voltage written into the jth sub-pixel unit of the following pixel unit; i. j, eiAnd ejIs a uniform positive integer, i is more than or equal to 1 and less than or equal to M, j is more than or equal to 1 and less than or equal to M, and e is more than or equal to 1 and less than or equal to ei≤2M，1≤ejLess than or equal to 2M; α is a preset threshold, preferably 0<α≤3。
The principle of the above formula (1) is specifically explained below:
the inventor of the invention discovers that when the absolute value of the difference between the sum Total of the weights of two adjacent pixel units in one pixel unit group is less than or equal to 3, no obvious gray-scale vertical moire appears when the display panel displays. On the contrary, when the display panel displays, obvious gray-scale vertical moire can appear. Based on the principle, the problem of gray scale vertical moire when the display panel displays can be solved as long as the time sequence of writing data voltage into a plurality of sub-pixel units of the display panel meets the formula (1).
Specifically, referring to the weight analysis table shown in fig. 8, the numerical value corresponding to each sub-pixel unit in the table is the weight corresponding to the rising time of the drain voltage in the process of writing the data voltage into the sub-pixel unit, the larger the numerical value is, the longer the rising time of the leakage voltage is, and meanwhile, the longer the rising time of the leakage voltage is, the earlier the sequence of the data voltage written into the sub-pixel unit is, that is, the sequence number eiAnd ejThe smaller and vice versa.
Taking the 9 th row of data in fig. 7 as an example, the weights of the sub-pixel units R1, G1, B1, R2, G2, and B2 are 6, 4, 2, 5, 3, and 1, respectively, and their physical meanings are as follows: the sub-pixel cell R1 is written with data voltage at 1 st, the sub-pixel cell R2 is written with data voltage at 2 nd, the sub-pixel cell G1 is written with data voltage at 3 rd, the sub-pixel cell G2 is written with data voltage at 4 th, the sub-pixel cell B1 is written with data voltage at 5 th, and the sub-pixel cell B2 is written with data voltage at 6 th.
In other words, as for the above-described adjacent two pixel cells, in the previous pixel cell, the serial number e of the data voltage is written to the sub-pixel cell R11As 1, the sub-pixel unit R2 is written with the serial number e of the data voltage 22, the sub-pixel cell G1 is written with the serial number e of the data voltage 33; in the latter pixel cell, sub-pixel cell G2 is written with the serial number e of the data voltage 44, the sub-pixel unit B1 is written with the serial number e of the data voltage5Sequence of sub-pixel cell B2 being written with data voltage 5Number e6＝6。
Calculating based on the sequence number of the write data voltage corresponding to the sub-pixel unit:
|(1+3+5)-(2+4+6)|＝3 (2)
therefore, the sequence of writing the data voltages into the sub-pixel units meets the condition of formula (1).
It should be noted that the several timings shown in fig. 7 are only used for understanding the technical solution of the present invention, and do not limit the present invention, in other words, the timings satisfying the formula (1) are not limited to the several timings shown in the table of fig. 7.
In the present invention, the number N of pixel units included in each pixel unit group is not limited, and preferably, N is 2, that is, each pixel unit group includes two pixel units.
Meanwhile, the number M of the sub-pixel units of different colors included in each pixel unit is not limited, preferably, M is 3, and further, the sub-pixel units of different colors may be a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit.
In the present invention, when M is 3, in the same pixel unit group, the sequence number of the order in which the data voltages are written in the sub-pixel units of two adjacent pixel units satisfies: e is not less than 1i≤6，1≤ej≤6。
In the present invention, the timing satisfying the formula (1) includes a plurality of timings, wherein, preferably, in the same pixel cell group, the sub-pixel cells of the same color are adjacent to the sequence number of the written data voltage.
In the present invention, the number of sub-pixel units included in each pixel unit and the number of pixel units in each pixel unit group are not particularly limited. For example, each pixel unit group may include two pixel units, and each pixel unit may include three sub-pixels (red, green, and blue sub-pixels, respectively). In other words, N is 2 and M is 3.
The driving method of the present invention will be described below by taking a display panel that may include two pixel units in each pixel unit group, and each pixel unit may include three sub-pixels (red sub-pixel, green sub-pixel, and blue sub-pixel, respectively). When the grid signal of a certain row of pixel units corresponding to the display panel is in a high level period, sequentially providing data voltages for a plurality of sub-pixel units in one pixel unit group according to the following sequence: r1 (sequence number 1), R2 (sequence number 2), G1 (sequence number 3), G2 (sequence number 4), B1 (sequence number 5), B2 (sequence number 6); that is, corresponding to fig. 8, the weights of the sub-pixel units are sequentially: r1 ═ 6, R2 ═ 5, G1 ═ 4, G2 ═ 3, B1 ═ 2, and B2 ═ 1.
As shown in fig. 7, the time interval between writing data voltages into the sub-pixel units R1 and R2, G1 and G2, and B1 and B2 of the same color is significantly shorter than that of the prior art shown in fig. 2, the difference of leakage rise time is reduced, and the difference Δ Vmux of the leakage amount of the sub-pixel units of the same color is reduced, so that the difference Δ Vp of gray scale voltages within the pixel is also reduced; and the difference of the sum of the low voltage duration time in the sub-pixel units of the two pixel units is reduced, so that the gray scale vertical moire when the display panel displays is improved to a certain extent, even eliminated.
As a second aspect of the present invention, a display device is provided, as shown in fig. 10, the display device includes a display panel 10 and a source driving module 20, the display panel 10 includes a plurality of pixel units arranged in rows and columns, each N pixel units form a pixel unit group from a first column of pixel units, N is a positive integer and N ≧ 2, each pixel unit includes M sub-pixel units of different colors, M is a positive integer and M ≧ 3. Wherein, the display device also comprises a gating control module 30 and a multi-path gating module 40.
The source driving module 20 includes (nxm)/2 signal output terminals, and the multiplexing gate module 40 includes (nxm)/2 total input terminals and nxm output terminals, where the nxm output terminals correspond to the nxm columns of sub-pixel units one to one, and the (nxm)/2 total input terminals are electrically connected to the (nxm)/2 signal output terminals in a one to one correspondence.
The gating control module 30 is used for controlling the total input ends and the output ends of the multi-path gating module 40 to be conducted according to the following rules:
for any one of the total input ends, M output ends which are sequentially and continuously conducted with the total input end correspond to the sub-pixel units of the pixel units in different columns respectively, so that for any one of the pixel unit groups, M sub-pixel units which are sequentially and continuously written with data voltages belong to different pixel units.
Through the cooperation of the source driving module 20, the gate control module 30 and the multi-path gate module 40, the display device can be driven by the method provided by the invention, so that the display device has less or even no gray-scale vertical moire when displaying.
In the present invention, the above method can be implemented by controlling the multiplexer. For example, the multiplexer 110 shown in fig. 1 may be provided in the display panel to supply data signals to the sub-pixel units of each column of the display panel.
In the order shown in fig. 6, effective control signals are sequentially supplied to the control signal lines MUXR1, MUXR2, MUXG1, MUXG2, MUXB1 and MUXB2 so that the output terminal of the multiplexer electrically connected to the sub-pixel R1, the output terminal of the multiplexer electrically connected to the sub-pixel R2, the output terminal of the multiplexer electrically connected to the sub-pixel G1, the output terminal of the multiplexer electrically connected to the sub-pixel G2, the output terminal of the multiplexer electrically connected to the sub-pixel B1 and the output terminal of the multiplexer electrically connected to the sub-pixel B2 are sequentially turned on to the global input terminal Data1, so that the sub-pixel R1, the sub-pixel R2, the sub-pixel G1, the sub-pixel G2, the sub-pixel B1 and the sub-pixel B2 sequentially receive Data voltages.
Of course, the present invention is not limited thereto, and the source driving unit and each column of sub-pixel units may be electrically connected by other components.
The source driving unit may be electrically connected to each column of sub-pixel units using a multiplexing module including a plurality of multiplexing components. Specifically, as shown in fig. 9, the multiple gating component includes two total input terminals (total incoming Data1 and total input terminal Data2, respectively), and two multiple gating units (multiple gating unit 110 and multiple gating unit 120, respectively), where each gating unit includes M sub-input terminals, M output terminals, and M control terminals, where the M input terminals are in one-to-one correspondence with the M output terminals, the M sub-input terminals are in one-to-one correspondence with the M control terminals, and when any one control terminal receives a first control signal, the corresponding sub-input terminal is turned on with the corresponding output terminal.
Each multi-path gating unit corresponds to one pixel unit group, and M output ends of the same multi-path gating unit are respectively used for providing data voltages for M sub-pixel units in the corresponding pixel unit groups.
Each of the total input ends is electrically connected with 2M sub-input ends, and the sub-input ends electrically connected with the same total input end belong to different multi-path gating units.
By utilizing the multi-channel gating component provided by the invention, data voltage can be provided for sub-pixel units which are far away from each other through a total input end, so that gray-scale vertical moire can be further reduced. Also, the multiple gating component shown in FIG. 9 is advantageous in that: when the multi-channel gating component is applied to a liquid crystal display device, the same signal line is used for inputting signals to pixels in odd columns or even columns, and power consumption can be reduced when pixel column inversion is achieved.
For example, when N is 2 and M is 3, and one pixel unit includes a red sub-pixel unit, a green sub-pixel unit, and a blue-to-pixel unit, the Data voltage may be supplied to the red sub-pixel unit of the 1 st column, the blue sub-pixel unit of the 3 rd column, the green sub-pixel unit of the 5 th column, the red sub-pixel unit of the 7 th column, the blue sub-pixel unit of the 9 th column, and the green sub-pixel unit of the 11 th column using the total input Data 1; the Data voltages can be supplied to the green sub-pixel unit of the 2 nd column, the red sub-pixel unit of the 4 th column, the blue sub-pixel unit of the 6 th column, the green sub-pixel unit of the 8 th column, and the red sub-pixel unit of the 10 th column by using the total input Data 2. In other words, the plurality of sub-pixel units in the odd-numbered columns share one data line, and the plurality of sub-pixel units in the even-numbered columns share one data line.
In the present invention, the specific structure of the multiple gating unit is not particularly limited. In the embodiment shown in fig. 9, each multiplexing gating unit includes 2M gating transistors, gates of which are formed as control terminals of the gating unit, first poles of which are formed as sub-input terminals of the gating unit, and second poles of which are formed as output terminals of the gating unit.
It should be explained that when the control terminal of the gating transistor receives an effective control signal, the first pole and the second pole of the gating transistor are conducted; the gate transistor is turned off between the first and second poles when its control terminal receives an inactive control signal.
In the embodiment shown in fig. 9, the gating transistor is an N-type transistor, and thus the active control signal is a high level signal and the inactive control signal is a low level signal.
In addition, the display device including the display panel is not limited in the present invention, and for example, the display device may be a smart phone, a tablet computer, an in-vehicle display device, and the like.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (8)
1. A driving method of a display panel is characterized in that the display panel comprises a plurality of pixel units which are arranged in a plurality of rows and columns, every N pixel units form a pixel unit group from a first column of pixel units, N is a positive integer and N is larger than or equal to 2, each pixel unit comprises M sub-pixel units with different colors, M is a positive integer and M is larger than or equal to 3, and the driving method comprises the following steps:
writing data voltages into a plurality of sub-pixel units, wherein M sub-pixel units written with the data voltages in sequential succession belong to different pixel units for any one pixel unit group;
for any two adjacent pixel units in the same pixel group, the sequence of writing data voltages into the sub-pixel units satisfies the following formula (1):
wherein e isiWriting the sequence number of the data voltage to the ith sub-pixel unit in the previous pixel unit;
ejthe sequence number of the data voltage written into the jth sub-pixel unit of the following pixel unit;
i、j、eiand ejIs a uniform positive integer, i is more than or equal to 1 and less than or equal to M, j is more than or equal to 1 and less than or equal to M, and e is more than or equal to 1 and less than or equal to ei≤2M，1≤ej≤2M；
Alpha is a preset threshold value.
2. The driving method according to claim 1, wherein 0< α ≦ 3.
3. The driving method according to claim 1, wherein N-2 and M-3.
4. The driving method according to any one of claims 1 to 3, wherein the sub-pixel cells of the same color in the same pixel cell group are adjacent to each other with the sequence number of the data voltage being written.
5. A display device comprises a display panel and a source electrode driving module, wherein the display panel comprises a plurality of pixel units which are arranged in a plurality of rows and columns, every N pixel units form a pixel unit group from a first column of pixel units, N is a positive integer and is more than or equal to 2, each pixel unit comprises M sub-pixel units with different colors, M is a positive integer and is more than or equal to 3, the display device is characterized by further comprising a gating control module and a multi-path gating module,
the source electrode driving module comprises (NxM)/2 signal output ends;
the multichannel gating module comprises (NxM)/2 total input ends and NxM output ends, wherein the NxM output ends are in one-to-one correspondence with the NxM column sub-pixel units, and the (NxM)/2 total input ends are in one-to-one correspondence with the (NxM)/2 signal output ends;
the gating control module is used for controlling the conduction of each total input end and each output end of the multi-path gating module according to the following rules:
for any one of the total input ends, M output ends which are continuously conducted with the total input end in time sequence respectively correspond to the sub-pixel units of the pixel units in different columns, so that for any one of the pixel unit groups, M sub-pixel units which are continuously written with data voltages in time sequence belong to different pixel units;
for any two adjacent pixel units in the same pixel group, the sequence of writing data voltages into the sub-pixel units satisfies the following formula (1):
wherein e isiWriting the sequence number of the data voltage to the ith sub-pixel unit in the previous pixel unit;
ejthe sequence number of the data voltage written into the jth sub-pixel unit of the following pixel unit;
i、j、eiand ejIs a uniform positive integer, i is more than or equal to 1 and less than or equal to M, j is more than or equal to 1 and less than or equal to M, and e is more than or equal to 1 and less than or equal to ei≤2M，1≤ej≤2M；
Alpha is a preset threshold value.
6. The display device according to claim 5, wherein the multi-channel gating module comprises a plurality of multi-channel gating components, the multi-channel gating components comprise two main input ends and two multi-channel gating units, each gating unit comprises M sub-input ends, M output ends and M control ends, the M input ends are in one-to-one correspondence with the M output ends, the M sub-input ends are in one-to-one correspondence with the M control ends, and when any one control end receives a first control signal, the corresponding sub-input end is conducted with the corresponding output end;
each multi-path gating unit corresponds to one pixel unit group, and M output ends of the same multi-path gating unit are respectively used for providing data voltages for M sub-pixel units in the corresponding pixel unit groups;
each of the total input ends is electrically connected with 2M sub-input ends, and the sub-input ends electrically connected with the same total input end belong to different multi-path gating units.
7. The display device according to claim 6, wherein each multiplexing gating cell includes 2M gating transistors, gates of the gating transistors are formed as control terminals of the gating cell, first poles of the gating transistors are formed as sub-input terminals of the gating cell, and second poles of the gating transistors are formed as output terminals of the gating cell.
8. The display device according to any one of claims 6 to 7, wherein the multiplex assembly comprises two of the total inputs and two of the multiplex units, N-2 and M-3.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105096809A (en) * | 2015-09-18 | 2015-11-25 | 京东方科技集团股份有限公司 | Display substrate and driving method thereof and display device |
| CN105118430A (en) * | 2015-08-31 | 2015-12-02 | 上海和辉光电有限公司 | Pixel driving circuit, driving method thereof and display device |
| CN106097988A (en) * | 2015-04-30 | 2016-11-09 | 乐金显示有限公司 | Display device |
| CN106292096A (en) * | 2016-10-13 | 2017-01-04 | 武汉华星光电技术有限公司 | A kind of De mux liquid crystal display and driving method thereof |
| CN106297720A (en) * | 2016-10-17 | 2017-01-04 | 武汉华星光电技术有限公司 | The driving method of a kind of display panels and system |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI275056B (en) * | 2005-04-18 | 2007-03-01 | Wintek Corp | Data multiplex circuit and its control method |
| KR101253273B1 (en) * | 2005-12-16 | 2013-04-10 | 삼성디스플레이 주식회사 | Display apparatus and method for driving the same |
| CN103280195B (en) * | 2012-06-28 | 2016-01-13 | 上海天马微电子有限公司 | Row reversion is adopted to drive liquid crystal indicator and the driving method thereof of the reversion of realization point |
| CN106531096B (en) * | 2016-11-28 | 2019-12-24 | 武汉华星光电技术有限公司 | RGBW four primary color display panel driving method |
| CN108648681A (en) * | 2018-06-29 | 2018-10-12 | 厦门天马微电子有限公司 | A kind of display panel, its driving method, driving device and display device |
| CN109754745B (en) * | 2019-03-26 | 2021-10-01 | 京东方科技集团股份有限公司 | Display panel driving method and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106097988A (en) * | 2015-04-30 | 2016-11-09 | 乐金显示有限公司 | Display device |
| CN105118430A (en) * | 2015-08-31 | 2015-12-02 | 上海和辉光电有限公司 | Pixel driving circuit, driving method thereof and display device |
| CN105096809A (en) * | 2015-09-18 | 2015-11-25 | 京东方科技集团股份有限公司 | Display substrate and driving method thereof and display device |
| CN106292096A (en) * | 2016-10-13 | 2017-01-04 | 武汉华星光电技术有限公司 | A kind of De mux liquid crystal display and driving method thereof |
| CN106297720A (en) * | 2016-10-17 | 2017-01-04 | 武汉华星光电技术有限公司 | The driving method of a kind of display panels and system |
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