WO2020192676A1

WO2020192676A1 - Drive method and drive device for display panel, and display device

Info

Publication number: WO2020192676A1
Application number: PCT/CN2020/081040
Authority: WO
Inventors: 王争奎; 王珍; 张寒
Original assignee: 京东方科技集团股份有限公司; 鄂尔多斯市源盛光电有限责任公司
Priority date: 2019-03-26
Filing date: 2020-03-25
Publication date: 2020-10-01
Also published as: CN109754745B; CN109754745A

Abstract

Disclosed are a drive method and a drive device for a display panel, and a display device. The display panel comprises a plurality of pixel units arranged in multiple rows and columns, each pixel unit comprising a plurality of sub-pixel units, and the display panel has at least one pixel unit group, each pixel unit group comprising at least two columns of pixel units. The drive method comprises: step S1, during the writing of a data signal into sub-pixel units, located in the same row, of each pixel unit group, writing the data signal into the sub-pixel units successively according to a time sequence, wherein M sub-pixel units into which the data signal is written sequentially in time comprise sub-pixel units from different pixel units, M being an integer greater than three.

Description

Driving method of display panel, driving device and display device

Cross references to related applications

This application claims the priority of Chinese Patent Application No. 201910231212.3 filed on March 26, 2019, the content of which is incorporated herein by reference in its entirety.

Technical field

The present disclosure relates to the field of display technology, and in particular, to a driving method of a display panel, a driving device for executing the driving method, and a display device including the driving device.

Background technique

At present, narrow bezel design has become the development trend of smart mobile display devices. The display device includes a display panel. In order to realize the narrow frame, the source driving circuit of the display panel may use multiplexers to write data voltages for the pixel units arranged in the array to reduce the number of input data lines. .

Summary of the invention

As an aspect of the present disclosure, a method for driving a display panel is provided, wherein the display panel includes a plurality of pixel units arranged in multiple rows and multiple columns, each pixel unit includes a plurality of sub-pixel units, and the display panel has At least one pixel unit group, and each pixel unit group includes at least two columns of pixel units. The driving method includes: during the writing of data signals to the sub-pixel units in the same row in each pixel unit group, sequentially writing data signals to the sub-pixel units in a time sequence, wherein the data signals are successively written in time. The M sub-pixel units in which data signals are written include sub-pixel units from different pixel units, and M is an integer greater than 3.

In some embodiments, the order in which data signals are written to sub-pixel units in any two adjacent pixel units in the same pixel unit group meets the following conditions:

Where e _i is the sequence number of the i-th sub-pixel unit in the first pixel unit of the two pixel units being written with data signals; e _j is the sequence number in the second pixel unit of the two pixel units The sequence number of the j-th sub-pixel unit in which the data signal is written; i, j, e _i and e _j are all positive integers, and 1≤i≤M, 1≤j≤M, 1≤e _i ≤2M, 1≤ e _j ≤ 2M; α is the preset threshold.

In some embodiments, 0<α≦3.

In some embodiments, each pixel unit group includes N pixel units, and the N sub-pixel units to which data signals are successively written in time belong to different pixel units, and N is an integer greater than 2.

In some embodiments, in the same pixel unit group, the sub-pixel units of the same color are written adjacent to each other in an order in which data signals are written.

As another aspect of the present disclosure, a driving device for a display panel is provided. The display panel includes a plurality of pixel units arranged in multiple rows and multiple columns, each pixel unit includes a plurality of sub-pixel units, the display panel has at least one pixel unit group, and each pixel unit group includes at least two columns of pixel units. The driving device is configured to: during the writing of data signals to the sub-pixel units in the same row in each pixel unit group, the data signals are sequentially written to the sub-pixel units in chronological order, wherein, successively in time The M sub-pixel units to which the data signal is written include sub-pixel units from different pixel units, and M is an integer greater than 3.

In some embodiments, the driving device is configured such that the order in which data signals are written into the sub-pixel units in any two adjacent pixel units in the same pixel unit group meets the following conditions:

In some embodiments, 0<α≦3.

In some embodiments, in the same pixel unit group, the sub-pixel units of the same color are written adjacent to each other in the order of writing data signals.

As another aspect of the present disclosure, there is provided a display device including a display panel, a multiplexer circuit, and a gate controller. The display panel includes a plurality of pixel units arranged in multiple rows and multiple columns, each pixel unit includes a plurality of sub-pixel units, the display panel has at least one pixel unit group, and each pixel unit group includes at least two columns of pixel units. The multiplexer circuit is configured to control data signal writing to the sub-pixel units in each pixel unit group. The strobe controller is configured to control the multiplexer circuit to perform the following operations: during the writing of data signals to the sub-pixel units in the same row in each pixel unit group, sequentially causing the The sub-pixel unit receives the data signal, wherein the M sub-pixel units connected in time to receive the data signal include sub-pixel units from different pixel units, and M is an integer greater than 3.

In some embodiments, the strobe controller is configured to control the multiplexer circuit so that the order in which the sub-pixel units of any two adjacent pixel units in the same pixel unit group receive data voltages meets the following conditions:

Where e _i is the sequence number of the i-th sub-pixel unit in the first pixel unit of the two pixel units to receive the data signal; e _j is the j-th sub-pixel unit of the second pixel unit in the two pixel units The sequence number of the pixel unit receiving the data signal; i, j, e _i and e _j are all positive integers, and 1≤i≤M, 1≤j≤M, 1≤e _i ≤2M, 1≤e _j ≤2M; α is the preset threshold.

In some embodiments, 0<α≦3.

In some embodiments, the gate controller is configured to control the multiplexer circuit so that the sub-pixel units of the same color in the same pixel unit group are adjacent to each other in order of receiving data signals.

In some embodiments, the multiplexer circuit includes at least one multiplexer, each multiplexer is connected to each sub-pixel unit of a pixel unit group, and is configured to respond to a set of control The signal transfers the data signal from the general input terminal to the corresponding sub-pixel unit.

In some embodiments, each multiplexer includes a plurality of switching elements, a first end of each switching element is connected to a column of sub-pixel units, and a second end of each switching element is connected to the total input end, each The control terminal of the switching element is connected to the corresponding control signal terminal.

In some embodiments, the second ends of the multiple switching elements of each multiplexer are all connected to the same general input end.

In some embodiments, the multiplexer circuit includes a first multiplexer and a second multiplexer, the first multiplexer and the second multiplexer The second end of the switching element connected to the odd-numbered column of the sub-pixel unit is connected to the first total input terminal, the first multiplexer and the second multiplexer and the even-numbered column The second end of the switching element connected to the pixel unit is connected to a second total input end, and the first total input end is different from the second total input end.

In some embodiments, each pixel unit group includes N pixel units, and the gate controller is configured to control the multiplexer circuit so that the N sub-pixel units that are connected in time and receive data signals belong to different Pixel unit, N is an integer greater than 2.

Description of the drawings

The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the attached picture:

Figure 1 is a schematic diagram of a multiplexer in a display device;

2 is a timing diagram of writing data voltages to sub-pixel units of the display panel;

3 is a schematic diagram of charging when writing data voltages to sub-pixel units of the display panel according to the timing chart shown in FIG. 2;

Figure 4 is a simulation waveform diagram when the display panel is driven;

Fig. 5 is a flowchart of a driving method according to an embodiment of the present disclosure;

6 is a timing diagram of writing data voltages to sub-pixel units using the driving method according to an embodiment of the present disclosure;

7 is a schematic diagram of charging when writing data voltages to sub-pixel units of the display panel according to the timing chart shown in FIG. 6;

FIG. 8 is a weight table corresponding to the timing of writing a data voltage to the sub-pixel unit in the driving method according to an embodiment of the present disclosure;

Figure 9 is a schematic diagram of a multiplexer in the display device;

FIG. 10 is a schematic diagram of a display device according to an embodiment of the present disclosure.

detailed description

The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described here are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure.

Figure 1 is a schematic diagram of a multiplexer in a display device. Two

multiplexers

110, 120 are shown in FIG. The multiplexer 110 is electrically connected to the total input terminal Data1, and the multiplexer 120 is electrically connected to the total input terminal Data2. Each multiplexer has six output terminals, and the six output terminals of the same multiplexer are connected to the six columns of sub-pixel units in a one-to-one correspondence. The six control terminals of the multiplexer 110 are electrically connected to the control signal line MUXR1, the control signal line MUXG1, the control signal line MUXB1, the control signal line MUXR2, the control signal line MUXB2, and the control signal line MUXG2. According to the time sequence shown in Figure 2, effective signals are provided to the control signal line MUXR1, control signal line MUXG1, control signal line MUXB1, control signal line MUXR2, control signal line MUXB2, and control signal line MUXG2 to control the multiplexer 110. The six output terminals are connected to the main input terminal in sequence. As a result, data can be written to six different sub-pixel units through one total input terminal, thereby reducing the number of total input terminals and helping to achieve a narrow frame.

However, the above driving method has the following problem: when the display panel displays an image, gray-scale vertical moiré (mura) appears on the image, which affects the display quality.

Studies have found that the reasons for the gray-scale vertical moiré appearing when displaying images on the display panel are as follows.

According to the time sequence shown in FIG. 2, effective control signals are sequentially provided to each control terminal of the multiplexer, and the data voltage (charging) can be written to the corresponding sub-pixel unit through the source driver. When the data voltages charged by two adjacent columns of pixel units are the same, as shown in FIG. 3, when the signal on the gate line Gate of the Nth row is an on signal, the sub-pixel unit R1 of the Nth row and the first column is charged first; Then, the N-th row and the second column sub-pixel unit G1 is charged. At the moment when the control signal line MUXR1 receives an invalid control signal, the pixel voltage coupling of the sub-pixel unit R1 decreases. At the same time, since the signal on the gate line Gate is still an on signal, the input data line corresponding to the sub-pixel unit R1 in the Nth row and the first column leaks to the Nth row and the first column sub-pixel unit R1 through the multiplexer, resulting in the Nth The gray-scale voltage of the sub-pixel unit R1 in the first column of the row gradually rises. By analogy, the 6 sub-pixel units sequentially write data voltages. After each sub-pixel unit writes the data voltage, the corresponding control signal line receives an invalid control signal, and then the gray-scale voltage of the sub-pixel unit that writes the data voltage rises. The time is shorter. Furthermore, the voltage coupling of each row of sub-pixel units is reduced due to the closure of the corresponding channel of the multiplexer, the leakage voltage recovery time is different, the charging time of the sub-pixel units with the data voltage written later is shorter, the gray-scale voltage is smaller, The pixels are dark. As a result, gray-scale vertical moiré appears when the display panel displays images.

In addition, when writing the data voltage to the sub-pixel unit of the display panel, as shown in FIG. 4, the data voltage is written into the sub-pixel unit during the period when the gate output signal Gate out is at a high level. During the high-level period of the gate output signal, the control signal lines corresponding to each sub-pixel unit sequentially output high-level signals to selectively write the corresponding data voltages into the sub-pixel units.

In the above process of writing the data voltage, when the gate output signal Gate out is at a high level, the control signal line corresponding to the sub-pixel unit does not provide a valid control signal (for example, when MUXG2 does not reach a high level), due to the frame Flip, the voltage on the data line of the corresponding sub-pixel unit is +5V, and the pixel voltage in the sub-pixel unit is -5V. According to the data line coupling capacitor and the storage capacitor of the sub-pixel unit, the voltage is redistributed, the data line and the corresponding sub-pixel unit The voltages are reduced. For example, in FIG. 4, the sub-pixel unit G2 writes a data voltage after the sub-pixel unit R1. Therefore, after the control signal line MUXR1 receives a valid control signal, the control signal line MUXG2 of the sub-pixel unit G2 receives an invalid control signal. At this time, the voltage value of the sub-pixel unit G2 and the voltage value of the corresponding data line are both about 2.6V. Therefore, the duration of the low voltage in the sub-pixel unit where the data voltage is written later is longer, and the duration is consistent with the duration of the low voltage duration of the corresponding data line (for example, the duration of the low voltage area A on G2_source in the figure), so As a result, the pixel unit appears dark, which in turn causes vertical gray-scale moiré to appear when the display panel displays an image.

In the present disclosure, by reducing the time interval for writing data voltages in adjacent pixel units, the problem of gray-scale vertical moiré appearing when the display panel displays an image is solved to a certain extent.

In view of this, as an aspect of the present disclosure, a method for driving a display panel is provided. The display panel includes multiple pixel units arranged in multiple rows and multiple columns, and each pixel unit includes multiple sub-pixel units. The display panel has at least one pixel unit group, and each pixel unit group includes at least two columns of pixel units. In some embodiments, each pixel unit group includes N pixel units, where N is a positive integer and N≧2, and each pixel unit includes M sub-pixel units of different colors, and M is a positive integer and M≧3. As shown in FIG. 5, the driving method includes:

Step S1. During the writing of data signals to the sub-pixel units in the same row in each pixel unit group, the data signals are sequentially written to the sub-pixel units in chronological order, wherein data is written successively in time The M sub-pixel units of the signal include sub-pixel units from different pixel units.

As described above, when the display panel is driven by the driving method of the present disclosure, the M sub-pixel units to which data signals are written successively in time include image sub-pixel units from different pixel units, in other words, multiple sub-pixel units are adjusted The timing of writing the data voltage does not write the data voltage to each pixel unit sequentially. For any two adjacent pixel units in the same pixel unit group, after the data voltage is written to the first sub-pixel unit of one of the pixel units until the data voltage is written to the last sub-pixel unit of the pixel unit Previously, at least a data voltage was written to at least one sub-pixel unit of another pixel unit.

When data voltages are written to a plurality of sub-pixel units according to the driving method, the time interval for writing data voltages of the two adjacent pixel units can be shortened, thereby reducing the difference in the recovery time of the leakage voltage. In addition, since the low voltage in the sub-pixel unit is turned on for a long time, when the data voltage is written to multiple sub-pixel units according to the driving method, any two adjacent ones in the same pixel unit group can also be used. The difference in the sum of the total time of the continuous low voltage of the respective sub-pixel units of the pixel unit decreases. Furthermore, to a certain extent, the gray-scale vertical moiré that appears when the display panel displays an image is improved or even eliminated.

In some embodiments, the order in which data signals are written to sub-pixel units in any two adjacent pixel units in the same pixel unit group satisfies the following formula (1):

Wherein, e _i is the sequence number of the i-th sub-pixel unit in the first pixel unit of the two pixel units in which data signals are written; e _j is the sequence number of the second pixel unit in the two pixel units The sequence number of the data voltage written into the j sub-pixel unit; i, j, e _i, and e _j are all positive integers, and 1≤i≤M, 1≤j≤M, 1≤e _i ≤2M, 1≤e _j ≤2M; α is the preset threshold. In some embodiments, 0<α≦3.

The inventors of the present disclosure have conducted multiple drive tests on the display panel and found that when the absolute value of the difference between the weight and Total of two adjacent pixel units in a pixel unit group is less than or equal to 3, the display panel will not display images. Obvious gray-scale vertical moiré appears. On the contrary, when the display panel displays an image, there will be obvious vertical gray-scale moiré. Based on the above test results, as long as the timing of writing data voltages to the multiple sub-pixel units of the display panel satisfies formula (1), the problem of gray-scale vertical moiré during display of the display panel can be solved.

Referring to the weighting table shown in FIG. 8, the corresponding value of each sub-pixel unit (R1, G1, B1, R2, G2, B2) in the table is the corresponding value of the leakage voltage rise time of the sub-pixel unit in the process of writing the data voltage. the weight of. The larger the value of the weight, the longer the recovery time of the leakage voltage. At the same time, the longer the recovery time of the leakage voltage also indicates that the sub-pixel unit is written in the data voltage earlier, that is, the sequence numbers e _i and e _{j are} smaller. ,vice versa.

Taking the 7th row data in Figure 8 as an example, the weights of sub-pixel units R1, G1, B1, R2, G2, and B2 are 6, 4, 2, 5, 3, 1, respectively, and their physical meaning is: sub-pixel unit R1 The first is written with data voltage, sub-pixel unit R2 is written with data voltage the second, sub-pixel unit G1 is written with data voltage the third, sub-pixel unit G2 is written with data voltage fourth, sub-pixel The fifth cell B1 is written with data voltage, and the sixth sub-pixel cell B2 is written with data voltage.

In other words, the pixel unit including the sub-pixel units R1, G1, and B1 and the pixel unit including the sub-pixel units R2, G2, and B2, the sub-pixel unit R1 is written with the order number e ₁ =1 of the data voltage, and the sub-pixel unit R2 is The sequence number of the written data voltage e ₂ =2, the sequence number of the sub-pixel unit G1 being written with data voltage e ₃ =3; the sequence number of the sub-pixel unit G2 being written with the data voltage e ₄ =4, the sub-pixel unit B1 The sequence number e ₅ =5 of the written data voltage, and the sequence number e ₆ =6 of the sub-pixel unit B2 where the data voltage is written.

Put the above sequence number into formula 1 to get:

Therefore, the sequence of writing data voltages in the sub-pixel units meets the condition of formula (1).

It should be noted that the several time sequences shown in FIG. 8 are only used to understand the technical solutions of the present disclosure, and do not constitute a limitation to the present disclosure. In other words, the time sequence that satisfies formula (1) is not limited to the situation in FIG. 8.

In the present disclosure, the number N of pixel units included in each pixel unit group is not limited. In some embodiments, N=2, that is, each pixel unit group includes two pixel units.

In addition, in the present disclosure, the number M of sub-pixel units of different colors included in each pixel unit is not limited. In some embodiments, M=3. The sub-pixel units of different colors may be red sub-pixel units, green sub-pixel units, and blue sub-pixel units.

In the present disclosure, when M=3, in the same pixel unit group, the sequence numbers of the written data voltages of the sub-pixel units of two adjacent pixel units satisfy: 1≤e _i ≤6, 1≤e _j ≤6 .

In the present disclosure, there are multiple timings that satisfy the formula (1). In some embodiments, the N sub-pixel units to which data signals are written consecutively in time belong to different pixel units. In some embodiments, in the same pixel unit group, the sub-pixel units of the same color are written adjacent to each other in an order in which data signals are written.

In the present disclosure, there are no special restrictions on the number of sub-pixel units included in each pixel unit and the number of pixel units in each pixel unit group. For example, each pixel unit group may include two pixel units, and each pixel unit may include three sub-pixels (respectively a red sub-pixel, a green sub-pixel, and a blue sub-pixel). In other words, N=2, M=3.

Taking a display panel in which each pixel unit group can include two pixel units, and each pixel unit can include three sub-pixels (respectively a red sub-pixel, a green sub-pixel, and a blue sub-pixel) as an example, the drive of the present disclosure Methods are introduced. When the gate signal of the pixel unit corresponding to a certain row of the display panel is at a high level, the data voltage is provided to multiple sub-pixel units in a pixel unit group in the following order: sub-pixel unit R1 (sequence number 1), sub-pixel Unit R2 (sequence number is 2), sub-pixel unit G1 (sequence number is 3), sub-pixel unit G2 (sequence number is 4), sub-pixel unit B1 (sequence number is 5), sub-pixel unit B2 (sequence number is 6); That is, corresponding to FIG. 8, the weights of each sub-pixel unit are: R1=6, R2=5, G1=4, G2=3, B1=2, B2=1.

As shown in FIG. 7, the time interval for writing data voltages in the sub-pixel units R1 and R2, G1 and G2, B1 and B2 of the same color is significantly shorter than that shown in FIG. 2, and the difference in leakage voltage recovery time is reduced. . In addition, the leakage amount difference ΔVmux of the sub-pixel units of the same color is reduced, and the gray-scale voltage difference ΔVp in the pixel unit is also reduced; and the difference in the sum of the low voltage duration of the respective sub-pixel units of the two pixel units is also reduced. Therefore, it can improve or even eliminate the gray-scale vertical moiré that appears when the display panel displays images to a certain extent.

As a second aspect of the present disclosure, a display device is provided. As shown in FIG. 10, the display device includes a display panel 10 and a source driving circuit 40. The display panel 10 includes multiple pixel units arranged in multiple rows and multiple columns, and each pixel unit includes multiple sub-pixel units. The display panel has at least one pixel unit group, and each pixel unit group includes at least two columns of pixel units. In some embodiments, each pixel unit group includes N pixel units, where N is a positive integer and N≧2, and each pixel unit includes M sub-pixel units of different colors, and M is a positive integer and M≧3. The display device also includes a gate controller 30 and multiple

gater circuits

110 and 120. The

multiplexer circuits

110 and 120 are configured to control the writing of data signals to the sub-pixel units in each pixel unit group. The gate controller 30 is configured to control the multiple

gater circuits

110 and 120 to perform the following operations: during the writing of data signals to the sub-pixel units in the same row in each pixel unit group, the The sub-pixel unit receives the data signal, wherein the M sub-pixel units connected in time to receive the data signal include sub-pixel units from different pixel units.

Through the cooperation of the source drive circuit 40, the gate controller 30, and the

multiple gate circuits

110, 120, the display device can be driven by the above-mentioned method according to the present disclosure. Therefore, when the display device displays an image, There is little or no gray-scale vertical moiré.

In the present disclosure, the above-mentioned driving method can be realized by controlling the multiplexer circuit. For example, the multiplexer 110 shown in FIG. 1 may be provided in the display panel to provide data signals to each column of sub-pixel units of the display panel. In some embodiments, the multiplexer circuit includes at least one multiplexer, and each multiplexer is connected to each sub-pixel unit of a pixel unit group and is configured to respond to a set of control signals. The data signal from the total input terminal is transferred to the corresponding sub-pixel unit. In some embodiments, each multiplexer includes a plurality of switching elements, a first end of each switching element is connected to a column of sub-pixel units, and a second end of each switching element is connected to the total input end, each The control terminal of the switching element is connected to the corresponding control signal terminal. In some embodiments, the second ends of the multiple switching elements of each multiplexer are all connected to the same general input end.

According to the time sequence shown in Fig. 6, effective control signals are provided to the control signal lines MUXR1, MUXR2, MUXG1, MUXG2, MUXB1, and MUXB2 in sequence, so that the output terminals and the multiple channels electrically connected to the sub-pixel unit R1 in the multiplexer The output terminal that is electrically connected to the sub-pixel unit R2 in the multiplexer, the output terminal that is electrically connected to the sub-pixel unit G1 in the multiplexer, the output terminal that is electrically connected to the sub-pixel unit G2 in the multiplexer, The output terminal electrically connected to the sub-pixel unit B1 in the multiplexer and the output terminal electrically connected to the sub-pixel unit B2 in the multiplexer are sequentially connected to the total input terminal Data1, so that the sub-pixel units R1, The sub-pixel unit R2, the sub-pixel unit G1, the sub-pixel unit G2, the sub-pixel unit B1, and the sub-pixel unit B2 sequentially receive the data voltage.

Of course, the present disclosure is not limited to this, and other components may also be used to electrically connect the source driving circuit with each column of sub-pixel units.

The source driving circuit can be electrically connected to each column of sub-pixel units by using a multiplexer circuit including multiple multiplexer components. As shown in Figure 9, the multi-channel gating component includes two total input terminals (respectively the total number of single input Data1 and total input data2), two multiplexers (respectively the multiplexer 110 and Multiplexer 120), each multiplexer includes M sub-input terminals, M output terminals, and M control terminals. The M sub-input terminals correspond to the M output terminals one-to-one, and the M sub-input terminals There is a one-to-one correspondence with the M control terminals. When any one of the control terminals receives the first control signal, the corresponding sub-input terminal is conducted with the corresponding output terminal. In some embodiments, the multiplexer circuit includes a first multiplexer and a second multiplexer, the first multiplexer and the second multiplexer and the odd column The second end of the switching element connected to the sub-pixel unit is connected to the first total input end, and the second end of the switching element connected to the even-numbered column of the sub-pixel units in the first multiplexer and the second multiplexer Connected to a second total input terminal, and the first total input terminal is different from the second total input terminal.

Each multiplexer corresponds to a pixel unit group, and the M output terminals of the same multiplexer are respectively used to provide data voltages for the M sub-pixel units in the corresponding pixel unit group.

Each of the total input terminals is electrically connected to 2M sub-input terminals, and the sub-input terminals electrically connected to the same total input terminal may belong to different multiplexers.

By using the multi-channel gating component according to the present disclosure, the data voltage can be provided to the far apart sub-pixel units through one total input terminal, so that the gray-scale vertical moiré can be further reduced. The advantage of the multi-channel gate assembly shown in FIG. 9 is that when the multi-channel gate assembly is applied to a liquid crystal display device, the same signal line is used to input signals for odd-numbered or even-numbered columns of pixels, which can be implemented Reduce power consumption when pixel columns are inverted.

For example, when N=2, M=3, and a pixel unit includes a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit, the total input terminal Data1 can be used to send data to the red sub-pixel unit R1 in the first column. The blue sub-pixel unit B1 in the 3rd column, the green sub-pixel unit G2 in the 5th column, the red sub-pixel unit R1 in the 7th column, the blue sub-pixel unit B1 in the 9th column, and the green sub-pixel unit in the 11th column G2 provides data voltage; the total input terminal Data2 can be used to provide the green sub-pixel unit G1 in the second column, the red sub-pixel unit R2 in the fourth column, the blue sub-pixel unit B2 in the sixth column, and the green sub-pixel in the eighth column The cell G1, the red sub-pixel unit R2 in the 10th column, and the blue sub-pixel unit B2 in the 12th column provide data voltages. In other words, multiple sub-pixel units located in odd-numbered columns share one data line, and multiple sub-pixel units located in even-numbered columns share one data line.

In the present disclosure, there is no special restriction on the specific structure of the multiplexer. In the embodiment shown in Fig. 9, each multiplexer includes M*N gate transistors, and the gate of the gate transistor is formed as the control terminal of the multiplexer, so The first pole of the gate transistor is formed as a sub-input terminal of the multiplexer, and the second pole of the gate transistor is formed as an output terminal of the multiplexer.

It should be explained that when the control terminal of the strobe transistor receives a valid control signal, the first and second electrodes of the strobe transistor are turned on; when the control terminal of the strobe transistor receives an invalid control signal, the selection The first pole and the second pole of the pass transistor are disconnected.

In the embodiment shown in FIG. 9, the gate transistor is an N-type transistor, therefore, the effective control signal is a high-level signal, and the ineffective control signal is a low-level signal. In other embodiments, the gate transistor is a P-type transistor, the effective control signal is a low-level signal, and the ineffective control signal is a high-level signal.

In addition, the present disclosure does not limit the display device including the display panel. For example, the display device may be a smart phone, a tablet computer, a vehicle-mounted display device, and the like.

As a third aspect of the present disclosure, a driving device for a display panel is provided. The display panel includes multiple pixel units arranged in multiple rows and multiple columns, and each pixel unit includes multiple sub-pixel units. The display panel has at least one pixel unit group, and each pixel unit group includes at least two columns of pixel units. The driving device is configured to sequentially write data signals to the sub-pixel units in chronological order during the writing of data signals to the sub-pixel units in the same row in each pixel unit group. The M sub-pixel units to which data signals are successively written in time include sub-pixel units from different pixel units, and M is an integer greater than 3.

Where e _i is the sequence number of the i-th sub-pixel unit in the first pixel unit of the two pixel units being written with data signals; e _j is the sequence number in the second pixel unit of the two pixel units The sequence number of the j-th sub-pixel unit in which the data signal is written; i, j, e _i and e _j are all positive integers, and 1≤i≤M, 1≤j≤M, 1≤e _i ≤2M, 1≤ e _j ≤ 2M; α is the preset threshold. In some embodiments, 0<α≦3.

It can be understood that the above implementations are merely exemplary implementations used to illustrate the principle of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

A method for driving a display panel, wherein the display panel includes a plurality of pixel units arranged in multiple rows and multiple columns, each pixel unit includes a plurality of sub-pixel units, the display panel has at least one pixel unit group, each The pixel unit group includes at least two columns of pixel units, and the driving method includes:

During the writing of data signals to the sub-pixel units in the same row in each pixel unit group, the data signals are sequentially written to the sub-pixel units in chronological order, where the data signals are written successively in time. Each sub-pixel unit includes sub-pixel units from different pixel units, and M is an integer greater than 3.
The driving method according to claim 1, wherein the order in which the data signals are written into the sub-pixel units in any two adjacent pixel units in the same pixel unit group satisfies the following conditions:

Wherein, e i is the sequence number in which the data signal is written into the i-th sub-pixel unit in the first pixel unit of the two pixel units;

e j is the sequence number in which the data signal is written into the j-th sub-pixel unit in the second pixel unit of the two pixel units;

i, j, e i and e j are all positive integers, and 1≤i≤M, 1≤j≤M, 1≤e i ≤2M, 1≤e j ≤2M;

α is the preset threshold.
The driving method according to claim 2, wherein 0<α≦3.
The driving method according to claim 1, wherein each pixel unit group includes N pixel units, and the N sub-pixel units to which data signals are written consecutively in time belong to different pixel units, and N is an integer greater than 2.
The driving method according to any one of claims 1 to 4, wherein, in the same pixel unit group, the sub-pixel units of the same color are written in the same order of data signals.
A driving device for a display panel, wherein the display panel includes a plurality of pixel units arranged in multiple rows and multiple columns, each pixel unit includes a plurality of sub-pixel units, the display panel has at least one pixel unit group, each The pixel unit group includes at least two columns of pixel units, and the driving device is configured to:

During the writing of data signals to the sub-pixel units in the same row in each pixel unit group, the data signals are sequentially written to the sub-pixel units in chronological order, where the data signals are written successively in time. Each sub-pixel unit includes sub-pixel units from different pixel units, and M is an integer greater than 3.
7. The driving method according to claim 6, wherein the driving device is configured such that the order in which the data signals are written into the sub-pixel units in any two adjacent pixel units in the same pixel unit group meets the following conditions:

Wherein, e i is the sequence number in which the data signal is written into the i-th sub-pixel unit in the first pixel unit of the two pixel units;

e j is the sequence number in which the data signal is written into the j-th sub-pixel unit in the second pixel unit of the two pixel units;

i, j, e i and e j are all positive integers, and 1≤i≤M, 1≤j≤M, 1≤e i ≤2M, 1≤e j ≤2M;

α is the preset threshold.
The driving method according to claim 7, wherein 0<α≦3.
7. The driving method according to claim 6, wherein each pixel unit group includes N pixel units, and the N sub-pixel units to which data signals are successively written in time belong to different pixel units, and N is an integer greater than 2.
The driving method according to any one of claims 6 to 9, wherein, in the same pixel unit group, the sub-pixel units of the same color are written in the order of adjacent data signals.
A display device includes a display panel, a multiplexer circuit, and a gate controller. The display panel includes a plurality of pixel units arranged in multiple rows and multiple columns, and each pixel unit includes a plurality of sub-pixel units. The display panel has at least one pixel unit group, and each pixel unit group includes at least two columns of pixel units,

The multiplexer circuit is configured to control the writing of data signals to the sub-pixel units in each pixel unit group;

The strobe controller is configured to control the multiplexer circuit to perform the following operations: during the writing of data signals to the sub-pixel units in the same row in each pixel unit group, sequentially causing the The sub-pixel unit receives the data signal, wherein the M sub-pixel units connected in time to receive the data signal include sub-pixel units from different pixel units, and M is an integer greater than 3.
11. The display device according to claim 11, wherein the gate controller is configured to control the multiplexer circuit so that sub-pixel units of any two adjacent pixel units in the same pixel unit group receive data voltages The order meets the following conditions:

Wherein, e i is the sequence number in which the i-th sub-pixel unit in the first pixel unit of the two pixel units receives the data signal;

e j is the sequence number of the data signal received by the j-th sub-pixel unit of the second pixel unit of the two pixel units;

i, j, e i and e j are all positive integers, and 1≤i≤M, 1≤j≤M, 1≤e i ≤2M, 1≤e j ≤2M;

α is the preset threshold.
The display device according to claim 12, wherein 0<α≦3.
The display device according to any one of claims 11 to 13, wherein the strobe controller is configured to control the multiplexer circuit so that sub-pixel units of the same color in the same pixel unit group receive The order of the data signals is adjacent.
11. The display device according to claim 11, wherein the multiplexer circuit comprises at least one multiplexer, each multiplexer is connected to each sub-pixel unit of a pixel unit group, and is configured In response to a set of control signals, the data signal from the general input terminal is transferred to the corresponding sub-pixel unit.
15. The display device according to claim 15, wherein each multiplexer includes a plurality of switching elements, a first end of each switching element is connected to a column of sub-pixel units, and a second end of each switching element is connected to the The total input terminal, the control terminal of each switching element is connected to the corresponding control signal terminal.
16. The display device of claim 16, wherein the second ends of the plurality of switching elements of each multiplexer are connected to the same general input end.
The display device according to claim 16, wherein the multiplexer circuit comprises a first multiplexer and a second multiplexer, the first multiplexer and the second multiplexer The second end of the switching element connected to the odd-numbered column of the sub-pixel unit in the two multiplexers is connected to the first total input end, and the first multiplexer and the second multiplexer The second end of the switch element connected to the even-numbered column of the sub-pixel unit is connected to a second total input end, and the first total input end is different from the second total input end.
The display device according to claims 11 to 18, wherein each pixel unit group includes N pixel units, and the gate controller is configured to control the multiplexer circuit so that the data signal is received and connected in time The N sub-pixel units belong to different pixel units, and N is an integer greater than 2.