CN109742151B - Thin film transistor, manufacturing method thereof, array substrate and display panel - Google Patents
Thin film transistor, manufacturing method thereof, array substrate and display panel Download PDFInfo
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Abstract
The invention provides a thin film transistor and a manufacturing method thereof, an array substrate and a display panel, wherein the thin film transistor comprises a substrate, a grid electrode insulating layer, an active layer, a source electrode and a drain electrode, the grid electrode is arranged on the substrate, the grid electrode insulating layer is arranged on the grid electrode and the substrate, the active layer covers a part of the grid electrode insulating layer, the source electrode and the drain electrode are both arranged on the active layer and the grid electrode insulating layer, the active layer comprises a first active layer and a second active layer which are arranged in a stacking mode, the second active layer is in contact with the grid electrode insulating layer, the first active layer and the second active layer are indium-gallium-zinc oxide layers, the element proportion of indium, gallium and zinc in the first active layer is unequal, and the element proportion of indium, gallium and zinc in the first active layer is different from the element proportion of indium, gallium and zinc in. The invention can improve the reliability of the device.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a thin film transistor, a manufacturing method thereof, an array substrate and a display panel.
Background
Thin Film Transistors (TFTs) are the main driving elements in liquid crystal display devices, and are directly related to the development of high performance flat panel display devices. In order to realize high-resolution display, the size of the TFT device needs to be "miniaturized", and the realization of a Back Channel Etching (BCE) structure is the key to the "miniaturization" of the size of the TFT device. In addition, the BCE-TFT is simple in manufacturing process and low in cost. More importantly, the definition precision of the channel size is high, and the miniaturization of the device size is easy to realize.
In the manufacturing process of the conventional BCE-type thin film transistor, a metal thin film layer is deposited on an active layer and a gate insulating layer formed by an oxide semiconductor, and the metal thin film layer is subjected to patterned etching by using a dry etching process to obtain a source electrode, a drain electrode and a channel located between the source electrode and the drain electrode, that is, the metal thin film layer on the upper side of the oxide semiconductor layer is removed by using the dry etching process, so that a channel structure is manufactured. In the etching process of the source electrode and the drain electrode, the active layer is gradually exposed along with the etching and directly contacts with the etching medium.
In the manufacturing process, the oxide semiconductor surface layer under the metal film layer is directly contacted with the etching medium, so that the oxide semiconductor surface layer is easily damaged to generate byproducts, thereby causing unstable reliability of the oxide semiconductor and low reliability of the thin film transistor.
Disclosure of Invention
The invention provides a thin film transistor, a manufacturing method thereof, an array substrate and a display panel, which can improve the reliability of the thin film transistor.
In a first aspect, the present invention provides a thin film transistor, including a substrate, a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, wherein the gate electrode is disposed on the substrate, the gate insulating layer is disposed on the gate electrode and the substrate, the active layer covers a portion of the gate insulating layer, the source electrode and the drain electrode are both disposed on the active layer and the gate insulating layer, the active layer includes a first active layer and a second active layer which are stacked, the second active layer is in contact with the gate insulating layer, the first active layer and the second active layer are both indium gallium zinc oxide layers, the element proportions of indium, gallium and zinc in the first active layer are not equal, and the element proportions of indium, gallium and zinc in the first active layer are different from the element proportions of indium, gallium and zinc in the second active layer.
In a second aspect, the present invention provides an array substrate, including the above thin film transistor.
In a third aspect, the present invention provides a display panel, which includes a color film substrate, a liquid crystal layer and the array substrate, wherein the liquid crystal layer is sandwiched between the color film substrate and the array substrate.
In a fourth aspect, the present invention provides a method for manufacturing a thin film transistor, including: sequentially depositing a grid electrode and a grid electrode insulating layer on a substrate; sequentially forming a second active layer and a first active layer on the gate insulating layer, wherein the first active layer and the second active layer are indium-gallium-zinc oxide layers, and the first active layer and the second active layer jointly form the active layer, wherein the element proportions of indium, gallium and zinc in the first active layer are different, and the element proportions of indium, gallium and zinc in the first active layer are different from the element proportions of indium, gallium and zinc in the second active layer; and forming a source electrode and a drain electrode on the active layer and the gate insulating layer.
The thin film transistor comprises a substrate, a grid electrode insulating layer, an active layer, a source electrode and a drain electrode, wherein the grid electrode is arranged on the substrate, the grid electrode insulating layer is arranged on the grid electrode and the substrate, the active layer covers part of the grid electrode insulating layer, the source electrode and the drain electrode are both arranged on the active layer and the grid electrode insulating layer, the active layer comprises a first active layer and a second active layer which are arranged in a stacking mode, the second active layer is in contact with the grid electrode insulating layer, the first active layer and the second active layer are indium-gallium-zinc oxide layers, the element proportion of indium, gallium and zinc in the first active layer is unequal, and the element proportion of indium, gallium and zinc in the first active layer is different from the element proportion of indium, gallium and zinc in the second active layer. The active layer is divided into a first active layer which bears etching damage and a second active layer which is located below the first active layer and does not bear etching damage. Therefore, the second active layer is effectively protected by the first active layer, and the reliability of the thin film transistor can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a bias test result of a thin film transistor according to an embodiment of the present invention;
fig. 3 is a schematic flow chart illustrating a method for manufacturing a thin film transistor according to a second embodiment of the present invention;
fig. 4a to fig. 4g are schematic process diagrams illustrating a detailed manufacturing method of a thin film transistor according to a second embodiment of the invention.
Description of reference numerals:
10-a thin film transistor;
20-a substrate;
30-a gate;
40-a gate insulating layer;
50-an active layer;
51 — a first active layer;
52-a second active layer;
60-a source;
70-a drain electrode;
80-a passivation layer;
90-pixel electrode;
91-through hole.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
Fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention. As shown in fig. 1, the thin film transistor 10 of the present embodiment includes a substrate 20, a gate electrode 30, a gate insulating layer 40, an active layer 50, a source electrode 60, and a drain electrode 70, wherein the gate electrode 30 is disposed on the substrate 20, the gate insulating layer 40 is disposed on the gate electrode 30 and the substrate 20, the active layer 50 covers a portion of the gate insulating layer 40, the source electrode 60 and the drain electrode 70 are both disposed on the active layer 50 and the gate insulating layer 40, the active layer 50 includes a first active layer 51 and a second active layer 52 which are stacked, the second active layer 52 is in contact with the gate insulating layer 40, the first active layer 51 and the second active layer 52 are both indium-gallium-zinc oxide layers, and the element ratios of indium, gallium, and zinc in the first active layer 51 are not equal, and the element ratios of indium, gallium, and zinc in the first active layer 51 are different from the element ratios of indium, gallium, and zinc in the second active layer 52.
In the above-described configuration, the active portion 50 located between the source electrode 60 and the drain electrode 70 constitutes a channel portion of the thin film transistor 10. In addition, optionally, the active layer 50 covers a portion of the gate insulating layer 40, specifically, the active layer 50 is located at a position corresponding to the gate 30.
By providing the active layer 50 as two layers of the first active layer 51 and the second active layer 52, the element ratios of indium, gallium, and zinc in the first active layer 51 are not equal, and the element ratios of indium, gallium, and zinc in the first active layer 51 and the element ratios of indium, gallium, and zinc in the second active layer 52 are different, the active layer 50 can be divided into the first active layer 51 which is subject to etching damage and the second active layer 52 which is located below the first active layer 51 and is not subject to etching damage. In this way, the second active layer 52 is effectively protected by the first active layer 51, and thus the reliability of the thin film transistor can be improved.
Specifically, the active layer in the prior art is an indium gallium zinc oxide layer, which is used as a novel display material and has the characteristics of high carrier mobility, good turn-off characteristics, easy industrial production and the like, but when the source electrode and the drain electrode are manufactured by a dry etching process, the characteristics of the shallow surface layer of the indium gallium zinc oxide layer are inevitably affected by an etching medium, so that the characteristics of the indium gallium zinc oxide layer are changed, and the stability of the array substrate is deteriorated.
In the present embodiment, the first active layer 51 is disposed close to the source electrode 60 and the drain electrode 70, and in the process of forming the source electrode 60 and the drain electrode 70 by removing the metal above the first active layer 51 (above the channel portion) through etching, because the element proportions of indium, gallium, and zinc in the first active layer 51 are not equal, the first active layer 51 thus formed can resist the erosion of the etching medium during the etching process, so as to form a protective layer of the active layer 50, and therefore, in the etching process of the source electrode 60 and the drain electrode 70, the active layer 50 is not damaged, so that the performance stability of the active layer 50 is ensured, and the reliability of the thin film transistor can be improved.
Further optimization of the layers of the active layer 50 can make the elemental proportions of indium, gallium and zinc in the second active layer 52 equal, i.e. the elemental proportions of indium, gallium and zinc in the second active layer 52 are 1: 1: 1, which can ensure stable performance of the second active layer 52.
Further, alternatively, the elemental ratio of Indium (Indium), Gallium (galium), and Zinc (Zinc) in the first active layer 51 is 1: (2-5): (2-8). That is, when the ratio of indium is set to 1, the composition of gallium and zinc satisfies: gallium is more than or equal to 2 and less than or equal to 5, and zinc is more than or equal to 2 and less than or equal to 8. The first active layer 51 with the above composition ratio can effectively resist the corrosion of the etching medium during the etching process, so that the damage of the etching medium to the active portion 50 can be reduced, and the stability of the thin film transistor 10 can be improved.
In the present application, the element ratio of indium, gallium and zinc, that is, the atomic ratio or the atomic weight ratio of indium, gallium and zinc. Specifically, the element ratio of indium, gallium, and zinc refers to a molar ratio of indium element, gallium element, and zinc element, or refers to a ratio of indium element, gallium element, and zinc element in each of the first active layer and the second active layer in terms of mass percentage. For example, the elemental ratio of indium, gallium, and zinc in the first active layer 51 is 1: (2-5): (2-8), specifically, the molar ratio of indium element, gallium element and zinc element in the first active layer 51 is 1: (2-5): (2-8), or the ratio of the indium element, the gallium element and the zinc element in the first active layer in percentage by mass is 1: (2-5): (2-8). And the elemental ratio of indium, gallium and zinc in the second active layer 52 is 1: 1: 1, specifically, the molar ratio of indium element, gallium element, and zinc element in the second active layer 52 is 1: 1: 1, or the ratio of the indium element, the gallium element, and the zinc element in the second active layer 52 is 1: 1: 1.
in addition, as shown in fig. 1, the coverage areas of the first and second active layers 51 and 52 are the same. In other words, the first active layer 51 and the second active layer 52 have the same shape and size when viewed from the top, which ensures that the first active layer 51 completely covers the second active layer 52 and better protects the second active layer 52. Of course, the present invention is not limited thereto, and the coverage area of the first active layer 51 may be larger than that of the second active layer 52 as long as the first active layer 51 can play a role of protecting the second active layer 52.
In addition, optionally, the substrate 20 may be a glass substrate, the gate electrode 30, the source electrode 60, and the drain electrode 70 are formed of a metal, and the metal used for the gate electrode 30, the source electrode 60, and the drain electrode 70 may be at least one selected from Cu, Al, Mo, Ti, Nb, and Ag. Of course, the metal forming the gate layer, the source, and the drain may be one of Cu, Al, Mo, Ti, Nb, and Ag, or a combination of two or more of Cu, Al, Mo, Ti, Nb, and Ag. The gate insulating layer 40 is a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a composite layer formed by stacking a silicon oxide layer and a silicon nitride layer.
In order to further reduce the damage to the active layer 50 caused by the etching process, the source electrode 60 and the drain electrode 70 may be selectively formed by wet etching. The etching agent for dry etching is plasma, and is a process for forming volatile substances by utilizing the reaction of the plasma and the surface of an active layer or directly bombarding the surface of the active layer to corrode the active layer, but in the etching process, an etching medium easily damages the surface layer of the active layer; the wet etching is an etching method for stripping an etched substance by chemical reaction between chemical etching liquid and the surface of an active layer, and the method has strong adaptability, good surface uniformity and small damage to the surface of the active layer. Therefore, in this embodiment, while the first active layer 51 is provided as a protective layer for the active layer 50, the dry etching is replaced by the wet etching, and damage to the active layer 50 can be further reduced.
Further, since the source and drain wirings are formed by etching in the same process as the source and drain electrodes 60 and 70, the source and drain wirings are also formed by wet etching.
In addition, as shown in fig. 1, a passivation layer 80 and a pixel electrode 90 are optionally further disposed on the gate insulating layer 40, the active layer 50, the source electrode 60 and the drain electrode 70. Specifically, a passivation layer 80 is formed on the gate insulating layer 40, the active layer 50, the source electrode 60, and the drain electrode 70, a through hole 91 is further formed on the passivation layer 80 at a position corresponding to the drain electrode 70, and a pixel electrode 90 is formed on the passivation layer 80, the pixel electrode 90 being connected to the drain electrode 70 via the through hole 91.
In the present embodiment, the element ratio of indium, gallium, and zinc in the first active layer 51 is 1: (2-5): (2-8), wherein the element ratio of indium, gallium and zinc in the second active layer 52 is 1: 1: the thin film transistor 10 of 1 was subjected to a bias test.
Fig. 2 is a graph showing the results of a bias test of a thin film transistor according to an embodiment of the present invention, and table 1 shows the values of threshold voltage shift when the active layers are respectively formed of a single layer in the related art and the first active layer 51 and the second active layer 52 (double layers) having the above-mentioned specific composition ratio. In fig. 2, the vertical axis represents the threshold voltage shift amount (unit: V) of the thin film transistor, the hatched pattern represents the Positive threshold voltage shift in the Positive Bias Temperature test (PBT), and the open pattern represents the Negative threshold voltage shift in the Negative Bias Temperature test (PBT).
Table one:
| single layer threshold voltage drift (V) | Double layer threshold Voltage Drift (V) | |
| Positive bias temperature test | 2.48 | 1.26 |
| Negative bias temperature test | -6.46 | -3.31 |
As can be seen from fig. 2 and table one, when the active layer 50 is changed from a single layer to a double layer consisting of the first active layer 51 and the second active layer 52 of the above-mentioned specific composition ratio, the threshold voltage drift is reduced from 2.48V to 1.26V in the positive direction and from 6.46V to 3.31V in the negative direction, and thus it can be seen that when the active layer 50 is changed from a single layer to a double layer consisting of the first active layer 51 and the second active layer 52 of the above-mentioned specific composition ratio, the threshold voltage drift of the thin film transistor is significantly reduced, whereby the characteristics of the device consisting of the thin film transistor, such as a liquid crystal display panel, etc., can be significantly improved.
In addition, the gist of the present invention is that, in the structure of a BCE-type thin film transistor, a first active layer and a second active layer having different element composition ratios are formed by double-layering an oxide semiconductor constituting a channel portion between a source electrode and a drain electrode, and in this example, the element ratios of indium, gallium, and zinc in the first active layer are 1: (2-5): (2-8), wherein the element proportion of indium, gallium and zinc in the second active layer is 1: 1: the present invention is not limited to the example 1, and the object of the present invention can be achieved as long as the element ratios of indium, gallium and zinc in the first active layer and the element ratios of indium, gallium and zinc in the second active layer are different, that is, the active layers are divided into a first active layer subject to etching damage and a second active layer not subject to etching damage.
In this embodiment, the thin film transistor includes a substrate, a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode, the gate electrode is disposed on the substrate, the gate insulating layer is disposed on the gate electrode and the substrate, the active layer covers a portion of the gate insulating layer, the source electrode and the drain electrode are both disposed on the active layer and the gate insulating layer, the active layer includes a first active layer and a second active layer that are stacked, the second active layer is in contact with the gate insulating layer, the first active layer and the second active layer are both indium-gallium-zinc oxide layers, the element ratios of indium, gallium, and zinc in the first active layer are not equal, and the element ratios of indium, gallium, and zinc in the first active layer are different from the element ratios of indium, gallium, and zinc in the second active layer. In this embodiment, the active layer is configured as two layers, i.e., a first active layer and a second active layer, the element proportions of indium, gallium and zinc in the first active layer are not equal, and the element proportions of indium, gallium and zinc in the first active layer are different from the element proportions of indium, gallium and zinc in the second active layer, so that the active layer can be divided into the first active layer which is damaged by etching and the second active layer which is located below the first active layer and is not damaged by etching. Therefore, the second active layer is effectively protected by the first active layer, and the reliability of the thin film transistor can be improved.
Example two
The method for manufacturing a thin film transistor provided in this embodiment can be used to manufacture the thin film transistor 10 described in the first embodiment. The detailed structure and function of the thin film transistor 10 have been described in detail in the first embodiment, and are not described herein again. Fig. 3 is a schematic flow chart of a manufacturing method of a thin film transistor according to a second embodiment of the present invention. As shown in fig. 3, the method for manufacturing a thin film transistor provided in this embodiment may specifically include the following steps:
s11, sequentially depositing a grid electrode and a grid electrode insulating layer on the substrate;
s12, sequentially forming a second active layer and a first active layer on the gate insulating layer; the first active layer and the second active layer are indium-gallium-zinc oxide layers and jointly form the active layer, wherein the element proportions of indium, gallium and zinc in the first active layer are different, and the element proportions of indium, gallium and zinc in the first active layer are different from the element proportions of indium, gallium and zinc in the second active layer.
And S13, forming a source electrode and a drain electrode on the active layer and the gate insulating layer.
As described above, since the first active layer is disposed close to the source electrode and the drain electrode, in the process of forming the source electrode and the drain electrode by removing the metal of the first active layer above the channel portion through etching, the elemental proportions of indium, gallium, and zinc in the first active layer are not equal, and thus, the etching medium erosion in the etching process can be resisted, and therefore, in the etching process of the source electrode and the drain electrode, the active layer is not damaged, the performance stability of the active layer can be ensured, and the reliability of the thin film transistor can be improved.
Optionally, forming a source and a drain on the active layer and the gate insulating layer specifically includes: and forming a source electrode and a drain electrode on the active layer and the gate insulating layer by wet etching. Compared with dry etching, wet etching can further reduce the damage of the etching process to the active layer, so that the source electrode and the drain electrode are formed by wet etching. Since the source and drain wirings are formed by etching in the same process as the source and drain, the source and drain wirings are also formed by wet etching.
A specific example is given below to describe the manufacturing process of the thin film transistor in this embodiment, and fig. 4a to 4g are schematic diagrams illustrating the detailed process of the manufacturing method of the thin film transistor according to the second embodiment of the present invention. The manufacturing method comprises the following steps:
a) as shown in fig. 4a, a substrate 20 is provided and a gate 30 is formed on the substrate 20.
Specifically, a first metal film is deposited on the substrate 20, and the gate 30 is obtained after patterning the first metal film by wet etching.
b) As shown in fig. 4b, a gate insulating layer 40 is formed on the substrate 20 and the gate electrode 30.
Specifically, the gate insulating layer 40 is deposited by a chemical vapor deposition method.
c) As shown in fig. 4c, a second active layer 52 is formed on the gate insulating layer 40; the second active layer 52 is an indium gallium zinc oxide layer, and the element ratio of indium, gallium, and zinc in the second active layer 52 is 1: 1: 1.
d) as shown in fig. 4d, a first active layer 51 is formed on the second active layer 52; the first active layer 51 is also an indium gallium zinc oxide layer, and the element ratio of indium, gallium, and zinc in the first active layer 51 is 1: (2-5): (2-8). The first active layer 51 and the second active layer 52 together constitute the active layer 50.
e) As shown in fig. 4e, the source electrode 60 and the drain electrode 70 are formed on the active layer 50 (first active layer 51) and the gate insulating layer 40.
Specifically, a second metal film is deposited on the first active layer 51 and the gate insulating layer 40 in the active layer 50, and is etched by wet etching, so that the source electrode 60 and the drain electrode 70 are located on the active layer 50 and the gate insulating layer 40, and the active layer 50 between the source electrode 60 and the drain electrode 70 is formed as a channel portion.
f) As shown in fig. 4f, a passivation layer 80 is formed on the gate insulating layer 40, the source electrode 60, the drain electrode 70, and the active layer 50, and a through-hole 91 is formed on the passivation layer 80 at a position corresponding to the drain electrode 70.
g) As shown in fig. 4g, a pixel electrode 90 is formed on the passivation layer 80, and the pixel electrode 90 is connected to the drain electrode 70 via the through hole 91. Specifically, the material of the pixel electrode 90 may be indium tin oxide.
The elemental ratio of indium, gallium, and zinc in the second active layer 52 is 1: 1: 1, which can ensure stable performance of the second active layer 52. In addition, the elemental ratio of indium, gallium, and zinc in the first active layer 51 is 1: (2-5): (2-8). The first active layer 51 having the above composition ratio can effectively resist the corrosion of the etching medium during the etching process, so that the damage of the etching medium to the active portion 50 can be reduced, and the characteristic stability of the thin film transistor 10 can be improved.
In this embodiment, the element ratios of indium, gallium, and zinc in the first active layer are listed as 1: (2-5): (2-8), wherein the element proportion of indium, gallium and zinc in the second active layer is 1: 1: the present invention is not limited to the example 1, and the object of the present invention can be achieved as long as the element ratios of indium, gallium and zinc in the first active layer and the element ratios of indium, gallium and zinc in the second active layer are different, that is, the active layers are divided into a first active layer subject to etching damage and a second active layer not subject to etching damage.
In addition, optionally, the substrate 20 may be a glass substrate, the gate electrode 30, the source electrode 60, and the drain electrode 70 are formed of a metal, and the metal used for the gate electrode 30, the source electrode 60, and the drain electrode 70 may be at least one selected from Cu, Al, Mo, Ti, Nb, and Ag. Of course, the metal forming the gate layer, the source, and the drain may be one of Cu, Al, Mo, Ti, Nb, and Ag, or a combination of two or more of Cu, Al, Mo, Ti, Nb, and Ag. The gate insulating layer 40 is a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a composite layer formed by stacking a silicon oxide layer and a silicon nitride layer.
In this embodiment, the method for manufacturing a thin film transistor includes: sequentially depositing a grid electrode and a grid electrode insulating layer on a substrate; sequentially forming a second active layer and a first active layer on the gate insulating layer, wherein the first active layer and the second active layer are indium-gallium-zinc oxide layers, and the first active layer and the second active layer jointly form the active layer, wherein the element proportions of indium, gallium and zinc in the first active layer are different, and the element proportions of indium, gallium and zinc in the first active layer are different from the element proportions of indium, gallium and zinc in the second active layer; and forming a source electrode and a drain electrode on the active layer and the gate insulating layer. Because the first active layer is arranged close to the source electrode and the drain electrode, in the process of forming the source electrode and the drain electrode by removing metal of the first active layer above the channel part through etching, the element proportion of indium, gallium and zinc in the first active layer is unequal, so that the corrosion of an etching medium in the etching process can be resisted, the active layer cannot be damaged in the etching process of the source electrode and the drain electrode, the performance stability of the active layer can be ensured, and the reliability of the thin film transistor can be improved.
EXAMPLE III
An aspect of the present embodiment provides an array substrate, which includes the thin film transistor 10 described in the first embodiment, wherein the detailed structure and function of the thin film transistor 10 have been described in detail in the first embodiment, and thus are not described herein again. In addition, the manufacturing method of the array substrate may refer to the method of the second embodiment, and details are not repeated here.
In the thin film transistors included in the array substrates, the active layers are arranged as the first active layer and the second active layer, the element proportions of indium, gallium and zinc in the first active layer are not equal, and the element proportions of indium, gallium and zinc in the first active layer are different from the element proportions of indium, gallium and zinc in the second active layer, so that the active layers can be divided into the first active layer capable of bearing etching damage and the second active layer which is positioned below the first active layer and does not bear etching damage. In this way, the second active layer is effectively protected by the first active layer, so that the reliability of the thin film transistor can be improved, and the array substrate provided by the embodiment has higher reliability.
Example four
The present embodiment provides a display panel, including the array substrate described in the third embodiment, where the display panel may be an OLED display panel or a liquid crystal display panel, where when the display panel is an OLED display panel, the array substrate is further provided with an organic light emitting unit, and when the display panel is a liquid crystal display panel, the display panel further includes a color film substrate, and a liquid crystal layer is disposed between the array substrate and the color film substrate.
In another aspect of this embodiment, a display device is further provided, which includes the display panel, and the display device may be a flexible display device, where in this embodiment, the display device may be any component having a display function, such as electronic paper, a tablet computer, a liquid crystal display, a liquid crystal television, a digital photo frame, and a mobile phone.
In the display panel and the display device provided in this embodiment, since the active layers are provided as two layers, i.e., the first active layer and the second active layer, in the thin film transistor included in the display panel and the display device, the element ratios of indium, gallium, and zinc in the first active layer are not equal, and the element ratios of indium, gallium, and zinc in the first active layer and the element ratios of indium, gallium, and zinc in the second active layer are different, the active layers can be divided into the first active layer capable of withstanding etching damage and the second active layer located below the first active layer and not withstanding etching damage. In this way, the second active layer is effectively protected by the first active layer, so that the reliability of the thin film transistor can be improved, and thus the display panel and the display device provided by the embodiment have higher reliability.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
In addition, in the present invention, unless otherwise explicitly specified or limited, the terms "connected," "fixed," "mounted," and the like are to be construed broadly, e.g., as mechanical or electrical connections; the terms may be directly connected or indirectly connected through an intermediate, and may be used for communicating between two elements or for interacting between two elements, unless otherwise specifically limited, and the specific meaning of the terms in the present invention will be understood by those skilled in the art according to specific situations.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A thin film transistor is characterized by comprising a substrate, a grid electrode insulating layer, an active layer, a source electrode and a drain electrode, wherein the grid electrode is arranged on the substrate, the grid electrode insulating layer is arranged on the grid electrode and the substrate, the active layer covers a part of the grid electrode insulating layer, the source electrode and the drain electrode are both arranged on the active layer and the grid electrode insulating layer, the active layer comprises a first active layer and a second active layer which are arranged in a stacking mode, the second active layer is in contact with the grid electrode insulating layer, the first active layer and the second active layer are indium-gallium-zinc oxide layers, the first active layer and the second active layer are both composed of indium, gallium, zinc and oxygen, the element proportion of indium, gallium and zinc in the first active layer is not equal, and indium in the first active layer is not equal, The element proportion of gallium and zinc is different from the element proportion of indium, gallium and zinc in the second active layer;
the element proportion of indium, gallium and zinc in the first active layer is 1: (2-5): 8;
the element proportions of indium, gallium and zinc in the second active layer are all equal.
2. The thin film transistor according to claim 1, wherein the first active layer and the second active layer have the same coverage area.
3. The thin film transistor according to claim 1 or 2, wherein the source electrode and the drain electrode are formed by wet etching.
4. The thin film transistor according to claim 1 or 2, wherein a passivation layer and a pixel electrode are further provided on the gate insulating layer, the active layer, the source electrode, and the drain electrode.
5. An array substrate comprising the thin film transistor according to any one of claims 1 to 4.
6. A display panel, comprising a color film substrate, a liquid crystal layer and the array substrate of claim 5, wherein the liquid crystal layer is sandwiched between the color film substrate and the array substrate.
7. A method for manufacturing a thin film transistor includes:
sequentially depositing a grid electrode and a grid electrode insulating layer on a substrate;
sequentially forming a second active layer and a first active layer on the gate insulating layer, wherein the first active layer and the second active layer are indium-gallium-zinc oxide layers, the first active layer and the second active layer are formed by indium element, gallium element, zinc element and oxygen element, and the first active layer and the second active layer jointly form the active layer, wherein the element proportions of indium, gallium and zinc in the first active layer are different, and the element proportions of indium, gallium and zinc in the first active layer are different from the element proportions of indium, gallium and zinc in the second active layer;
forming a source electrode and a drain electrode on the active layer and the gate insulating layer;
the element proportion of indium, gallium and zinc in the first active layer is 1: (2-5): 8;
the element proportions of indium, gallium and zinc in the second active layer are all equal.
8. The method for manufacturing a thin film transistor according to claim 7, wherein the forming of the source electrode and the drain electrode on the active layer and the gate insulating layer specifically comprises:
and forming the source electrode and the drain electrode on the active layer and the gate insulating layer by wet etching.
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| CN112864231A (en) * | 2021-01-28 | 2021-05-28 | 合肥维信诺科技有限公司 | Thin film transistor, preparation method thereof, array substrate and display panel |
| CN113838759A (en) * | 2021-07-29 | 2021-12-24 | 信利半导体有限公司 | Manufacturing method of thin film transistor, thin film transistor and electronic equipment |
| CN113764282B (en) * | 2021-09-03 | 2023-09-05 | 深圳市华星光电半导体显示技术有限公司 | Back channel etched thin film transistor and method for fabricating the same |
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