CN109727921A - Array substrate and production method, display panel - Google Patents
Array substrate and production method, display panel Download PDFInfo
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- CN109727921A CN109727921A CN201910001472.1A CN201910001472A CN109727921A CN 109727921 A CN109727921 A CN 109727921A CN 201910001472 A CN201910001472 A CN 201910001472A CN 109727921 A CN109727921 A CN 109727921A
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- 239000000758 substrate Substances 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title abstract description 36
- 238000000137 annealing Methods 0.000 claims abstract description 131
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 80
- 229920005591 polysilicon Polymers 0.000 claims abstract description 78
- 239000010409 thin film Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 38
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims description 14
- 238000003860 storage Methods 0.000 claims description 13
- 230000002093 peripheral effect Effects 0.000 claims description 10
- 230000005611 electricity Effects 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 abstract description 17
- 238000005224 laser annealing Methods 0.000 description 9
- 239000010408 film Substances 0.000 description 7
- 238000002425 crystallisation Methods 0.000 description 5
- 230000008025 crystallization Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- Thin Film Transistor (AREA)
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Abstract
The invention discloses array substrate and production methods, display panel.This method comprises: providing substrate, the ceiling substrate has viewing area surely, and along symmetrically arranged first periphery circuit region in the viewing area and the second periphery circuit region；And thin film transistor (TFT) is set in first periphery circuit region of the substrate and second periphery circuit region, the step of setting thin film transistor (TFT) includes: in first periphery circuit region and second periphery circuit region setting amorphous silicon layer, the amorphous silicon layer is made annealing treatment, to form polysilicon layer, wherein, it is identical as the annealing mask plate of second periphery circuit region is applied to applied to the annealing mask plate of first periphery circuit region.The first periphery circuit region and the second periphery circuit region use identical annealing mask plate as a result, it is possible to reduce the replacement number for mask plate of annealing reduces preparation difficulty, improves working efficiency, reduces production cost.
Description
Technical field
The present invention relates to field of display technology, and in particular, to array substrate and production method, display panel.
Background technique
Low temperature polycrystalline silicon (LTPS) mobility with higher, is suitably applied in the array substrate of current drive-type.Mesh
The preparation of preceding array substrate polysilicon, generallys use low-temperature polysilicon silicon technology, wherein the preparation of polysilicon in periphery circuit region
Process is generally as follows: firstly, preparing one layer of amorphous silicon layer in array substrate then passes through compartmentalization laser annealing techniques
(MLA) amorphous silicon layer is made annealing treatment, to form polysilicon, the active layer as thin film transistor (TFT) is used.Remove display
Other than thin film transistor (TFT) in area for controlling each sub-pixel, also there are multiple films in the periphery circuit region of non-display area
Transistor constitutes control circuit with other electronic components, to control the thin film transistor (TFT) in viewing area.Peripheral circuit generally along
Viewing area is symmetricly set on its two sides, and the element in the peripheral circuit of viewing area two sides, usually in mirror symmetry arrangement.
Therefore, when carrying out compartmentalization laser annealing, then need to introduce a variety of annealing mask plates.
However, current array substrate and production method, display panel still have much room for improvement.
Summary of the invention
The present invention is directed to alleviate or solve the problems, such as at least one in above-mentioned refer at least to some extent.
In one aspect of the invention, the invention proposes a kind of methods for making array substrate.This method comprises: providing
Substrate, the ceiling substrate have viewing area surely, and along symmetrically arranged first periphery circuit region in the viewing area and second
Periphery circuit region；And it is brilliant in first periphery circuit region of the substrate and second periphery circuit region setting film
The step of body pipe, the setting thin film transistor (TFT) includes: in first periphery circuit region and second periphery circuit region
Amorphous silicon layer is set, the amorphous silicon layer is made annealing treatment, to form polysilicon layer, wherein is applied to described first week
The annealing mask plate of side circuit region is identical as the annealing mask plate of second periphery circuit region is applied to.First periphery as a result,
Circuit region and the second periphery circuit region use identical annealing mask plate, it is possible to reduce the replacement number for mask plate of annealing reduces
Difficulty is prepared, working efficiency is improved, reduces production cost.
According to an embodiment of the invention, the polysilicon layer in first periphery circuit region is relative to the first periphery electricity
Position one of the polysilicon layer relative to second periphery circuit region in the position in road area, with second periphery circuit region
It causes.Thus, it is possible to the crystallization complexity of periphery circuit region be effectively reduced, so that the first periphery circuit region and the second peripheral circuit
Area can form polysilicon layer using identical annealing operation, shorten manufacturing cycle, improve work efficiency.
According to an embodiment of the invention, the annealing mask plate has hollowed out area, have in first periphery circuit region
There is the first presumptive area, the area of the hollowed out area is greater than the area of first presumptive area, first presumptive area
It is configurable for forming the thin film transistor (TFT), carrying out the annealing in first periphery circuit region includes: to enable institute
The orthographic projection of the hollowed out area of annealing mask plate on the substrate is stated, first presumptive area is covered.As a result, based on above-mentioned
The polysilicon layer that mask plate of annealing is formed, can be etched to form multiple active layers in the next steps, in two periphery circuit regions
Multiple active layers relative position can multiple active layers in identical or two periphery circuit regions be symmetrical arranged.
According to an embodiment of the invention, to the polysilicon of first periphery circuit region and second periphery circuit region
Layer performs etching processing, wherein applied to the etch mask version in first periphery circuit region, and applied to the second week
Etch mask version in the circuit region of side is identical.It can be formed after the etched processing of polysilicon layer in two periphery circuit regions as a result,
Multiple active layers, and position of the active layer in the first periphery circuit region relative to the first periphery circuit region, with the second periphery electricity
Active layer in the area of road is identical relative to the position of the second periphery circuit region.
According to an embodiment of the invention, the area of the hollowed out area is at least the two of the first presumptive area area
Times, the method further includes: to the polysilicon layer of first periphery circuit region and second periphery circuit region into
Row etching processing, wherein electric with second periphery is applied to applied to the etch mask version in first periphery circuit region
Etch mask version in the area of road is mutually symmetrical with.It can be formed after the etched processing of polysilicon layer in two periphery circuit regions as a result,
There are multiple active layer, and the active layer in the active layer and the second periphery circuit region in the first periphery circuit region is symmetrical arranged, improves
The problem of currently forming brought by symmetrically arranged active layer frequently replacement annealing mask plate, in other words, utilization is identical
Annealing mask plate can also form the active layer being symmetrical set.
According to an embodiment of the invention, the annealing mask plate has hollowed out area, have in first periphery circuit region
There is the first presumptive area, the area of the hollowed out area is less than the area of first presumptive area, first presumptive area
It is configurable for forming the thin film transistor (TFT), which comprises it is based on the annealing mask plate, it is predetermined to described first
The amorphous silicon layer in region carries out the repeatedly annealing, wherein the position of the multiple annealing is different.It is based on as a result,
Multiple polysilicon layers that repeatedly annealing is formed constitute the first presumptive area, and in the next steps, above-mentioned polysilicon layer can lead to
Over etching forms multiple active layers, relative position of the active layer in the first periphery circuit region, and in the second periphery circuit region
Relative position it is consistent.
In another aspect of this invention, the invention proposes a kind of array substrates.According to an embodiment of the invention, the array
Substrate is made by mentioned-above method.The array substrate has the array substrate of mentioned-above method production as a result,
Whole features and advantage, details are not described herein.Generally speaking, which has that preparation process is simple, the production cycle
Short and low production cost advantage.
In another aspect of this invention, the invention proposes a kind of array substrates.According to an embodiment of the invention, the array
Substrate includes: substrate, and the ceiling substrate has viewing area surely, and along symmetrically arranged first peripheral circuit in the viewing area
Area and the second periphery circuit region；And first periphery of the substrate is arranged in thin film transistor (TFT), the thin film transistor (TFT)
Circuit region and second periphery circuit region, wherein the thin film transistor (TFT) in first periphery circuit region is relative to described
Thin film transistor (TFT) in the position of first periphery circuit region, with second periphery circuit region is relative to second peripheral circuit
The position consistency in area.The array substrate has the advantages that manufacturing process is simple, with short production cycle and production cost is low as a result,.
According to an embodiment of the invention, the array substrate further comprises: storage capacitance is located at first peripheral circuit
Position of the storage capacitance relative to first periphery circuit region in area, with the storage being located in second periphery circuit region
Position consistency of the capacitor relative to second periphery circuit region.Thus, it is possible to make storage capacitance and corresponding film crystal
Pipe matches.
In another aspect of this invention, the invention proposes a kind of display panels.According to an embodiment of the invention, the display
Panel includes mentioned-above array substrate.Generally speaking, the display panel have manufacturing process it is simple, it is with short production cycle and
The low advantage of production cost.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1 shows the flow diagram of production array substrate method according to an embodiment of the invention；
Fig. 2 shows the vertical section structure schematic diagram of array substrate in the prior art；
Fig. 3 shows the top view of array substrate in the prior art；
Fig. 4 shows the structural schematic diagram of array substrate according to an embodiment of the invention；
Fig. 5 shows the top view of array substrate according to an embodiment of the invention；
Fig. 6 shows the top view of annealing mask plate according to an embodiment of the invention；
Fig. 7 shows the top view of annealing mask plate in accordance with another embodiment of the present invention；
Fig. 8 shows the top view of array substrate according to an embodiment of the invention；
Fig. 9 shows the top view of array substrate in accordance with another embodiment of the present invention；
Figure 10 shows the top view of array substrate in accordance with another embodiment of the present invention；And
Figure 11 shows the top view of array substrate in accordance with another embodiment of the present invention.
Description of symbols:
100: substrate；110: viewing area；121: the first periphery circuit regions；122: the second periphery circuit regions；200: amorphous silicon
Layer；300: polysilicon layer；400: annealing mask plate；410: hollowed out area；500: active layer；10: the first presumptive areas；20: the
One symmetrical region；30: the first circuits；40: second circuit.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and for explaining only the invention, and is not considered as limiting the invention.
In one aspect of the invention, the invention proposes a kind of methods for making array substrate.As previously mentioned, current battle array
Circuit in column substrate periphery circuit region is in mirror settings.Specifically, array substrate includes viewing area and periphery circuit region, show
Show the circuit in the periphery circuit region of the symmetrical two sides in area in mirror settings, in other words, the peripheral circuit of the symmetrical two sides in viewing area
The active layer of thin film transistor (TFT) in area is also in mirror settings, specifically, with reference to Fig. 2 and Fig. 3, current array substrate packet
Include: substrate 100 and setting amorphous silicon layer 200 on the substrate 100 define viewing area 110 and periphery electricity on substrate 100
Road area, periphery circuit region include along symmetrically arranged first periphery circuit region 121 in viewing area 110 and the second periphery circuit region
122.Wherein, it is arranged in the amorphous silicon layer 200 in the first periphery circuit region 121 and the second periphery circuit region 122, has and pass through
The polysilicon layer 300 that compartmentalization laser annealing processing is formed, and the polysilicon layer 300 in the first periphery circuit region 121, with second
Polysilicon layer 300 in periphery circuit region 122 is symmetrical set.Utilizing compartmentalization laser annealing techniques symmetrical to viewing area two
When the amorphous silicon layer of side is made annealing treatment, since the active layer of two sides is mirror settings, two sides are used to form polysilicon
Annealing mask plate it is different, after the annealing for completing side, need using new annealing mask plate, to another symmetrical side
Amorphous silicon layer made annealing treatment, not only increase new annealing mask plate, also add annealing mask plate replacement number,
Preparation difficulty is increased, manufacturing cycle is extended, reduces working efficiency, increases production cost.
Although using quasi-molecule laser annealing technology (ELA) carry out annealing can to avoid annealing mask plate use,
However due to there is reirradiation using the process of this method preparation periphery circuit region polysilicon, the polycrystalline resulted in
Silicon is uneven, that is, passes through the crystallite dimension for the polysilicon that reirradiation region is formed and formed without reirradiation region more
The crystallite dimension of crystal silicon is different, and then influences the performance of finally formed thin film transistor (TFT).In other words, it can not be moved back by changing
Ignition method solves the problems, such as above-mentioned complex process.Therefore, current compartmentalization laser annealing techniques can such as be improved, is kept away
The introducing for exempting from a variety of annealing mask plates, substantially will alleviate or even solve the above problems.
It is set according to an embodiment of the invention, the periphery circuit region of the symmetrical two sides in array substrate viewing area is having the same
Therefore meter can carry out the amorphous silicon layer in the periphery circuit region of the symmetrical two sides in viewing area by identical annealing mask plate
Annealing, and then the replacement number of annealing mask plate can be reduced, preparation difficulty is reduced, manufacturing cycle is shortened, improves working efficiency,
Reduce production cost.According to an embodiment of the invention, the periphery circuit region of the symmetrical two sides in array substrate viewing area is with identical
Design can refer to, the polysilicon layer design having the same in the periphery circuit region of the symmetrical two sides in viewing area so that
The crystallization process of the periphery circuit region amorphous silicon layer of the symmetrical two sides in viewing area is consistent, to simplify compartmentalization laser annealing techniques pair
The process of periphery circuit region annealing.
Below according to specific embodiments of the present invention, the method for production array substrate according to an embodiment of the present invention is carried out
It is described in detail:
According to an embodiment of the invention, with reference to Fig. 1, this method comprises:
S100: substrate is provided.
According to an embodiment of the invention, in this step, providing substrate, which is underlay substrate.It is according to the present invention
Embodiment defines viewing area 110, and along viewing area 110 symmetrically arranged first with reference to Fig. 4 and Fig. 5 on substrate 100
Periphery circuit region 121 and the second periphery circuit region 122.Wherein, the left and right sides of viewing area 110 can be respectively the first periphery
Circuit region 121 and the second periphery circuit region 122, the two sides up and down of viewing area 110 can also be respectively the first periphery circuit region 121
With the second periphery circuit region 122.The preparation for subsequent step thin film transistor (TFT) provides substrate as a result,.
S200: thin film transistor (TFT) is set in the first periphery circuit region of substrate and the second periphery circuit region, is used to form
The annealing mask plate of thin film transistor (TFT) in first periphery circuit region, and is used to form thin film transistor (TFT) in the second periphery circuit region
Mask plate of annealing is identical.
According to an embodiment of the invention, in this step, the first periphery circuit region and the second peripheral circuit in substrate
Thin film transistor (TFT) is arranged in area.According to an embodiment of the invention, setting thin film transistor (TFT) may include: firstly, in base with reference to Fig. 4
One layer of amorphous silicon layer 200 is set on plate 100, wherein the first periphery circuit region 121 and the second periphery circuit region 122 are respectively provided with
There is amorphous silicon layer 200.Then, to the amorphous silicon layer 200 in the first periphery circuit region 121 and the second periphery circuit region 122 into
Row annealing, to form polysilicon layer 300, wherein applied to the annealing mask plate of the first periphery circuit region 121, with application
Annealing mask plate in the second periphery circuit region 122 is identical.The first periphery circuit region uses phase with the second periphery circuit region as a result,
Same annealing mask plate, it is possible to reduce the replacement number for mask plate of annealing reduces preparation difficulty, improves working efficiency, reduces and give birth to
Produce cost.
It should be noted that " making annealing treatment to amorphous silicon layer " refers to needing to form active layer in subsequent step
Region is made annealing treatment, and the region made annealing treatment can be corresponded with the region where active layer, or be moved back
The region of fire processing can cover the region where multiple active layers, and the region after annealing can form polysilicon layer,
Polysilicon layer can form active layer by subsequent etching processing, using the preparation of grid, source electrode, drain electrode etc., can be formed
Thin film transistor (TFT).
According to an embodiment of the invention, annealing is that compartmentalization laser annealing is handled, compartmentalization laser annealing processing is adopted
With microlens array annealing mask plate carries out laser energy amplification and graphical crystallization process, thus, it is possible to needing to anneal
Region carry out proprietary annealing in other words only the region for needing to transform amorphous silicon into polysilicon made annealing treatment.
According to an embodiment of the invention, form the annealing mask plate of the polysilicon layer of the first periphery circuit region, and the is formed
The annealing mask plate of the polysilicon layer of two periphery circuit regions is identical, as a result, relative to current first periphery circuit region and second week
The preparation for the polysilicon layer being symmetrical set in the circuit region of side can save new annealing according to the method for the embodiment of the present invention and cover
Film version, while the replacement number of annealing mask plate is reduced, working efficiency can be significantly improved, production cost is reduced.According to this hair
The annealing mask plate that bright embodiment, the first periphery circuit region and the second periphery circuit region use is identical, then the first peripheral circuit
Size, the shape of polysilicon layer and the polysilicon layer in the second periphery circuit region in area are all the same.
According to an embodiment of the invention, the polysilicon layer 300 in the first periphery circuit region 121 is relative to first with reference to Fig. 5
Polysilicon layer 300 in the position of periphery circuit region 121, with the second periphery circuit region 122 is relative to the second periphery circuit region 122
Position consistency (polysilicon layer of the viewing area up and down in the periphery circuit region of two sides is not shown).Thus, it is possible to which periphery is effectively reduced
The crystallization complexity of circuit region allows the first periphery circuit region and the second periphery circuit region using identical annealing operation
Polysilicon layer is formed, manufacturing cycle is shortened, improves work efficiency.According to an embodiment of the invention, the first periphery circuit region
Size, the shape, relative position of polysilicon layer 300 in 121, with the polysilicon layer 300 in the second periphery circuit region 122
Size, shape, relative position are consistent, and the first periphery circuit region and the second periphery circuit region can be moved back using identical as a result,
Firer's sequence and identical annealing mask plate are annealed, and are shortened manufacturing cycle, are improved work efficiency.
According to an embodiment of the invention, annealing mask plate 400 has hollowed out area, and it can be a hollowed out area, it can also
Think multiple hollowed out areas independent of each other.Specifically, annealing mask plate 400 can have a hollowed out area with reference to Fig. 6
410.The annealing mask plate has simple structure as a result, and the hollowed out area of the annealing mask plate can cover polysilicon layer
The region at place, the polysilicon layer same or similar suitable for region can be further reduced the replacement number of annealing mask plate,
Improve working efficiency.According to another embodiment of the invention, with reference to Fig. 7, mask plate 400 of annealing may include multiple only each other
Vertical hollowed out area 410.Each hollowed out area of the annealing mask plate is opposite with the region where each polysilicon layer as a result,
It answers, it is possible to reduce the consumption of energy.
According to an embodiment of the invention, hollowed out area and annealing formed polysilicon layer match, as a result, hollowed out area with
And the polysilicon layer size and shape having the same that annealing is formed.According to an embodiment of the invention, when annealing mask plate has
One hollowed out area, and the area of the hollowed out area be greater than need annealing region area when, formed by the annealing mask plate
Polysilicon layer, etching can form multiple active layers in the next steps, in other words, what multiple active layers were formed, there is phase
With the polysilicon layer in region or proximate region, annealing formation is carried out using above-mentioned annealing mask plate.Thus, it is possible to further
The replacement number of annealing mask plate is reduced, working efficiency is improved.When mask plate of annealing has multiple hollowed out areas, by the annealing
The polysilicon layer that mask plate is formed can be corresponded with active layer, in other words, each hollowed out area of the annealing mask plate
It is corresponded with the size, shape and position of each active layer.Thus, it is possible to reduce the consumption of energy.
According to an embodiment of the invention, there is the first presumptive area 10, and move back in the first periphery circuit region 121 with reference to Fig. 8
The area of the hollowed out area of fiery mask plate is greater than the area of the first presumptive area 10, and the first presumptive area 10 is used to form film crystalline substance
Body pipe, carried out in the first periphery circuit region 121 annealing include: enable annealing mask plate hollowed out area on substrate just
Projection covers the first presumptive area 10, and the polysilicon layer formed as a result, based on above-mentioned annealing mask plate in the next steps may be used
It is etched to form multiple active layers, the relative position of multiple active layers in two periphery circuit regions can identical or two week
Multiple active layers in the circuit region of side are symmetrical arranged.
According to an embodiment of the invention, the annealed processing of the first presumptive area 10 forms polysilicon layer, then, to first week
Side circuit region and the polysilicon layer of the second periphery circuit region perform etching processing, wherein are applied in the first periphery circuit region
Etch mask version, be applied to the second periphery circuit region in etch mask version it is identical.As a result, in two periphery circuit regions
Multiple active layers can be formed after the etched processing of polysilicon layer, and the active layer in the first periphery circuit region is relative to the first periphery
The position of circuit region, it is identical relative to the position of the second periphery circuit region as the active layer in the second periphery circuit region.
According to an embodiment of the invention, annealing mask plate has a hollowed out area, and the area of hollowed out area is at least
Two times of first presumptive area, 10 area have the first presumptive area 10 and the with reference to Fig. 8, in the first periphery circuit region 121
One symmetrical region 20, the first symmetrical region 20 is symmetrical in the first periphery circuit region 121 with the first presumptive area 10, annealing
Orthographic projection of the hollowed out area of mask plate on substrate covers the first presumptive area and the first symmetrical region.As a result, based on upper
The polysilicon layer that annealing mask plate is formed is stated, not only includes the first presumptive area but also includes the first symmetrical region.
According to an embodiment of the invention, the first presumptive area 10 and the annealed processing of the second symmetrical region 20 be respectively formed it is more
Crystal silicon layer, the first periphery circuit region 121 is identical with the annealing mask plate that the second periphery circuit region 122 uses, therefore, the second periphery
The first presumptive area 10 and the annealed processing of the first symmetrical region 20 in circuit region 122 are also respectively formed polysilicon layer.Then,
Processing is performed etching to the polysilicon layer of the first periphery circuit region and the second periphery circuit region, wherein be applied to the first periphery
Etch mask version in circuit region, be applied to the second periphery circuit region in etch mask version it is mutually symmetrical with.Two week as a result,
Can form multiple active layers after the etched processing of polysilicon layer in the circuit region of side, and the active layer in the first periphery circuit region with
Active layer in second periphery circuit region is symmetrical arranged, and is improved and is currently formed brought by symmetrically arranged active layer frequently more
The problem of changing annealing mask plate, in other words, can also form the active layer being symmetrical set using identical annealing mask plate.
It should be noted that above-mentioned annealing mask plate has a hollowed out area, the hollowed out area can cover the as a result,
One presumptive area and the first symmetrical region perform etching polysilicon layer convenient for subsequent step symmetrically arranged active to be formed
Layer.Wherein, the first symmetrical region can be the axial symmetry region of the first presumptive area, can also be in the first presumptive area
Heart symmetrical region, those skilled in the art can as the case may be to annealing mask plate hollowed out area be designed.
According to an embodiment of the invention, when annealing mask plate can cover the first presumptive area, or first can be covered
When presumptive area and the first symmetrical region, which can also be the annealing mask plate with multiple hollowed out areas,
Since each hollowed out area of the annealing mask plate is corresponded with each polysilicon layer, above-mentioned annealing exposure mask is utilized as a result,
The polysilicon layer that version is formed, it is consistent in the first periphery circuit region and relative position in the second periphery circuit region.
According to an embodiment of the invention, there is the first fate for being used to form thin film transistor (TFT) in the first periphery circuit region
Domain, for the area for mask plate building empty region of annealing less than the area of the first presumptive area, this method may include: based on above-mentioned annealing
Mask plate repeatedly makes annealing treatment the amorphous silicon layer of the first presumptive area, wherein and the position repeatedly made annealing treatment is different,
The multiple polysilicon layers formed as a result, based on multiple annealing constitute the first presumptive area, in the next steps, above-mentioned polycrystalline
Silicon layer can form multiple active layers by etching, relative position of the active layer in the first periphery circuit region, and on the second periphery
Relative position in circuit region is consistent.
It should be noted that in the present invention, " relative position is consistent " refers in particular to polysilicon layer in the first periphery circuit region
Coordinate position, it is consistent with coordinate position of the polysilicon layer in the second periphery circuit region.
According to an embodiment of the invention, making a reservation for when orthographic projection of the hollowed out area of annealing mask plate on substrate is located at first
When in region, annealing mask plate can have a hollowed out area, specifically, the first presumptive area 10 needs to carry out with reference to Fig. 9
Repeatedly annealing, in other words, the first presumptive area 10 need multiple annealing mask plates, and each annealing mask plate is one corresponding
Polysilicon layer 300, each polysilicon layer 300 is corresponding with the annealing above-mentioned hollowed out area of mask plate, and is covered based on above-mentioned annealing
Each polysilicon layer 300 that film version is formed can form multiple active layers 500, active layer 500 by etching in the next steps
Relative position in the first periphery circuit region 121, it is consistent with the relative position in the second periphery circuit region 122.
It should be noted that the polysilicon layer 300 that each annealing mask plate is formed, what etching was formed in the next steps has
The number of active layer 500 can determine have in each polysilicon layer 300 in Fig. 9 according to the size of the annealing mask plate actually used
The number of active layer 500 should not be understood as pair merely to illustrate that polysilicon layer 300 can etch to form multiple active layers 500
The limitation of the number for the active layer 500 that polysilicon layer 300 is capable of forming.
Other embodiments according to the present invention, when orthographic projection of the hollowed out area on substrate of annealing mask plate is located at the
When in one presumptive area, annealing mask plate can have multiple hollowed out areas independent of each other, specifically, with reference to Figure 10, first
The needs of presumptive area 10 are repeatedly made annealing treatment, and in other words, the first presumptive area 10 needs multiple annealing mask plates, each
Annealing mask plate corresponds to multiple polysilicon layers 300, and each polysilicon layer 300 is opposite with annealing each hollowed out area of mask plate
It answers, and each polysilicon layer 300 can be etched to form an active layer 500 in the next steps, active layer 500 was at first week
Relative position in side circuit region 121, it is consistent with the relative position in the second periphery circuit region 122.
It should be noted that in order to guarantee subsequent etching processing formed active layer performance, using have it is multiple that
When the annealing mask plate of this independent hollowed out area is annealed, the size for the polysilicon layer that each hollowed out area is formed needs
More than or equal to the size of the subsequent active layer needed to form, to guarantee the service performance of active layer.
According to an embodiment of the invention, by one that the thin film transistor (TFT) that this method is formed is circuit in periphery circuit region
Point, specifically, being provided with the first circuit 30 in the first periphery circuit region 121 with reference to Figure 11, being set in the second periphery circuit region 122
It is equipped with second circuit 40, the thin film transistor (TFT) in the first circuit 30, size, ruler with the thin film transistor (TFT) in second circuit 40
Very little, direction and relative position are consistent, so that the first circuit 30 and the design with uniformity of second circuit 40.According to the present invention
Specific embodiment, the first circuit 30 and second circuit 40 can be gate driving circuit (GOA).
According to an embodiment of the invention, the position of thin film transistor (TFT) is relative to current in the first circuit 30 and second circuit 40
The position of thin film transistor (TFT) is changed in circuit, in order to guarantee that the first circuit 30 is consistent with 40 electric property of second circuit
Property, can design the connection type and cabling mode of conducting wire by calculating, so that the first circuit 30 and second circuit 40
Electric property is consistent, guarantees that the circuit in the periphery circuit region of the symmetrical two sides in viewing area 110 is consistent to the control of pixel unit, into
And guarantee viewing area display quality with higher.
It should be noted that " electric property is consistent ", and " the first circuit and second circuit design with uniformity ", it is special
Refer to the first circuit 30 and second circuit 40 being located on substrate (including the original parts such as thin film transistor (TFT), storage capacitance and conducting wire)
Circuit diagram is identical.
It will be appreciated to those of skill in the art that the polysilicon layer of viewing area is preferable repeated due to having,
The crystallization process of entire viewing area can be carried out using the same annealing mask plate, details are not described herein.
In another aspect of this invention, the invention proposes a kind of array substrates.According to an embodiment of the invention, the array
Substrate is made by previously described method.The array substrate has the array substrate of previously described method production as a result,
Whole features and advantage, details are not described herein.Generally speaking, which has that preparation process is simple, the production cycle
Short and low production cost advantage.
In another aspect of this invention, the invention proposes a kind of array substrates.According to an embodiment of the invention, the array
Substrate can for using previously described method preparation array substrate, as a result, the array substrate can have with it is previously mentioned
Method preparation the identical feature of array substrate and advantage, details are not described herein.
According to an embodiment of the invention, the array substrate includes: substrate 100 and film crystal with reference to Fig. 4 and Fig. 5
Pipe, wherein viewing area 110 is defined on substrate 100 and along symmetrically arranged first periphery circuit region 121 in viewing area 110
And second periphery circuit region 122, the first periphery circuit region 121 and the second periphery circuit region 122 of substrate 100 are provided with thin
Film transistor, wherein relative position of the thin film transistor (TFT) in the first periphery circuit region 121 in the first periphery circuit region 121,
It is consistent with relative position of the thin film transistor (TFT) in the second periphery circuit region 122 in the second periphery circuit region 122.As a result, should
Array substrate has the advantages that manufacturing process is simple, with short production cycle and production cost is low.
According to an embodiment of the invention, the first periphery circuit region 121 is consistent with relative position in the second periphery circuit region 122
The shape of thin film transistor (TFT), size it is also consistent.As a result, when making the thin film transistor (TFT) of periphery circuit region, it can use
Identical annealing mask plate and identical annealing operation simplify preparation section, shorten manufacturing cycle.
It should be noted that the film in the thin film transistor (TFT) in the first periphery circuit region, with the second periphery circuit region is brilliant
The size of body pipe, shape, relative position are consistent, can specifically refer to, having in the thin film transistor (TFT) in the first periphery circuit region
Active layer, it is consistent with the size of the active layer in the thin film transistor (TFT) in the second periphery circuit region, shape, relative position.Exist as a result,
During preparing thin film transistor (TFT), identical annealing mask plate and identical annealing operation can be used, is prepared first week
The active layer in active layer and the second periphery circuit region in the circuit region of side effectively simplifies preparation process, shortens preparation week
Phase improves working efficiency, reduces production cost.
According to an embodiment of the invention, the array substrate can also include: storage capacitance, it is located in the first periphery circuit region
Relative position of the storage capacitance in the first periphery circuit region, with the storage capacitance that is located in the second periphery circuit region second
Relative position in periphery circuit region is consistent.Thus, it is possible to which storage capacitance is made to match with corresponding thin film transistor (TFT).
According to an embodiment of the invention, being provided with circuit, circuit in the first periphery circuit region and the second periphery circuit region
Including thin film transistor (TFT) and storage capacitance, the position of the first periphery circuit region and the thin film transistor (TFT) in the second periphery circuit region
Position relative to the thin film transistor (TFT) in current above-mentioned periphery circuit region is changed, in order to guarantee the first periphery circuit region
In circuit and the circuit in the second periphery circuit region electric property it is consistent, the connection side of conducting wire can be designed by calculating
Formula and cabling mode, so that the electric property one of the circuit in the first periphery circuit region and the circuit in the second periphery circuit region
It causes, guarantees that the circuit in the periphery circuit region of the symmetrical two sides in viewing area is consistent to the control of pixel unit, and then guarantee viewing area
Display quality with higher.According to a particular embodiment of the invention, the circuit in the first periphery circuit region and the second periphery electricity
Circuit in the area of road can be gate driving circuit.
In another aspect of this invention, the invention proposes a kind of display panels.According to an embodiment of the invention, the display
Panel includes previously described array substrate.As a result, the display panel have previously described array substrate whole features with
And advantage, details are not described herein.Generally speaking, the display panel is simple, with short production cycle with manufacturing process and is produced into
This low advantage.
In the description of the present invention, the orientation or positional relationship of the instructions such as term " on ", "lower" is based on the figure
Orientation or positional relationship is merely for convenience of the description present invention rather than requires the present invention that must be constructed and be grasped with specific orientation
Make, therefore is not considered as limiting the invention.
In the description of this specification, the description of reference term " one embodiment ", " another embodiment " etc. means to tie
The embodiment particular features, structures, materials, or characteristics described are closed to be included at least one embodiment of the present invention.At this
In specification, the schematic representation of the above terms does not necessarily have to refer to the same embodiment or example.Moreover, the tool of description
Body characteristics, structure, material or feature may be combined in any suitable manner in any one or more of the embodiments or examples.This
Outside, without conflicting with each other, those skilled in the art by different embodiments described in this specification or can show
The feature of example and different embodiments or examples is combined.In addition, it is necessary to illustrate, in this specification, term
" first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicate meaning
The quantity of the technical characteristic shown.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (10)
1. a kind of method for making array substrate characterized by comprising
Substrate is provided, the ceiling substrate has viewing area surely, and along symmetrically arranged first peripheral circuit in the viewing area
Area and the second periphery circuit region；And
In first periphery circuit region of the substrate and second periphery circuit region, thin film transistor (TFT) is set, it is described to set
The step of setting thin film transistor (TFT) include:
Amorphous silicon layer is set in first periphery circuit region and second periphery circuit region, the amorphous silicon layer is carried out
Annealing, to form polysilicon layer,
Wherein, the annealing mask plate applied to first periphery circuit region, with moving back applied to second periphery circuit region
Fiery mask plate is identical.
2. the method according to claim 1, wherein polysilicon layer in first periphery circuit region relative to
Polysilicon layer in the position of first periphery circuit region, with second periphery circuit region is relative to the second periphery electricity
The position in road area is identical.
3. the method according to claim 1, wherein the annealing mask plate have hollowed out area, described first
There is the first presumptive area, the area of the hollowed out area is greater than the area of first presumptive area, institute in periphery circuit region
The first presumptive area is stated to be configurable for forming the thin film transistor (TFT),
Carrying out the annealing in first periphery circuit region includes:
The orthographic projection of the hollowed out area of the annealing mask plate on the substrate is enabled, first presumptive area is covered.
4. according to the method described in claim 3, it is characterized in that, further comprising:
Processing is performed etching to the polysilicon layer of first periphery circuit region and second periphery circuit region, wherein answer
For the etch mask version in first periphery circuit region, with the etch mask version being applied in second periphery circuit region
It is identical.
5. according to the method described in claim 3, it is characterized in that, the area of the hollowed out area to be at least described first predetermined
Two times of region area, the method further includes:
Processing is performed etching to the polysilicon layer of first periphery circuit region and second periphery circuit region, wherein answer
For the etch mask version in first periphery circuit region, with the etch mask version being applied in second periphery circuit region
It is mutually symmetrical with.
6. the method according to claim 1, wherein the annealing mask plate have hollowed out area, described first
There is the first presumptive area, the area of the hollowed out area is less than the area of first presumptive area, institute in periphery circuit region
The first presumptive area is stated to be configurable for forming the thin film transistor (TFT), which comprises
Based on the annealing mask plate, the repeatedly annealing is carried out to the amorphous silicon layer of first presumptive area, wherein
The position of the multiple annealing is different.
7. a kind of array substrate, which is characterized in that made by method described in any one of claims 1-6.
8. a kind of array substrate characterized by comprising
Substrate, the ceiling substrate have a viewing area surely, and along symmetrically arranged first periphery circuit region in the viewing area and
Second periphery circuit region；And
Thin film transistor (TFT), the thin film transistor (TFT) be arranged in the substrate first periphery circuit region and the second week
Side circuit region,
Wherein, position of the thin film transistor (TFT) in first periphery circuit region relative to first periphery circuit region, with institute
State position consistency of the thin film transistor (TFT) relative to second periphery circuit region in the second periphery circuit region.
9. array substrate according to claim 8, which is characterized in that further comprise:
Storage capacitance, position of the storage capacitance relative to first periphery circuit region in first periphery circuit region
It sets, the position consistency with the storage capacitance in second periphery circuit region relative to second periphery circuit region.
10. a kind of display panel, which is characterized in that including the described in any item array substrates of claim 7-9.
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| CN1560907A (en) * | 2004-03-08 | 2005-01-05 | 友达光电股份有限公司 | Laser annealing device and its laser annealing method |
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| CN105842980A (en) * | 2016-06-02 | 2016-08-10 | 京东方科技集团股份有限公司 | Mask plate and design method, array substrate and manufacturing method, and related display apparatus |
| CN106505071A (en) * | 2016-10-18 | 2017-03-15 | 武汉华星光电技术有限公司 | Thin-film transistor array base-plate and preparation method thereof |
| CN109003991A (en) * | 2018-08-01 | 2018-12-14 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof and display panel |
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2019
- 2019-01-02 CN CN201910001472.1A patent/CN109727921B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1560907A (en) * | 2004-03-08 | 2005-01-05 | 友达光电股份有限公司 | Laser annealing device and its laser annealing method |
| CN104576438A (en) * | 2013-10-29 | 2015-04-29 | 昆山国显光电有限公司 | Device and method for preparing polycrystalline silicon thin film |
| CN105842980A (en) * | 2016-06-02 | 2016-08-10 | 京东方科技集团股份有限公司 | Mask plate and design method, array substrate and manufacturing method, and related display apparatus |
| CN106505071A (en) * | 2016-10-18 | 2017-03-15 | 武汉华星光电技术有限公司 | Thin-film transistor array base-plate and preparation method thereof |
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