CN109726063B

CN109726063B - Automatic judgment method for Verilog-based MIPS processor

Info

Publication number: CN109726063B
Application number: CN201811554156.9A
Authority: CN
Inventors: 万寒; 刘康旭; 高小鹏; 钟梓皓; 王辰昱; 杨子琛; 冯炜韬
Original assignee: Beihang University
Current assignee: Beihang University
Priority date: 2018-12-19
Filing date: 2018-12-19
Publication date: 2020-05-08
Anticipated expiration: 2038-12-19
Also published as: CN109726063A

Abstract

The invention provides an automatic judgment method for a Verilog-based MIPS processor, which belongs to the field of teaching auxiliary tools. The method comprises the following steps: constructing an instruction sequence written into a register and a data memory in the same period to execute an MIPS assembly language to write a test program; inserting a $ display statement into a general register and a data memory module as required to simulate a simulation project created by calling hardware simulation software through a tcl script; initializing two queues, and comparing whether the instruction address, the write address and the write content of the two records are the same; and synthesizing the judgment results of all the instruction behaviors to obtain the correctness judgment result of the MIPS processor. The invention judges the correctness of the MIPS processor and provides the automatic teaching auxiliary method of error related prompt information, thereby improving the teaching efficiency and reducing the debugging difficulty of learners.

Description

Automatic judgment method for Verilog-based MIPS processor

Technical Field

The invention belongs to the field of teaching auxiliary tools, and relates to an automatic judgment method for an MIPS (million Instructions per second) processor written by Verilog (hardware description language).

Background

The MIPS (Microprocessor without Interlocked Pipeline Stages) architecture is a simplified instruction set processor architecture proposed by stanford university, in which all instructions are of the same word size, and the details of the internal implementation of the processor are visible to programmers. Based on the characteristics, the MIPS processor is realized through autonomous design, so that learners can be helped to understand the computer composition principle and relevant knowledge of a computer system structure, and the MIPS processor plays an auxiliary role in teaching of relevant theoretical courses.

Verilog is a Hardware Description Language (Hardware Description Language), can model digital circuits by using different abstraction levels such as transistor level, logic gate level, register transmission level, behavior level and the like, and is widely applied to the microelectronic industry. The digital Circuit modeled by Verilog can be mapped into a logic Gate-level netlist by a logic synthesis tool, and further, the netlist can be used for producing Integrated Circuit devices such as an FPGA (Field Programmable Gate Array), an ASIC (Application-Specific Integrated Circuit) and the like.

The existing MIPS processor correctness evaluation methods can be mainly classified into a waveform comparison method and a register (data memory) comparison method. The former needs to perform simulation waveform analysis and comparison cycle by cycle, usually only can judge the simulation waveform of a single instruction or a small amount of instructions, and meanwhile, an evaluator is also required to have deep understanding on an MIPS instruction set and a framework, so that the MIPS instruction set and the framework are difficult to complete automatically, the labor cost is high, and the rate of missed judgment is high. The latter judges the correctness of the MIPS processor by comparing the contents stored in the general purpose registers before and after the execution of the test program with the contents stored in the data memory, and the method has the disadvantage that the specific position where the error occurs cannot be located.

Disclosure of Invention

The invention provides an automatic judgment method of an MIPS processor based on Verilog of instruction behaviors aiming at the problems of difficulty in judgment of correctness of related experiments of MIPS processor design, inconvenience in debugging of a learner and the like in practical teaching, and provides an automatic teaching auxiliary method for judging the correctness of the MIPS processor and giving wrong related prompt information so as to improve teaching efficiency and reduce debugging difficulty of the learner.

The invention discloses an automatic judgment method of an MIPS processor based on instruction behaviors and realized by Verilog, which comprises the following steps:

step 1: and writing a test program by using MIPS assembly language, and assembling the test program to obtain the initialization content of the MIPS machine code and the data memory.

Step 2: and (3) loading the test program written in the step (1) in the customized Mars, opening a state recording tool State Recorder, linking to the current operating environment, and then executing the test program. The State register records the writing behaviors of the general register, the multiplication and division register and the data memory in the running process in a text form and exports the writing behaviors as a recording file A.

In the step 2, when the write-in behaviors of the general register, the multiply-divide register and the data memory are recorded, each record comprises an instruction address for generating a current write request, a hexadecimal write-in address of the current write request and hexadecimal write-in content; in the exported record file A, each line contains one write-in behavior record, and the recording sequence cannot be disturbed.

And step 3: calling hardware simulation software through a tcl script to create a simulation project, adding a Verilog source file (set) of the MIPS processor to be judged, machine codes and data memory initialization contents in the step 1 and a testbench excitation file into the project, and simulating the project according to preset simulation duration.

The $ display command is built in the general register and the data memory module of the MIPS processor to be evaluated in the step 3, and when each write request in the simulation process arrives, the following information is output to a standard output Stream (STDOUT): the current simulation time, the instruction address generating the current write request, the hexadecimal write address of the current write request and the hexadecimal write content. And after the simulation is finished, dumping the text information in the standard output stream into a record file B. Each line in the record file B contains one write request record, and the recording sequence cannot be disturbed.

And 4, step 4: initializing two queues, and respectively storing the general registers in the record file A and the write requests of the data memory into the two queues in sequence; reading the write request in the record file B line by line, selecting the head of line record of the corresponding queue according to the type of the request, comparing whether the instruction address (program counter value), the write address and the written content of the two records are the same, if so, considering that the instruction is executed correctly, otherwise, considering that the instruction or the preorder instruction of the instruction is executed wrongly.

In the step 4, the current simulation time recorded in the step 3 is further used for screening the single-cycle or multi-cycle processor and the pipeline processor, and the specific method is as follows: and (2) adding an adjacent general register write-in instruction and a data memory write-in instruction into the test program constructed in the step (1), detecting the write request in the record file B, and if the write-in record of the general register and the data memory with the write-in time difference not exceeding one simulation cycle does not exist, proving that the MIPS processor is not a pipeline processor.

And 5: and (4) integrating the judgment results of the instruction behaviors in the step (4) to obtain the correctness judgment result of the MIPS processor, and giving the position range of the first error instruction for the wrong MIPS processor.

Compared with the existing correctness judging method of the MIPS processor, the method has the advantages and positive effects that:

(1) the method provided by the invention can be used for carrying out fine-grained analysis on the simulation result, not only avoids complex waveform analysis, but also provides more accurate error instruction position information while giving the judgment result of the correctness of the MIPS processor, assists learners to modify the design, and improves the development and debugging efficiency.

(2) The method provided by the invention reduces the constraint condition for MIPS processor design, and learners only need to insert $ display sentences into the general register and the data memory module according to requirements without paying attention to details such as module names, module hierarchical relations and the like.

(3) The method provided by the invention realizes the discrimination of the MIPS instruction set single-cycle (or multi-cycle) processor and the pipeline processor by utilizing the structural characteristics of the MIPS pipeline processor and constructing the instruction sequence of the write-in register and the write-in data memory in the same cycle, has the advantages of good universality and strong confidentiality, can not be interfered by a conventional confusion method, and avoids the problem that a learner uses the single-cycle (or multi-cycle) processor with low realization difficulty to impersonate the pipeline processor with high realization difficulty.

Drawings

FIG. 1 is a schematic flow chart of the method for automatically evaluating a Verilog-implemented MIPS processor based on instruction behavior according to the present invention;

FIG. 2 is a general register write request record command example;

fig. 3 is an example of a data memory write request record command.

Detailed Description

The technical solution of the present invention is described below with reference to the accompanying drawings and examples.

The automatic judgment method for the Verilog-based MIPS processor comprises the following five steps as shown in figure 1.

Step 1: and writing a test program by using MIPS assembly language, and assembling by using an assembler to obtain the initialization content of the MIPS machine code and the data memory. MIPS assemblers, such as Mars, are also assemblers used in embodiments of the present invention. The MIPS machine code is the initialized contents of the instruction memory.

When the MIPS assembly language is used for writing a test program, a single instruction or a plurality of instructions in the instruction set can be combined randomly according to teaching needs, and the test program can be written manually or generated through an automatic script.

The compiled initialization content of the instruction memory and the initialization content of the data memory are stored in the form of independent text files, and are read into the relevant memories by a $ readmemh command in a Verilog source file during simulation.

Step 2: and (3) loading the test program written in the step (1) in the customized Mars, opening a state recording tool State Recorder, linking to the current operating environment, and then executing the test program. The State element Recorder records the write-in behaviors of general registers, multiplication and division registers ($ hi, $ lo) and a data memory in a text form during operation and exports the write-in behaviors as a record file A. The customized Mars is characterized in that a state recording tool State Recorder is added on the basis of the original Mars.

When writing behaviors of the general register, the multiply-divide register ($ hi, $ lo) and the data memory are recorded, each record contains an instruction address (hexadecimal program counter value) for generating a current write request, a hexadecimal write address for the current write request, and hexadecimal write contents, and the write contents may be 1-4 bytes in length according to instructions. The records are independent of each other, and the sequence cannot be disordered.

In the exported record file A, each line contains one write-in action record, the recording sequence cannot be disturbed, and the record is ended by a file end mark EOF.

And step 3: calling hardware simulation software such as an ISE Simulator through a tcl (tool command language) script to create a simulation project, adding a MIPS processor Verilog source file (set) to be judged, instruction memory initialization content in the step 1, data memory initialization content in the step 1 and a universal testbench excitation file into the project, and simulating the project according to preset simulation duration.

In the simulation process, the $ display command shown in fig. 1 and 2, which is built in a general register and a data memory module in the MIPS processor, outputs information to a standard output Stream (STDOUT) in a certain format when each write request arrives. Each write request record output by the display command comprises: the current simulation time is a decimal integer and does not contain a unit; generating an instruction address of the current write request, wherein the instruction address is a hexadecimal program counter value; the current write request is for a hexadecimal write address and for hexadecimal write content. According to different instructions, the length of the written content can be 1-4 bytes, and if the single-cycle (or multi-cycle) processor and the pipeline processor do not need to be screened, the current simulation time information can be omitted.

As shown in fig. 2, when the general register write function is called, the built-in $ display command will be executed, outputting the current simulation time; generating an instruction address WPC of a current write request; the current write request is written into address Waddr in hexadecimal form; and hexadecimal write content Wdata. time is a decimal integer, without units. WPC is a hexadecimal program counter value. The write content may be 1-4 bytes in length, depending on the instruction.

Similarly, as shown in fig. 3, when the data memory write function is called, the built-in $ display command is executed, and the current simulation time is output; generating an instruction address PC of a current write request; the current write request is written into the address addr in hexadecimal form; and hexadecimal write content din. time is a decimal integer, without units. WPC is a hexadecimal program counter value. The write content may be 1-4 bytes in length, depending on the instruction.

And after the simulation is finished, dumping the text information in the standard output stream into a record file B. In the record file B, each line contains one write request record, and the recording order cannot be disturbed, ending with EOF.

The tcl script used in the step has the function of replacing a graphical interface to operate an XilinxISE Design Suite tool in scenes such as a server and the like, so that automatic testing is realized, and the testing efficiency is improved.

The testbench excitation file used in the step has the following functions: the MIPS processor is provided with stimulus signals including a periodic clock signal and a reset signal.

And 4, step 4: initializing two queues, and respectively storing the general registers in the record file A and the write requests of the data memory into the two queues in sequence; reading the write request in the record file B line by line, selecting the head of line record of the corresponding queue according to the type of the write request, comparing whether the instruction address (program counter value), the write address and the written content of the two records are the same, if so, considering that the instruction is executed correctly, otherwise, considering that the instruction or the preorder instruction of the instruction is executed wrongly.

In particular, since the value of the general register $ 0($ zero) in the MIPS instruction set is always 0, when the register is written, whether or not a write action is recorded, it should be considered as a correct action, and the difference of the written contents in the record is ignored.

In the method, the current simulation time information in the write request record is used for discriminating the single-cycle (or multi-cycle) processor and the pipeline processor, and the specific method is as follows: and (2) adding an adjacent general register write instruction and a data memory write instruction into the test program constructed in the step (1), wherein the general register write instruction and the data memory write instruction are inevitably and respectively written into the general register and the data memory in the same simulation period due to the structural characteristics of the pipeline MIPS processor. And detecting the write request in the record file B, and if the write records of the general register and the data memory, the write time difference of which does not exceed one simulation cycle, do not exist, the MIPS processor is proved not to be a standard pipeline processor.

The following is a sequence of assembler instructions consisting of two instructions that can be used to screen a single-cycle (or multi-cycle) processor:

1: ori $ t1, $ t0, 0xffff # ORs the general register $ t0 with the immediate 0xffff, and writes the result to register $ t1

2: sw $ t1, 0($0) # writes the value of general register $ t1 to a location in data memory having an address of 0

In a five-stage pipelined MIPS processor, when the memory access pipeline stage (MEM stage) performs a data memory write operation of instruction 2, the write register pipeline stage (WB stage) immediately following it just performs a general register write operation of instruction 1. In different Verilog implementations, the data memory and the general-purpose register may be written in a rising edge or a falling edge, but no matter what writing method is combined, in the MIPS processor with the five-stage pipeline structure, the writing operations of the instruction 1 and the instruction 2 are completed in the same simulation cycle, which is a characteristic that a single-cycle processor or a multi-cycle processor cannot simulate.

An assembler program for discriminating between single-cycle (or multi-cycle) processors and pipelined processors refers to any assembler program that includes an instruction that produces general-purpose register (non- $0 register) write behavior and an immediately subsequent instruction that produces data memory write behavior.

And 5: and (4) integrating the judgment results of the instruction behaviors in the step (4) to obtain the correctness judgment result of the MIPS processor, and giving relevant information of a first error instruction to the wrong MIPS processor to help a learner to find and solve the problems in the design.

The related information of the first error instruction is obtained by using the first error writing instruction (the instruction written into the register or the data memory) discovered by the judging method based on the instruction behavior in the step 4, the possible error range of the judged MIPS processor can be narrowed to a range between the successor instruction of the last correct writing instruction and the current writing instruction, in practical application, the number of the instructions in the range is usually not more than 3, and therefore, a learner can be effectively helped to discover the error root and quickly solve the problem.

Claims

1. An automatic judgment method for a Verilog-implemented MIPS processor based on instruction behaviors comprises the following steps:

step 1: compiling a test program by using MIPS assembly language, and assembling the test program to obtain initialization contents of MIPS machine codes and a data memory;

step 2: loading the test program written in the step 1 in Mars, opening a state recording tool statementRecorder, linking to the current operating environment, and then executing the test program, wherein the statementRecorder records the writing behaviors of a general register, a multiplication and division register and a data memory in the operating process in a text form and exports the writing behaviors as a recording file A;

and step 3: calling hardware simulation software through a tcl script to create a simulation project, adding a Verilog source file of the MIPS processor to be judged, the machine code and the data memory initialization content in the step 1 and a testbench excitation file into the project, and simulating the project according to preset simulation duration;

it is characterized in that the preparation method is characterized in that,

in the step 2, when the write-in behaviors of the general register, the multiply-divide register and the data memory are recorded, each record comprises an instruction address for generating a current write request, a hexadecimal write-in address of the current write request and hexadecimal write-in content; in the exported recording file A, each line contains a writing-in behavior record, and the recording sequence cannot be disturbed;

in step 3, in the simulation process, a $ display command is built in a general register and a data memory module of the MIPS processor, and when each write request arrives, the following information is output to the standard output stream: the method comprises the steps of at the current simulation moment, generating an instruction address of a current write request, a hexadecimal write address of the current write request and hexadecimal write content; after the simulation is finished, dumping the text information in the standard output stream into a record file B; each line in the record file B comprises a write-in request record, and the recording sequence cannot be disturbed;

and 4, step 4: initializing two queues, and respectively storing the general registers in the record file A and the write requests of the data memory into the two queues in sequence; reading the write request in the recording file B line by line, selecting the head of line record of the corresponding queue according to the type of the request, comparing whether the instruction address, the write address and the written content of the two records are the same, if so, considering that the instruction is executed correctly, otherwise, considering that the instruction or the preorder instruction of the instruction is executed wrongly;

and 5: the judgment results of all the instruction behaviors in the step 4 are integrated to obtain the correctness judgment result of the MIPS processor, and the position range of the first error instruction is given for the wrong MIPS processor;

the MIPS is a microprocessor without an internal interlocking pipeline stage, the Verilog is a hardware description language, and the Mars is a MIPS assembly operation simulator.

2. The method according to claim 1, wherein in step 4, when comparing record file B with record file A, when general register $0 is written, whether or not write activity is recorded, it is regarded as correct activity, and the difference of write contents in the record is ignored.

3. The method of claim 1, wherein in step 4, the current simulation time is further used to discriminate whether the processor is a single-cycle or multi-cycle processor or a pipeline processor, the test program constructed in step 1 is added with an immediately adjacent general register write instruction and data memory write instruction, the write request in the record file B is detected, and if there is no general register and data memory write record whose write times differ by no more than one simulation cycle, the MIPS processor is not a pipeline processor.