CN109714545A - A kind of high speed hyperspectral imager image processing system - Google Patents
A kind of high speed hyperspectral imager image processing system Download PDFInfo
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Abstract
It is an object of the present invention to provide a kind of high speed hyperspectral imager image processing systems, realize that high spatial resolution, high time resolution provide a kind of efficient technological approaches for remotely sensed image.In the high speed hyperspectral imager image processing system, analog video signal analog signal processing accordingly uses 64 operational amplification circuits to export 64 tunnel difference conditioned signals according to the form of single-ended transfer difference, the AFE(analog front end) of the high-speed ADC converter integrated into 8 four-ways, pass through the correlated-double-sampling of PLC technology, gain adjustment is carried out again, then analog-to-digital conversion is completed, the digital image data of 32 road parallel outputs is obtained after conversion；Then image data splicing and auxiliary data synthesis are carried out, adaptive gain adjustment feedback is carried out based on full frame image after synthesis；Full frame image data are divided into 8 pieces again, the corresponding high-speed transfer that realization mass image data after parallel-serial conversion is carried out by 8 tunnel high speed SerDes transceivers.
Description
Technical field
The present invention relates to a kind of high-resolution interference type imaging spectrometer image processing systems.
Background technique
As national economy in recent years develops rapidly, the departments such as environmental protection, land resources, meteorology, agricultural, mitigation are due to business
Demand, to Imaging remote sensing field, more stringent requirements are proposed.So that high spatial resolution, high time resolution, high spectral resolution
Rate imaging just becomes the target that must be realized.Under conditions of remotely sensed image is looked down ground breadth and is not reduced as far as possible, image point
Resolution wants constantly improve, then accordingly requires that remotely sensed image optical spectrum imagers image form is big, frame frequency wants high.Tradition is relied on again
Optical spectrum imagers mentality of designing simply carries out parallel processing to each one-channel signal of detector output, and bring is hardware
The proportional increase of design scale, imaging circuit power consumption increase, and substantially increase the excessive occupancy to satellite platform resource.Therefore
Designing high space-time, spectral resolution, low-power consumption optical spectrum imagers image processing system becomes problem.In this context, design is new
The efficient imaging sense of type is great.
Goal of the invention
It is an object of the present invention to provide a kind of high speed hyperspectral imager image processing systems, realize high spatial for remotely sensed image
Resolution ratio, high time resolution provide a kind of efficient technological approaches.
The technology of the present invention solution:
The high speed hyperspectral imager image processing system includes sequentially connected high speed optoelectronic conversion circuit plate, high speed view
Frequency signal condition and analog to digital conversion circuit plate, high speed image splicing and high speed transmission circuit board, to be set to high speed image splicing
And the FPGA on high speed transmission circuit board is central processing circuit unit；
CCD and its driving and analog video signal reading circuit, output are provided on the high speed optoelectronic conversion circuit plate
32 road analog video signals；It is wherein provided with outside every reading port of analog video signal all the way and is built by high-frequency triode
Voltage follower circuit, with realize read port impedance transformation and driving capability promoted；
The conditioning of analog video signal front end signal is provided on the high-speed video conditioning and analog to digital conversion circuit plate
Circuit, analog to digital conversion circuit, sequential control circuit；The sequential control circuit generates CCD photoelectricity according to the control signal of FPGA
The working sequence and phase adjustment timing of sequential logic timing needed for conversion, analog to digital conversion circuit；The analog video signal
Analog signal processing accordingly uses 64 operational amplification circuits to export the conditioning of 64 tunnel difference according to the form of single-ended transfer difference
Signal, the high-speed ADC converter that analog-digital conversion circuit as described uses 8 four-ways to integrate, 64 tunnel difference conditioned signals enter 8
The AFE(analog front end) of the integrated high-speed ADC converter of four-way, by the correlated-double-sampling of PLC technology, then carries out gain tune
It is whole, analog-to-digital conversion is then completed, the digital image data of 32 road parallel outputs is obtained after conversion；
The high speed image splicing and high speed transmission circuit board, based on FPGA to the digitized image number of 32 road parallel outputs
According to image data splicing and auxiliary data synthesis is carried out, the feedback to the gain adjustment is provided based on full frame image after synthesis,
It realizes adaptive gain adjustment, while recording auto-adaptive parameter into image auxiliary data, as adaptive adjustment label；Then
Full frame image data are divided into 8 pieces, realize large nuber of images after accordingly carrying out parallel-serial conversion by 8 tunnel high speed SerDes transceivers
The high-speed transfer of data.
Based on above scheme, the present invention has also further made following optimization:
The correlated-double-sampling of the PLC technology specifically realized by the FPGA, is initially starting point to view using reset pulse
The signal peak direction of frequency waveform is searched for, and according to the situation of change of the transfer function values of sampling point image, is repeated several times adjustment and is searched
Suo Fangxiang simultaneously reduces step-size in search, finally determines optimum sampling point, that is, reset level position is determined, thus the letter with video waveform
Number peak value makees difference and obtains the virtual value of reflection target information.
The gain adjustment is specifically: the adaptive gain adjustment, specifically: for image data splicing and supplementary number
According to the image that synthesis obtains, continuous several frames extract a frame, calculate maximum gradation value in the frame image, calculate the maximum gradation value
With the difference of given threshold；According to difference, the amplification/minification for needing to adjust is calculated, before the simulation of high-speed ADC converter
End carries out the feedback regulation of gain.
The CCD is back-illuminated type frame transfer CCD, has 2048 × 256 image surface battle arrays.
Data between high speed optoelectronic conversion circuit plate and high-speed video conditioning and analog to digital conversion circuit plate, which export, to be connected
Connect the HMM158FAE9X710787 connector that device uses the production of IEH company.
The operational amplification circuit uses the LMH6715J-QML of TI company.
The model XC5VFX130T-1FF1738I of the FPGA.
The workflow of the image processing system is as follows:
(1) under the control unit CCD driver' s timing control in high-speed video conditioning and analog to digital conversion circuit, high speed
Photoelectric conversion circuit realizes the conversion of scenery to electric signal, and by the electric signal speedy carding process comprising optical information；
(2) it is instructed according to several guard systems, vision signal conditioning and conversion circuit increase High Speed Analog video electrical signal
Benefit is adjusted；
(3) correlated-double-sampling is carried out to 32 road High Speed Analog vision signals, then every four channels are that a unit carries out
Analog-to-digital conversion；
(4) digital signals in parallel after analog-to-digital conversion send control unit to carry out image data splicing, and auxiliary data is added；
(5) whole using the bright shadow of adapting to image, it, can be according to entire image gray value histogram in non-artificial intervention
The nomography progress bright shadow of image is whole, and (feedback adjustment: adjusting parameter is generated by FPGA algorithm, and execution is reflected in analog-to-digital conversion front end
In gain adjustment amplifier in)；
(6) full frame image data are divided into 8 pieces, are sent in parallel through 8 tunnel high speed SerDes chips.
The invention has the following advantages:
(1) system takes full advantage of the advantage of high-speed four-channel gain adjustment, correlated-double-sampling function ADC, and carries out
Adaptive bright shadow is whole, solve the parallel high-speed signal conditions of the high speed optoelectronic data of high light spectrum image-forming generation, ADC conversion,
The practical problems such as high-speed transfer have many advantages, such as processing speed is fast, consistency is good, stable working performance, are spaceborne high-altitude
Between resolution ratio, high time resolution imaging expand dynamic range and provide a kind of new technological means.
(2) high-spectrum of the up to large format of 9.6Gbps bandwidth, high frame frequency, low noise is realized to the system high efficiency
As data-handling capacity.
(3) good in economic efficiency, practical.The system architecture compatible remote sensing fields use based on CCD, ADC, FPGA
Structure, interface is reserved to have fully considered that subsequent parameter promotes required extension, and the design that need to be referred to no longer needs to weight of spending a lot of time and energy
New designing system framework.
(4) system is with a wide range of applications, and may be also used in such as: the remotely sensed image of high-resolution business, stereo mapping
In many imaging devices such as camera, wide swath remote sensing generaI investigation, the monitoring of big picture high-resolution disaster.
Detailed description of the invention
Fig. 1 is the spaceborne high-resolution spectra imager image data processing system composition schematic diagram of the embodiment of the present invention.
Fig. 2 is sharpness evaluation function with close to optimum sampling point change in location curve.
Fig. 3 is the schematic diagram of optimum sampling point searching algorithm.
Specific embodiment
With reference to the accompanying drawing and specific embodiment the present invention is described in detail.
The invention mainly comprises 3 parts, are high speed optoelectronic conversion circuit, high-speed video conditioning and analog-to-digital conversion respectively
Circuit, high speed image splicing and high speed transmission circuit composition.
(1) high speed optoelectronic conversion circuit plate
The high speed optoelectronic conversion circuit high speed large area array back side illumination image sensor (CCD) wide using spectral response range,
Configuration driven circuit and analog video signal reading circuit, high speed, strong power needed for providing high speed optoelectronic conversion for detector
Driver' s timing, the video voltage signal of final high speed readout high sensitivity, high bandwidth, realizes high-performance photoelectricity turnover.
It is specific as shown in Figure 1, the large area array of the plate, high frame frequency, high-quantum efficiency ccd detector by using 2048 ×
256 image surface battle arrays, frame frequency 1500fps, using the structure of back-illuminated type, quantum efficiency within the scope of 450nm~850nm >=65%.
32 analog video signal reading circuits read the voltage for being provided with outside port and being built by high-frequency small power triode 3DG112D
Circuit is followed, the impedance transformation for reading end is realized and driving capability is promoted.Detector driving circuit uses Intersil company
Four-way drives device ISL7457, driving pulse most narrow spaces can control 9ns, realize every channel 34MHz and read pixel
Driving capability.
Data out connector uses the HMM158FAE9X710787 connector of IEH company production, and insertion loss is low, passes
Defeated cable signal integrity performance is good.
The course of work are as follows: while incident optical signal is converted into charge signal by CCD, under high-frequency drive pulsed drive,
Charge signal in gesture well is transferred to 32 road port reading circuits, then reading circuit converts the charge to voltage signal, warp
After voltage follower circuit enhances power, the signal condition and AD conversion unit of rear class are passed to.
(2) high-speed video conditioning and analog to digital conversion circuit plate
The high-speed video conditioning and analog to digital conversion circuit plate mainly include the conditioning of analog video signal front end signal
Unit, AD conversion unit, timing control unit.
The signal condition for the operational amplifier composition that the analog video signal front end signal conditioning unit uses band enabled
Circuit carries out the correlated-double-sampling and gain control regulatory function of PLC technology；The AD conversion unit circuit uses four
The integrated high-speed ADC converter in channel, output difference digital information splice circuit to back-end image；The timing control unit by
Driver' s timing needed for FPGA realizes control CCD photoelectric conversion, front-end gain control and the work of AD needed for generating ADC work
Timing and phase adjustment timing.
Specifically as shown in Figure 1, analog video signal front end signal conditioning unit is mainly (64) operation of 32 accesses
Amplifying circuit, AD conversion unit are mainly made of the ADC processor that 8 integrated four-way High Speed Analog front ends and ADC are converted,
For completing the High Speed Analog digital video in up to 32 channels, every channel highest 40MHz.
High-speed video conditioning circuit is made of the LMH6715J-QML of 64 TI companies, realizes high broadband high-speed simulation
Video Quality Metric.It is different according to optical spectrum imagers transmissivity of optical system, analogue signal amplitude can be adjusted flexibly, can be mended
Repay the deviation for filling optical design energy balane.Analog video data input connector selects IEH company HMM158FAE9X710787
Connector.
By the High Speed Analog vision signal of LMH6715, into four-way ADC conversion circuit, circuit first regards simulation
Frequency signal carries out correlated-double-sampling, then carries out gain adjustment, then carry out analog-to-digital conversion.Analog to digital conversion circuit uses
ADDI7004, adc circuit designs can be configured quantization digit in use.Highest supports 14bit quantization.To visible optical mode
Quasi- vision signal, analog-to-digital conversion need to search for optimum sampling point in debugging process, and the present invention also innovatively proposes one herein
Set quickly approaches the adjustment method of optimum sampling position.The analog-to-digital conversion clock of ADDI7004 uses 40MHz clock, after quantization
Serial mode gives rear class image mosaic and adaptive correction and control unit.
Aforementioned correlated-double-sampling, taking the signal peak of video waveform, (relative to reset pulse, which is low electricity
It is flat), it is poor to make with the reset level (flat sections, as reference value) in video waveform, obtains the virtual value of reflection target information.
The present invention is due to using high speed, high-precision ccd detector, so that signal (the voltage follow electricity after photoelectric conversion
Before the drive amplification of road) reseting stage in each period is not in flat level, but will appear fluctuation, therefore, this
Invention it needs to be determined that its trough reference point of the position as correlated-double-sampling.
Determination for reset level position, conventional algorithm is: the time of estimation reset pulse to flat sections, to determine
Reset level position.The adjustment method for quickly approaching optimum sampling position of the invention is:
1, reset pulse is estimated to the section of signal peak；
2, step-size in search is set, using reset pulse as starting point, is searched for signal peak direction and determines reset level position: is every
One " step " acquires a frame video image, calculates the transmission function of image, if the value of this transmission function is less than last time and transmits letter
Several values shows not arriving reset level position also, then continues to search for signal peak direction；
If the value tn of this transmission function is less than the value tn-1 of last time transmission function, show to have crossed optimum sampling point (again
Bit level position), then it adjusts step-size in search (step-length halves), opposite direction search；
If the transfer function values tn+1 that step-length sampled point adjusted is calculated compared with tn and tn-1, is determined in next step
The direction of search；
Less than tn, then continue to search for reset pulse direction；
By being repeated several times the adjustment direction of search and step-length, optimum sampling point is finally determined.
High-speed video conditioning and the analog to digital conversion circuit plate course of work are as follows: 32 road CCD analog videos are through operational amplifier circuit
After conditioned signal, the AFE(analog front end) of the high-speed ADC of 8 integrated four-ways is entered with difference form, each road gain is amplified
Afterwards, parallel high-speed ADC conversion is carried out, is sent to back-end processing circuit per the digital signal high speed serialization after converting all the way.
(3) high speed image splicing and high speed transmission circuit board
The high speed image splicing circuit completes image data splicing by FPGA and auxiliary data synthesizes, wherein further relating to certainly
Adapt to modified feedback control；The high speed transmission circuit realizes magnanimity figure after carrying out parallel-serial conversion by high speed SerDes transceiver
As the high-speed transfer of data.
High speed image splicing and high speed transmission circuit are with field programmable gate array (Field Programmable Gate
Array, FPGA) be core central processing circuit unit, and the multichannel based on the high speed serialization/transceiver TLK2711 that unstrings
Diameter, high-speed differential serial serial data transmission unit composition.
It is specific as shown in Figure 1, being that core form high speed image splicing circuit, by TLK2711 high speed serialization/unstring by FPGA
Transceiver forms high speed image data transmission circuit；High speed data transfer circuit external connection is produced by AirBorn company
HSMHK-02L0-402-275-26C0 connector is connected with data transmission set.
FPGA specifically selects FPGA model XC5VFX130T-1FF1738I, receives figure after mainly completing ADC quantization
As data high-speed splice, generate CCD photoelectric conversion needed for sequential logic timing, drive high-speed, multi-path ADC work clock and
Phase adjustment.
Adaptive bright dark modified meaning: making up the lag of ground intervening surface, make full use of the dynamic range (DN value) of camera,
Adjustment video image (digital signal) in real time.
For spliced image, every 1000 frame extracts 1 frame, calculates maximum gradation value (most bright spot) in the frame image, counts
Calculate the difference of the maximum gradation value and given threshold；The empirical value of the threshold value is the 2/3 of dynamic range, such as the DN value of camera is
4096, then the threshold value 2600；
According to difference, calculates the amplification/minification for needing to adjust, increased in the AFE(analog front end) of high-speed ADC converter
Benefit adjustment (feedback control).
FPGA sends serial image data, clock and control signal, is encoded according to 8b/10b, FPGA is soft by internal operation
Part, which calls the realization of its internal logic unit to be compiled into the image data of 12bit, can be used for the continuous of high speed SerDes transmission
16bit image data is then issued to high speed TLK2711 chip and carries out parallel-serial conversion.
High speed SerDes transmitting line has used 8 TLK2711 chips, monolithic work clock 100Mhz；The stabilization of monolithic
Transmission rate reaches 12.8Gbps transmission rate in 1.6Gbps, 8 TLK2711 chips of entire data-interface.
Operating process in the embodiment course of normal operation is as follows:
(1) under driver ISL7457 driving, the electric signal high-speed parallel that photoelectric conversion is generated is read ccd detector,
Generate continuous analog video signal；
After the signal conditioning circuit that (2) 32 High Speed Analog vision signals are built through broadband operational amplifier LMH6715, by 8 high speeds,
After four-way ADC chip ADDI7004 quantization, become digital image data；
The digital image data of (3) 32 parallel outputs, carries out image mosaic in FPGA, and stitching image contains frame
Frequently, after the auxiliary datas such as time, it is divided into 8 parts of image data packets；
(4) parallel image data packet is distributed to the serial transmission interface of 8 high speed SerDes chips composition by FPGA,
Image data is sent to Data transfer system with the rate of 12.8Gbps.
(5) Data transfer system is responsible in real time passing hyperspectral imager image data down.
Below with regard to quickly approached in analog-digital conversion process the adjustment method (optimum sampling point search) of optimum sampling position into
Row is described in detail:
The clarity of different sampling location imagings is evaluated, the clarity of the image on optimum sampling position is utilized
This best feature finds correct optimum sampling position.Judge whether to choose be optimum sampling position is to pass through image clearly
Evaluation function is spent as main measurement foundation.Utilize the image respective function under sharpness evaluation function difference sampling location
The curve graph that value sketches out searches in curve graph and characterizes the functional value of optimum sampling position.Evaluation function, which is chosen, to be had relatively surely
Determine the shade of gray function of characteristic.
When far from optimum sampling position, sharpness evaluation function value is smaller, continues equidirectional mobile sampling location, to most
Good sampling location is drawn close；When near optimum sampling position, sharpness evaluation function value is larger, then reduces moving step length,
Realize intense adjustment sampling location.
Image Definition is for describing image definition parameter, i.e. sharpness evaluation function value is got over
Greatly, image is more clear, and sampling location herein is exactly optimal sampling location.Image Definition should have unbiased
Property, can reflect the characteristic, small compared with high s/n ratio, calculation amount for leaving optimum sampling position at unimodality, while in optimum sampling position
Near, relatively narrow, the more precipitous advantage of characteristic curve is collapsed in reflection.Ideal Image Definition is with collapsing to most preferably adopting
The change curve of sampling point position degree is as shown in Figure 2.
Image grayscale time domain sharpness evaluation function includes following common form (line number and columns of x, y expression image):
Eight neighborhood shade of gray of f (x, y) are as follows:
During the sampling location AD in adjustment camera circuitry, corresponding the characteristics of generating image grayscale, design is based on ash
Spend evaluation function that maximum of gradients adds up, with reflection correspondence image clarity are as follows:
Wherein:
Max (T)=max (T1, T2, T3, T4, T5, T6, T7, T8)
Min (T)=min (T1, T2, T3, T4, T5, T6, T7, T8)
The sharpness evaluation function value at optimum sampling point neighbouring position is calculated according to sharpness evaluation function, is needed
Want searching algorithm find out clarity it is best when sampling point position.Sampled point searching algorithm requires fast convergence rate, simultaneously scans for
Accuracy it is high.Assuming that system arbitrary initial position is Pi, initial position sharpness evaluation function value is F (i), mobile primary
Location is Pi+1, sharpness evaluation function value is F (i+1), and search moving step length is L.
It is studied on the left of optimum sampling position with F (i), if F (i) can also be obtained on the right side of optimum sampling position
Similar conclusion out.Search process is as shown in Figure 3:
A) it sets and starts the selected sampling location of debugging as principle optimum sampling point and the position P in left sidei, clarity evaluation letter
Number F (i) is P with the mobile primary corresponding position big step-length Li+1, sharpness evaluation function value be F (i+1), if F (i) and
F (i+1) does not have significant difference, that is, when meeting the condition of formula (3), illustrates that the initial samples position also distance that choosing sampling takes is best
Farther out, continue searching influences sampling less, to keep direction constant, while will search plain step-length to become 2L from L sampling point position.TH
The empirical value DN=1800 chosen when for according to debugging, reason are that we generally use based on spaceborne image a/d resolution
12bit quantization, then image full scale maximum gradation value is in DN=4095.According to engineering experience, DN=3800 or more is non-linear bright
It is aobvious, therefore practical debugging is the upper limit with 3800.
If b) F (i+1) and F (i) are significantly increased, that is, when meeting the condition of formula (4), illustrate last L pairs of step-length
The influential effect for approaching optimum sampling point is larger, then keeps the direction of search constant, while reducing sampling moving step length L is L/2.
If c) F (i+1) is obviously reduced than F (i), that is, when meeting the condition of formula (5), illustrate current sampling location away from
It is close from optimum sampling point, change the direction of search, while reducing sampling moving step length L is L/2.Step (a) and (b) is repeated, directly
Reach 3 times to direction of search change.
D) sampled point has been positioned at optimum sampling vertex neighborhood at this time, changes the direction of search, is opened with minimum stepper distances Lmin
Begin to carry out verification search, until confirmation meets conditional (6), sampling is in optimum sampling point position at this time.
F(i+1)≥F(i) (6)
The advantages of optimum sampling point searching algorithm:
There is stronger immunological characteristic to influence of noise.Because when there are isolated noise point, it is easy in noise point
Acquisition greatest gradient is set, but for noise spot, eight neighborhood pixel grey scale is similar.
Have simultaneouslyThe characteristics of.
And due to the evaluation function of our definitionSo that for
The calculated result of isolated noise can show max (T) × [max (T)-min (T)]≤max (T), i.e., to the influence of evaluation function
It is very little.
In Practical Project test, we are chosen under laboratory stabilized light source (integrating sphere), and image grayscale DN=3800 is left
It is verified when right；After debugging out optimum sampling point, under different illumination, different scenery, image has reliable and stable camera
Picture characteristics demonstrates the validity of the algorithm.
Claims (7)
1. a kind of high speed hyperspectral imager image processing system, it is characterised in that: converted including sequentially connected high speed optoelectronic
Circuit board, high-speed video conditioning and analog to digital conversion circuit plate, high speed image splicing and high speed transmission circuit board, to be set to
FPGA in high speed image splicing and high speed transmission circuit board is central processing circuit unit；
It is provided with CCD and its driving and analog video signal reading circuit on the high speed optoelectronic conversion circuit plate, exports 32 tunnels
Analog video signal；Wherein the electricity built by high-frequency triode is provided with outside every reading port of analog video signal all the way
Pressure follows circuit, to realize that the impedance transformation for reading port and driving capability are promoted；
Be provided in high-speed video conditioning and analog to digital conversion circuit plate analog video signal analog signal processing,
Analog to digital conversion circuit, sequential control circuit；The sequential control circuit generates CCD photoelectric conversion institute according to the control signal of FPGA
The working sequence and phase adjustment timing of the sequential logic timing, analog to digital conversion circuit that need；The analog video signal front end letter
Number conditioning circuit accordingly uses 64 operational amplification circuits to export 64 tunnel difference conditioned signals, institute according to the form of single-ended transfer difference
The high-speed ADC converter that analog to digital conversion circuit uses 8 four-ways to integrate is stated, 64 tunnel difference conditioned signals enter 8 four-ways
The AFE(analog front end) of integrated high-speed ADC converter by the correlated-double-sampling of PLC technology, then carries out gain adjustment, then
Analog-to-digital conversion is completed, the digital image data of 32 road parallel outputs is obtained after conversion；
High speed image splicing and high speed transmission circuit board, based on FPGA to the digital image datas of 32 road parallel outputs into
The splicing of row image data and auxiliary data synthesis, provide the feedback to the gain adjustment based on full frame image after synthesis, realize
Adaptive gain adjustment, while auto-adaptive parameter is recorded into image auxiliary data, as adaptive adjustment label；It then will be whole
Frame image data is divided into 8 pieces, realizes mass image data after accordingly carrying out parallel-serial conversion by 8 tunnel high speed SerDes transceivers
High-speed transfer.
2. high speed hyperspectral imager image processing system according to claim 1, it is characterised in that: the programmable control
The correlated-double-sampling of system specifically realized by the FPGA, is initially starting point to the signal peak direction of video waveform using reset pulse
Search is repeated several times the adjustment direction of search and reduces step-size in search according to the situation of change of the transfer function values of sampling point image,
It is final to determine optimum sampling point, that is, reset level position is determined, so that the signal peak with video waveform obtains reflection mesh as difference
Mark the virtual value of information.
3. high speed hyperspectral imager image processing system according to claim 1, it is characterised in that: the gain adjustment
Specifically: the adaptive gain adjustment, specifically: the image synthesized for image data splicing and auxiliary data, even
Continue several frames and extract a frame, calculates maximum gradation value in the frame image, calculate the difference of the maximum gradation value and given threshold；Root
According to difference, the amplification/minification for needing to adjust is calculated, carry out the feedback tune of gain in the AFE(analog front end) of high-speed ADC converter
Section.
4. high speed hyperspectral imager image processing system according to claim 1, it is characterised in that: the CCD is back
Illuminated frame transfer CCD has 2048 × 256 image surface battle arrays.
5. high speed hyperspectral imager image processing system according to claim 1, it is characterised in that: high speed optoelectronic conversion
Data out connector between circuit board and high-speed video conditioning and analog to digital conversion circuit plate is using the production of IEH company
HMM158FAE9X710787 connector.
6. high speed hyperspectral imager image processing system according to claim 1, it is characterised in that: the operation amplifier
Circuit uses the LMH6715J-QML of TI company.
7. high speed hyperspectral imager image processing system according to claim 1, it is characterised in that: the type of the FPGA
Number be XC5VFX130T-1FF1738I.
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| CN111490784A (en) * | 2020-04-23 | 2020-08-04 | 全球能源互联网研究院有限公司 | Analog-to-digital converter and analog-to-digital conversion method |
| CN112104811A (en) * | 2020-09-21 | 2020-12-18 | 中国科学院长春光学精密机械与物理研究所 | Low-latency multi-group imaging control system |
| CN113609636A (en) * | 2021-06-21 | 2021-11-05 | 西安空间无线电技术研究所 | Analog-digital (AD) collected data Field Programmable Gate Array (FPGA) processing simulation verification system based on TLK2711 transmission |
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