CN109712994A - Array substrate and preparation method thereof - Google Patents
Array substrate and preparation method thereof Download PDFInfo
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- CN109712994A CN109712994A CN201910056789.5A CN201910056789A CN109712994A CN 109712994 A CN109712994 A CN 109712994A CN 201910056789 A CN201910056789 A CN 201910056789A CN 109712994 A CN109712994 A CN 109712994A
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- Prior art keywords
- layer
- via hole
- color blocking
- aperture
- film transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Abstract
The present invention provides a kind of array substrate and preparation method thereof, and wherein array substrate includes substrate, film transistor device, color blocking layer, passivation layer and pixel electrode layer.Film transistor device is arranged on the substrate.Color blocking layer is covered on the film transistor device, and the color blocking layer is equipped with groove.Passivation layer is covered in the color blocking layer, and is covered along the surface of the groove.Pixel electrode layer is arranged on the passivation layer.The passivation layer offers the first via hole and the second via hole, and the pixel electrode layer is electrically connected by first via hole and the film transistor device, and second via hole exposes the color blocking layer to the open air, wherein at least one second via hole is located on the groove.It is thereby achieved that the via hole on passivation layer, guarantees that the steam in color blocking layer is discharged from via hole.
Description
Technical field
The present invention relates to field of display technology, espespecially a kind of array substrate and preparation method thereof.
Background technique
With the promotion of social progress and people's demand, display is also towards large scale, high-resolution (High
Definition direction) is developed.To meet high-resolution and large-sized demand, in thin film transistor (TFT) (Thin-Film
Transistor, TFT) array substrate coating color blocking (COA, color filter on array) technology it is extensive
Using.On the one hand the promotion of panel aperture ratio (aperture ratio) may be implemented in COA technique.On the other hand, color blocking material
Due to its water absorption character, in particular by active layer of metal oxide, such as indium gallium zinc (IGZO, Indium Gallium
Zinc Oxide) etc., can obstruct extraneous steam has significant promotion effect to TFT device performance.
However, in COA technique research and development, since the processing procedures such as cleaning introduce after Q-time (waiting time) and color blocking processing procedure
Moisture will lead to steam in color blocking material and reach saturation state, to make that device electric is caused to deteriorate.Although steam in color blocking
It can be removed by subsequent baking processing procedure, but since COA technique can also prepare passivation layer in color blocking, it is subsequent to prevent
Damage of the dry carving technology to color blocking surface.Therefore passivation layer hinders the discharge of the steam in color blocking, causes TFT device performance serious
Deterioration.
Summary of the invention
In view of this, it is necessary to provide a kind of array substrate and preparation method thereof, to solve to ask present in the prior art
Topic.
The purpose of the present invention is to provide a kind of array substrate and preparation method thereof, passes through control photoresist thickness or etching
Technical arrangement plan realizes the via hole on passivation layer, guarantees that the steam in color blocking layer can be arranged in subsequent baking processing procedure from via hole
Out, the problem of effectively reducing the deterioration of display device performance.
To reach foregoing purpose of the invention, the present invention provides a kind of array substrate, including substrate, thin film transistor (TFT) device
Part, color blocking layer, passivation layer and pixel electrode layer.Film transistor device is arranged on the substrate.Color blocking layer is covered on described
On film transistor device, the color blocking layer is equipped with groove.Passivation layer is covered in the color blocking layer, and along the groove
Surface covering.Pixel electrode layer is arranged on the passivation layer, wherein the passivation layer offers the first via hole and at least 1 the
Two via holes, the pixel electrode layer are electrically connected by the metal electrode of first via hole and the film transistor device,
At least one second via hole exposes the color blocking layer to the open air, wherein at least one second via hole is located on the groove.
In one embodiment of this invention, the groove includes the first aperture and the second aperture, and first aperture is less than
Second aperture.
In one embodiment of this invention, second number of vias is 1 or multiple.
It in one embodiment of this invention, further include being arranged between the film transistor device and the color blocking layer
Flatness layer.
Furthermore the present invention separately provides a kind of production method of array substrate, comprising the following steps:
S10, substrate is provided；
S20, film transistor device is prepared on the substrate；
S30, color blocking layer is coated on the film transistor device, the color blocking layer is adjacent to the film transistor device
Form groove；And
S40, the deposit passivation layer in the color blocking layer, and deposited along the surface of the groove, on the passivation layer
It is etched after coating photoresist and exposed development, in first via hole of passivation layer formation and at least one second via hole；And
S50, deposition and graphical pixel electrode layer on the passivation layer；
Wherein the pixel electrode layer is electrical by the metal electrode of first via hole and the film transistor device
Connection, at least one second via hole expose the color blocking layer to the open air.
In one embodiment of this invention, in step s 40, after being coated with photoresist and exposed development on the passivation layer
Etching, wherein the etch process is to form first via hole and described second with dry etching (Dry Etching) technique
Via hole.
In one embodiment of this invention, when the coating photoresist is at the surface of the passivation layer, in the groove
Photoresist forms aperture by exposure development, and first via hole is then formed on the passivation layer by the dry etching.
In one embodiment of this invention, when being coated with the photoresist in the passivation layer, the photoresist of part can edge
Two side wall of groove flow down it is thinning, then by the dry etching, to form described at least 1 the on the passivation layer
Two via holes.
In one embodiment of this invention, in step s 40, the light blockage coating thickness is controlled between 1.5 to 2 microns
(um), the thickness of the color blocking layer is between 0.5-3.5 microns (um).
In one embodiment of this invention, in step s 30, formed the groove be it is trapezoidal, the groove include first
Aperture and the second aperture, first aperture are less than second aperture, and relatively described first aperture in second aperture is separate
The film transistor device.
Compared with prior art, the present invention can not increasing process apparatus cost and on the basis of other additional process,
Simply realize via hole on the passivation layer.The improvement of making technology through the invention, such as photoresist thickness control, etching work
Skill parameter adjustment etc., realizes via hole on the passivation layer, to guarantee that the steam in color blocking layer can be arranged in subsequent baking processing procedure
Out, array substrate/display device performance deterioration is effectively reduced, the performance and quality for promoting display device are reached.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the cross-sectional view that film transistor device is arranged in array substrate of the present invention in substrate；
Fig. 2 is that color blocking layer, passivation layer and the cross for being coated with photoresist is arranged in array substrate of the present invention on film transistor device
Sectional view；
Fig. 3 is that array substrate of the present invention etches photoresist to form the cross-sectional view of via hole on the passivation layer；
Fig. 4 is the cross-sectional view that pixel electrode layer is arranged in array substrate of the present invention on the passivation layer；
Fig. 5 is the implementation example figure that the present invention realizes via hole on the passivation layer；And
Fig. 6 is the flow chart of the production method of array substrate of the present invention.
Specific embodiment
Refer to that " embodiment " means that a particular feature, structure, or characteristic described in conjunction with the embodiments can in a specific embodiment
To be included at least one embodiment of the present invention.The identical term that different location in the description occurs not necessarily by
It is limited to identical embodiment, and should be understood as mutually being independent with other embodiments or alternative embodiment.At this
It invents under the enlightenment of technical solution disclosed in the embodiment provided, it should be appreciated by those skilled in the art that described in the invention
Embodiment can have other meet the technical solution of present inventive concept combine or variation.
The explanation of following embodiment is to can be used to the particular implementation of implementation to illustrate the present invention with reference to additional schema
Example.The direction term that the present invention is previously mentioned, for example, [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side],
[vertical], [level] etc. are only the directions with reference to annexed drawings.Therefore, the direction term used is to illustrate and understand this
Invention, rather than to limit the present invention.The similar unit of structure is with being given the same reference numerals in the figure.
Please refer to figs. 1 to 4, the present invention provides a kind of array substrate, including substrate 1, film transistor device 2,
Color blocking layer 3, passivation layer 4 and pixel electrode layer 5.Film transistor device 2 as shown in Figures 1 to 4 preferably carries on the back channel etching
The TFT structure of type (Back Channel Etching, BCE).In various other embodiments, film transistor device 2
It can be the TFT structures such as etch stopper stratotype (Etch Stop Layer, ESL), top-gated coplanar type (Top Gate type), and
It does not limit.Since above-mentioned TFT structure is the prior art, do not add to repeat herein.
Film transistor device 2 is arranged in the substrate 1.Color blocking layer 3 is covered on the film transistor device 2,
The color blocking layer 3 is equipped with groove 31 adjacent to the film transistor device 2.Passivation layer 4 is covered in the color blocking layer 3, and edge
The groove 31 surface covering.Pixel electrode layer 5 is arranged on the passivation layer 4.The passivation layer 4 offers the first mistake
Hole 41 and at least one second via hole 42.The pixel electrode layer 5 passes through first via hole 41 and the film transistor device 2
Metal electrode 21 be electrically connected, at least one second via hole 42 exposes the color blocking layer 42 to the open air, wherein described at least one second
Via hole 42 is located at the groove 31.It is thereby achieved that opening up via hole on passivation layer 4, guarantee that the steam in color blocking layer 3 can be from via hole 42
Discharge effectively reduces the deterioration of display device performance, and then promotes the performance and quality of display device, as shown in Figure 5.
As shown in Fig. 2, the groove 31 includes the first aperture 311 and the second aperture 312.First aperture 311 is less than
Second aperture 312, and relatively described first aperture 311 in second aperture 312 is far from the film transistor device 2.
Groove 31 as shown in the figure is trapezoidal, cupuliform or annular.Please with reference to shown in Fig. 3 and Fig. 4,42 quantity of the second via hole is excellent
It is selected as 1 or multiple, symmetrical and neighbouring second aperture 312 of each second via hole 42 is arranged.However in other secondary choosings
In embodiment, 42 quantity of the second via hole can be 1 or multiple, and be formed on the side wall of the groove 31.
It further include being arranged in the film transistor device 2 and the color blocking layer 3 in embodiment as shown in Figures 1 to 4
Between flatness layer 7.7 material of flatness layer is, for example, polycrystalline silicon material.
Please referring again to shown in Fig. 6, the present invention separately provides the production method of array substrate, comprising the following steps: S10, mentions
For substrate 1；S20, film transistor device 2 is prepared in the substrate 1；S30, it is coated on the film transistor device 2
Color blocking layer 3, the color blocking layer 3 form groove 31 adjacent to the film transistor device 2；And S40, in the color blocking layer 3 sink
Product passivation layer 4, and deposited along the surface of the groove 31, it is carved after being coated with photoresist 6 and exposed development on the passivation layer 4
Erosion, to form the first via hole 41 and at least one second via hole 42 in the passivation layer 4；And it S50, deposits on the passivation layer 4
And graphical pixel electrode layer 5；Wherein the pixel electrode layer 5 passes through first via hole 41 and the film transistor device
2 metal electrode 21 is electrically connected, and at least one second via hole 42 exposes the color blocking layer 3 to the open air.
In step s 30, it is trapezoidal for forming the groove 31.The groove 31 includes the first aperture 311 and the second aperture
312, first aperture 311 is less than second aperture 312, and relatively described first aperture 311 in second aperture 312 is separate
The film transistor device 2.
In step s 40, it is etched after being coated with photoresist 6 and exposed development on the passivation layer 4, wherein the etching work
Skill is to form first via hole 41 and second via hole 42 with dry etching (Dry Etching) technique.Control the light
Hindering 6 coating thickness can be between 1.5 to 2 microns (um), preferably 1.8 microns (um).The thickness of the color blocking layer 3 is then between 0.5-
3.5 microns (um).Preferred etch process parameters adjustment, for example, by using CF4+O2Process gas, lost using reactive ion
Carve (Reactive Ion Etching；RIE), carry out dry etching 150 seconds etc., so that the thickness of 31 top photoresist 6 of groove
It spends (relatively thin) and loses the effect for protecting passivation layer 4, cause the passivation layer 4 to be also etched and form the second via hole 42, such as
Shown in Fig. 5.
It is described when being coated with the photoresist 6 at the surface of the passivation layer 4 in embodiment as shown in Figures 2 and 3
Photoresist 6 in groove 31 is completed graphically by exposure development, and 6 aperture of photoresist is formed in 31 region of groove, then
First via hole 41 is formed on the passivation layer 4 by the dry etching.Specifically, since the photoresist 6 has
Certain viscosity and mobility, by being coated with photoresist 6 on the passivation layer 4 of 31 2 side of groove, and in the not yet complete levelling of photoresist 6
It is etched among to groove 31, to form first via hole 41 on passivation layer 4.In addition, when being coated with the photoresist 6
In the passivation layer 4, the photoresist 6 of part can flow down thinning along two side walls of the groove 31, cause in groove 31 2
6 difference in thickness of photoresist of upper side, then by the dry etching, to form described at least 1 the on the passivation layer 4
Two via holes 42.
3 thickness of color blocking layer described herein need to be greater than 0.5 micron, preferably 3 microns, to realize the step structure of groove.
The passivation layer 4 is preferably the laminated construction of SiOx or SiNx, with a thickness of 300 or 100 microns.The passivation layer 4 is preferably
With plasma-based Assisted Chemical Vapor depositing plated film (Plasma Enhanced CVD, PECVD) method film forming, then pass through dry etching
Technique is etched processing procedure.However in other alternative-embodiments, the passivation layer 4 is SiOx, SiNx, HfO2, Al2O3 etc.
The laminated construction that insulating materials or above-mentioned material are constituted.The thickness of the passivation layer 4 can be 1000A-10000A, and pass through
Chemical vapour deposition technique (Chemical Vapor Deposition, CVD) method film forming.
It should be noted that the gate insulating layer in film transistor device is preferably SiNx or SiOx laminated construction, thickness
For 100/300nm, and formed a film by PECVD method.However in other different embodiments, gate insulating layer can also for SiOx,
Optional laminated construction in the insulating dielectric materials such as SiNx, HfO2, Al2O3.The thickness of gate insulating layer can be 100A-
10000A, and can be formed a film by CVD method, it does not limit.Active layer in film transistor device 2 is preferably (Indium
Gallium Zinc Oxide, IGZO) indium gallium zinc.However in an alternate embodiment of the invention, active layer can also partly lead to be various
Body material, including the metal oxide semiconductor materials such as Si base semiconductor, AZO, IZO, IGTO, ZTO.
Therefore, the present invention can simply realize on the basis of not increasing process apparatus cost and other additional process
Via hole on the passivation layer.The improvement of making technology through the invention, such as the adjustment of photoresist thickness control, etch process parameters
Deng can realize via hole on the passivation layer, guarantee that the steam in color blocking layer can be discharged in subsequent baking processing procedure, effectively subtract
The deterioration of few array substrate/display device performance, and then promote the performance and quality of display device.
In conclusion although the present invention is described in conjunction with its specific embodiment, it should be understood that many substitutions are repaired
Changing and changing will be apparent those skilled in the art.Therefore, it is intended to want comprising falling into appended right
Ask all substitutions, modification and the variation in the range of book.
Claims (10)
1. a kind of array substrate, comprising:
Substrate；
Film transistor device, setting is on the substrate；
Color blocking layer is covered on the film transistor device, and the color blocking layer is equipped with groove；
Passivation layer is covered in the color blocking layer, and is covered along the surface of the groove；And
Pixel electrode layer is arranged on the passivation layer；
Wherein, the passivation layer offers the first via hole and at least one second via hole, and the pixel electrode layer passes through described first
The metal electrode of via hole and the film transistor device is electrically connected, and at least one second via hole exposes the color blocking layer to the open air,
Wherein at least one second via hole is located on the groove.
2. array substrate as described in claim 1, which is characterized in that the groove includes the first aperture and the second aperture, institute
The first aperture is stated less than second aperture.
3. array substrate as described in claim 1, which is characterized in that second number of vias is one or more.
4. array substrate as described in claim 1, which is characterized in that further include being arranged in the film transistor device and institute
State the flatness layer between color blocking layer.
5. a kind of production method of array substrate, comprising the following steps:
S10, substrate is provided；
S20, film transistor device is prepared on the substrate；
S30, color blocking layer is coated on the film transistor device, the color blocking layer is formed adjacent to the film transistor device
Groove；And
S40, the deposit passivation layer in the color blocking layer, and deposited along the surface of the groove, it is coated on the passivation layer
It is etched after photoresist and exposed development, in first via hole of passivation layer formation and at least one second via hole；And
S50, deposition and graphical pixel electrode layer on the passivation layer；
Wherein the pixel electrode layer is electrically connected by the metal electrode of first via hole and the film transistor device,
At least one second via hole exposes the color blocking layer to the open air.
6. the production method of array substrate as claimed in claim 5, which is characterized in that in step s 40, in the passivation layer
It is etched after upper coating photoresist and exposed development, wherein the etch process is with dry etching (Dry Etching) technique shape
At first via hole and second via hole.
7. the production method of array substrate as claimed in claim 6, which is characterized in that when the coating photoresist is in the passivation
When the surface of layer, the photoresist in the groove forms aperture by exposure development, then by the dry etching described blunt
Change and forms first via hole on layer.
8. the production method of array substrate as claimed in claim 6, which is characterized in that when the coating photoresist is in the passivation
When layer, the photoresist of part can be flowed down along two side walls of the groove it is thinning, then by the dry etching, thus described
At least one second via hole is formed on passivation layer.
9. the production method of array substrate as claimed in claim 5, which is characterized in that in step s 40, control the photoresist
Coating thickness is 1.8 microns (um) between 1.5 to 2 microns (um), and the thickness of the color blocking layer is between 0.5-3.5 microns (um).
10. the production method of array substrate as claimed in claim 5, which is characterized in that in step s 30, formed described recessed
Slot be it is trapezoidal, the groove include the first aperture and the second aperture, first aperture be less than second aperture, described second
Relatively described first aperture in aperture is far from the film transistor device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910056789.5A CN109712994B (en) | 2019-01-22 | 2019-01-22 | Array substrate and manufacturing method thereof |
| PCT/CN2019/077346 WO2020151056A1 (en) | 2019-01-22 | 2019-03-07 | Array substrate and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910056789.5A CN109712994B (en) | 2019-01-22 | 2019-01-22 | Array substrate and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
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| CN109712994A true CN109712994A (en) | 2019-05-03 |
| CN109712994B CN109712994B (en) | 2020-08-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910056789.5A Active CN109712994B (en) | 2019-01-22 | 2019-01-22 | Array substrate and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109712994B (en) |
| WO (1) | WO2020151056A1 (en) |
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| CN1547241A (en) * | 2003-12-16 | 2004-11-17 | 上海华虹（集团）有限公司 | A method for preventing side lobe from being transferred to substrate when etching |
| CN104157612A (en) * | 2014-08-21 | 2014-11-19 | 深圳市华星光电技术有限公司 | Manufacture method of TFT array substrate, and structure of the TFT array substrate |
| CN106842744A (en) * | 2017-02-14 | 2017-06-13 | 深圳市华星光电技术有限公司 | A kind of array base palte and preparation method thereof |
| CN107463042A (en) * | 2017-09-06 | 2017-12-12 | 深圳市华星光电技术有限公司 | Array base palte and its manufacture method, liquid crystal panel |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104035231B (en) * | 2013-03-07 | 2017-04-12 | 群创光电股份有限公司 | Liquid crystal display panel and liquid crystal display device comprising same |
| KR102184723B1 (en) * | 2014-02-10 | 2020-12-01 | 삼성디스플레이 주식회사 | Display substrate and method of manufacturing the same |
| CN105097673B (en) * | 2015-08-20 | 2018-01-30 | 武汉华星光电技术有限公司 | The preparation method of TFT substrate structure |
-
2019
- 2019-01-22 CN CN201910056789.5A patent/CN109712994B/en active Active
- 2019-03-07 WO PCT/CN2019/077346 patent/WO2020151056A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1547241A (en) * | 2003-12-16 | 2004-11-17 | 上海华虹（集团）有限公司 | A method for preventing side lobe from being transferred to substrate when etching |
| CN104157612A (en) * | 2014-08-21 | 2014-11-19 | 深圳市华星光电技术有限公司 | Manufacture method of TFT array substrate, and structure of the TFT array substrate |
| CN106842744A (en) * | 2017-02-14 | 2017-06-13 | 深圳市华星光电技术有限公司 | A kind of array base palte and preparation method thereof |
| CN107463042A (en) * | 2017-09-06 | 2017-12-12 | 深圳市华星光电技术有限公司 | Array base palte and its manufacture method, liquid crystal panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109712994B (en) | 2020-08-11 |
| WO2020151056A1 (en) | 2020-07-30 |
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