CN109683139B

CN109683139B - Radio frequency direct sampling digital transceiver circuit based on double sampling rates

Info

Publication number: CN109683139B
Application number: CN201811578955.XA
Authority: CN
Inventors: 季帅; 王敬东; 关炀; 王轶
Original assignee: CETC 20 Research Institute
Current assignee: CETC 20 Research Institute
Priority date: 2018-12-24
Filing date: 2018-12-24
Publication date: 2022-08-23
Anticipated expiration: 2038-12-24
Also published as: CN109683139A

Abstract

The invention provides a radio frequency direct-sampling digital transceiver circuit based on double sampling rates, wherein in a transmitting state, an FPGA interpolates data to be transmitted to a high data rate, and converts the data to be transmitted into a radio frequency signal after digital up-conversion; the two DA chips input different reference frequencies, and the transmitting signals are transmitted to the analog TR component through the four-in-one switch to realize the amplification of radio frequency signals after the corresponding DA chips are selected by the switch and different filters are selected by the one-out-four switch; in a receiving state, the two AD chips input different reference frequencies, the analog TR component finishes low-noise amplification of radio frequency echo signals, the echo signals are filtered by the band-pass filters in corresponding frequency bands, and the corresponding AD chips are selected by the switch to perform digital down-conversion and extraction filtering processing for down-sampling processing; and transmitting the sampled data to the FPGA. The invention satisfies the band-pass sampling theorem, realizes the direct radio frequency sampling, and reduces the cost and the realization difficulty of the system; and two sets of devices with sampling rates are configured at the same time, so that the switching time of S level when the sampling rates are switched is avoided.

Description

Radio frequency direct sampling digital receiving and transmitting circuit based on double sampling rates

Technical Field

The invention relates to a transceiver circuit, which mainly aims at a digital multichannel system with high sampling frequency and can realize the multichannel design of a P-L waveband all-digital array phased array radar antenna array surface.

Background

With the rapid development and wide application of software radio and digitization technology, digital radar receivers become a popular mode with unique flexibility and open reliability. However, the conventional digital receiver only aims at receiving a single signal, which greatly limits the signal processing capability of the receiver. The reception of multi-band parallel digital receivers, digital multi-channel receivers, channelized receivers, etc. for multi-band multi-bandwidth signals has emerged to address this need. Although the application of the structures is mature, the structures are still limited by the requirements of the existing devices such as ADC, FPGA and the like on the operating speed bandwidth, and the structures are difficult to change according to the requirements once being determined.

The development trend of modern receiver technology is multifunctional integration and digitization. In a radar system, it is desirable to integrate multiple functions of target searching, receiving, communication, etc., and these functions often work in different frequency bands, and the frequency bands have different bandwidths, which requires an ultra-wide frequency band radar receiver. The receiver of the ultra-wide frequency band can adjust the parameters of the receiver to receive different signals on the premise of not changing the structure of a hardware module of the receiver, can reduce the volume of the system to the maximum extent, has strong flexibility and variability and can be applied to various fields of military affairs, civil use, communication and the like.

In order to realize the design of a P-L waveband 5 octave receiver, the sampling frequency is required to meet the Nyquist sampling theorem, namely the sampled frequency cannot span two Nyquist zones, so that the limitation of direct radio frequency generation and a sampling circuit is determined, and the sampling rate of 5GHz or even higher can be selected to ensure that no spectrum aliasing occurs aiming at the 5 octave working bandwidth of 400 MHz-2 GHz; or the mode of variable sampling rate (adopting two lower sampling rates and an interactive mode) is adopted, and the suppression of an aliasing area is ensured through the anti-aliasing filtering processing of the radio frequency analog part. However, in practical application, both of the two methods have limitations, and for the high sampling rate method, the circuit structure is simple, but the pressure of signal processing increases suddenly, and for the multi-channel system, how to realize the inter-channel synchronization under the condition of such high rate becomes a great problem; the second method needs to add an anti-aliasing filter, but greatly reduces the difficulty of signal processing and synchronization, and the biggest problem is that the switching time required for switching the sampling rate reaches s level, which is unacceptable for the radar system. In the conventional frequency conversion mode, on the premise of 5 octaves, a very complex mixing filtering scheme and a huge filter bank are needed to ensure the performance of the system; in this situation, a reasonable rf direct digital transceiving is needed to ensure the performance of the system.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a radio frequency direct-sampling digital transceiver circuit based on double sampling rates, which can realize the multi-channel design of the P-L waveband all-digital array phased array radar antenna array surface.

The technical scheme adopted by the invention for solving the technical problems is as follows: a radio frequency direct sampling digital transceiver circuit based on double sampling rates comprises an analog TR component, a 400-2000MHz broadband radio frequency switch, a switch filter bank, 2 single-channel AD chips with the highest input frequency being more than or equal to 3GHz, 2 single-channel DA chips with the highest output frequency being more than or equal to 3GHz and an FPGA for realizing a signal processing function.

The switch filter bank comprises two 400-2000MHz broadband radio frequency switches and four band-pass filters, and the pass band frequency ranges of the band-pass filters are 400-700MHz, 1100-1600MHz, 700-1100MHz and 1600-2100MHz respectively;

in a transmitting state, the FPGA interpolates data to be transmitted to a high data rate, and converts the data to be transmitted into a radio frequency signal after digital up-conversion; the two DA chips input different reference frequencies, the reference frequency is 1.8GHz and 2.4GHz, and the DA chips with the reference frequency of 1.8GHz generate transmission signals of 400-700MHz and 1100-1600 MHz; the DA chip with the reference frequency of 2.4GHz generates transmitting signals of 700-1100MHz and 1600-2100 MHz; the transmitting signal is transmitted to the analog TR component through the four-in-one switch to realize the amplification of the radio frequency signal after the different filters are selected by the DA chip and the one-out-of-four switch which are selected by the switch;

in a receiving state, the two AD chips input different reference frequencies which are 1.8GHz and 2.4GHz respectively, and the AD chip with the reference frequency of 1.8GHz is used for processing echo signals of 400-700MHz and 1100-1600 MHz; the AD chip with the reference frequency of 2.4GHz is used for processing echo signals of 700-1100MHz and 1600-2100 MHz; the analog TR component completes low-noise amplification of radio-frequency echo signals, the echo signals are filtered by a band-pass filter of a corresponding frequency band, and a switch selects a corresponding AD chip to perform digital down-conversion and extraction filtering processing for down-sampling processing; and transmitting the sampled data to the FPGA.

The invention has the beneficial effects that: because two sets of AD/DA chips with relatively low speed (the sampling frequency is less than 2.5GHz) are adopted, on one hand, the band-pass sampling theorem is satisfied, the direct radio frequency sampling can be realized, and compared with a high-speed digital device with 5GHz or even higher sampling rate, the cost of the system and the difficulty of realization are reduced; on the other hand, two sets of sampling rate devices are simultaneously configured, so that the switching time of an S level when the sampling rate is switched is avoided, and the switching time of the invention depends on the switching time (generally ns level) of the switch.

The invention mainly reduces the difficulty of high-speed (400-2000 MHz) sampling processing by reducing the sampling rate, avoids unnecessary radar rest time for switching the sampling rate by utilizing the working mode of double sampling rates, and effectively reduces the dead zone of the radar.

Drawings

Fig. 1 is a circuit schematic of the present invention.

Detailed Description

The present invention will be further described with reference to the following drawings and examples, which include, but are not limited to, the following examples.

Referring to fig. 1, the embodiment of the invention mainly includes a simulated TR component, 400-plus-2000 MHz broadband radio frequency switches, a switch filter bank (composed of two 400-plus-2000 MHz broadband radio frequency switches and four band pass filters, the pass band frequency bands of the band pass filters include 400-plus-700 MHz, 1100-plus-1600 MHz, 700-plus-1100 MHz and 1600-plus-2100 MHz), 2 single-channel AD chips with the highest input frequency of not less than 3GHz, 2 single-channel DA chips with the highest output frequency of not less than 3GHz, and an FPGA for realizing the signal processing function.

And in the transmitting state, the FPGA receives data to be transmitted and transmits the data to the DAC. The DAC has a series of interpolation filters that can interpolate data to high data rates. The digital up-conversion module is provided with a 48-bit numerically-controlled oscillator (NCO), the NCO generates mixing frequency, the NCO can control the frequency through programming, data are converted into radio frequency signals after being subjected to digital up-conversion, and at the moment, two DA chips input different reference frequencies: 1.8GHz and 2.4GHz, and DA chips with reference frequency of 1.8GHz are used for generating transmitting signals of 400-700MHz and 1100-1600MHz (the inhibiting frequency is 900MHz and 1800 MHz); the DA chip with the reference frequency of 2.4GHz is used for generating transmitting signals of 700-1100MHz and 1600-2100MHz (the suppression frequency is 1200MHz and 2400 MHz). When the 400-channel 700MHz radio frequency signal is generated, a DA chip with the reference frequency of 1.8GHz generates the 400-channel 700MHz radio frequency signal, the 400-channel 700MHz radio frequency signal is filtered by a four-in-one switch (selecting a corresponding AD/DA chip) and a four-out switch (selecting different filters), the 400-channel 700MHz radio frequency signal is transmitted to the analog TR component through the four-in-one switch to realize the amplification of the radio frequency signal, and the radio frequency signal with the corresponding frequency is transmitted to the analog TR component through filters of different channels and filters of different reference frequency configurations and filter groups of the switches to realize the amplification of the radio frequency signal.

In a receiving state, the analog TR component completes low-noise amplification of a radio-frequency echo signal, enters a corresponding AD to realize digital down-conversion through the filtering selection function of the switch filtering group, and is provided with a 48-bit Numerically Controlled Oscillator (NCO) on a board, and the frequency of the NCO can be controlled through programming, so that the frequency of the down-conversion is controlled. The two AD chips input different reference frequencies: the AD chips with 1.8GHz and 2.4GHz and the reference frequency of 1.8GHz are used for processing echo signals with 400-700MHz and 1100-1600MHz (the suppression frequency is 900MHz and 1800 MHz); the AD chip with the reference frequency of 2.4GHz is used for processing echo signals of 700-1100MHz and 1600-2100MHz (the suppression frequency is 1200MHz and 2400 MHz). When the 400-channel 700MHz echo signal is processed, the 400-channel 700MHz echo signal is processed by the filtering function of a switch filtering group (corresponding to the 400-channel 700MHz band-pass filter), then the selection function of a four-select switch is used for selecting an AD chip with reference frequency configuration of 1.8GHz for digital down-conversion and decimation filtering processing, the echo signal with corresponding frequency is respectively processed by the frequency selection of a filter of a corresponding channel of the switch filtering group, and then is directly processed by decimation filtering after being processed by the digital down-conversion of the AD chip selected by the switch to be configured with the corresponding reference frequency. The sampled data are transmitted to the FPGA, and the FPGA adopts a XILINX ULTRASCALE FPGA series chip, has abundant logic resources and can realize different signal processing functions.

The external input signals comprise reference signals of 1.8GHz and 2.4GHz, trigger signals for controlling the working state of the components and common reference signals for realizing multi-channel synchronization, and the common reference signals serve as the reference of the multi-channel synchronization.

Claims

1. The utility model provides a radio frequency directly adopts digital transceiver circuit based on two sampling rates, includes analog TR subassembly, 400 ~ 2000 MHz's broadband radio frequency switch, switch filter group, 2 single channel AD chips that the highest input frequency is greater than or equal to 3GHz, 2 single channel DA chips that the highest output frequency is greater than or equal to 3GHz and the FPGA that realizes the signal processing function, its characterized in that:

the switch filter bank comprises two 400-2000MHz broadband radio frequency switches and four band-pass filters, wherein the pass band frequency ranges of the band-pass filters are respectively 400-700MHz, 1100-1600MHz, 700-1100MHz and 1600-2100 MHz;

in a transmitting state, the FPGA interpolates data to be transmitted to a high data rate, performs digital up-conversion and converts the data into radio frequency signals; the two DA chips input different reference frequencies, the reference frequency is 1.8GHz and 2.4GHz, and the DA chips with the reference frequency of 1.8GHz generate transmission signals of 400-700MHz and 1100-1600 MHz; a DA chip with the reference frequency of 2.4GHz generates transmitting signals of 700-1100MHz and 1600-2100 MHz; the transmitting signal is transmitted to the analog TR component through the four-in-one switch to realize the amplification of the radio frequency signal after the different filters are selected by the DA chip and the four-out switch which are selected by the switch;

in a receiving state, the two AD chips input different reference frequencies which are 1.8GHz and 2.4GHz respectively, and the AD chip with the reference frequency of 1.8GHz is used for processing echo signals of 400-700MHz and 1100-1600 MHz; the AD chip with the reference frequency of 2.4GHz is used for processing echo signals of 700-1100MHz and 1600-2100 MHz; the analog TR component completes low-noise amplification of a radio frequency echo signal, the echo signal is filtered by a band-pass filter of a corresponding frequency band, and a switch selects a corresponding AD chip to perform digital down-conversion and extraction filtering processing for down-sampling processing; and transmitting the sampled data to the FPGA.