CN109672490A - A kind of multiport tributary unit, signal processing method and storage medium - Google Patents
A kind of multiport tributary unit, signal processing method and storage medium Download PDFInfo
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- CN109672490A CN109672490A CN201710953723.7A CN201710953723A CN109672490A CN 109672490 A CN109672490 A CN 109672490A CN 201710953723 A CN201710953723 A CN 201710953723A CN 109672490 A CN109672490 A CN 109672490A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
Abstract
The invention discloses a kind of multiport tributary unit, signal processing method and storage mediums.Wherein, the signal processing method of the multiport tributary unit, comprising: poll reads the E1 data frame of each port from multiport memory according to the read control signal of generation；E1 data frame is converted into C4 data frame；C4 data frame is separated according to the port numbers of each port, the data frame after separation is written in the corresponding memory in each port.Unified clock signal port number can be used in the present invention, and successively poll reads or is written, and realizes the conversion between the low speed E1 signal of multiport and high speed C4 signal, effectively saves the logical resource and clock sources of FPGA, improves the stability of system operation.
Description
Technical field
The present invention relates to fields of communication technology, more particularly to a kind of multiport tributary unit, signal processing method and deposit
Storage media.
Background technique
In the SDH that rate is STM-1 (STM-Synchronous Transfer Module-1, synchronous transfer mode -1)
In (Synchronous Digital Hierarchy, synchronous digital system) optical communication network, when the system lateral line from equipment
Trackside send data when (down direction), the down direction of tributary unit (Tributary Unit, abbreviation TU) need by
The E1 signal of low speed becomes C4 signal by rate adaptation, mapping, positioning and multiplex process, and the clock of this treatment process is
19.44MHz.C4 signal is treated as STM-1 signal using high-order.When from the route side of equipment to system side send data
When (up direction), TU up direction need from the C4 signal of high speed extract E1 signal, this treatment process when
Clock is similarly 19.44MHz.
However when there is multiple ports STM-1 in equipment, it is independent for needing each port clock, that is to say, that is needed more
The conversion process of a individual E1 and C4 just can be achieved.And this kind of signal processing mode is used, it is patrolled when by may be programmed on a large scale
When collecting gate array (FPGA) realization, it will a large amount of logics, clock sources are consumed, last timing is influenced, causes fluctuation of service,
Even it cannot achieve since consumed resource is greater than selected device.
Summary of the invention
The embodiment of the present invention provides a kind of multiple port signal processing unit and method, to solve in the prior art using more
When a STM-1 port communication, the problem of consuming a large amount of fpga logics, clock sources.
For achieving the above object, the present invention uses following technical solutions:
According to one aspect of the present invention, a kind of signal processing method of multiport tributary unit is provided, downlink side is used for
To, comprising:
According to the read control signal of generation, poll reads the E1 data frame of each port from multiport memory；
The E1 data frame is converted into C4 data frame；
The C4 data frame is separated according to the port numbers of each port, each end is written into the data frame after separation
In the corresponding memory of mouth.
Optionally, the read control signal includes: port numbers, No. E1 and timeslot number；
Read control signal according to generation poll from multiport memory reads the E1 data frame of each port, packet
It includes:
Read address is generated according to port numbers, No. E1 and timeslot number and reads enable signal；
According to the read address and the E1 data frame read enable signal and read each port from multiport memory.
Optionally, it when generating E1, specifically includes:
The each port numbers of poll；
In the non-maximum value of port numbers, described No. E1 constant；
Port numbers be maximum value and it is described No. E1 be 62 when, be set to zero for described No. E1；
Port numbers be maximum value and it is described No. E1 be not 62 when, by described No. E1 plus 1；
Wherein, No. E1 value is 0 to 62.
Optionally, when generating timeslot number, comprising:
In the non-maximum value of port numbers, or port numbers be maximum value and it is described No. E1 be not 62 when, the timeslot number
It is constant；
Port numbers be maximum value, the timeslot number be not 36 and it is described No. E1 be 62 when, the timeslot number is added 1；
Port numbers be maximum value, the timeslot number be 36 and it is described No. E1 be maximum value when, the timeslot number is set to
1；
Wherein, the value of the timeslot number is 1 to 36.
Optionally, the E1 data frame is converted into C4 data frame, comprising:
The E1 data frame is configured to C12 base frame, and TU12 data frame is constructed based on the C12 base frame
C4 data frame described in idle, expense and Pointer generator is inserted into the TU12 data frame.
Optionally, after generating the read control signal, further includes: according to port numbers, No. E1 and described described
Timeslot number generates base frame number；
The E1 data frame is converted into C4 data frame, comprising:
Idle, expense and pointer byte are inserted into the TU12 data frame according to the base frame number, the timeslot number
Generate the C4 data frame.
Optionally, it is described according to the port numbers, No. E1 and the timeslot number generate base frame number, comprising:
When the port numbers, No. E1 and the timeslot number are maximum value, and the base frame number is 3, by institute
It states base frame number and is set to zero；
When the port numbers, No. E1 and the timeslot number are maximum value, and the base frame number is not 3, then
The base frame number adds 1；
When in the port numbers, No. E1 or the timeslot number it is any be non-maximum value when, then the base frame is compiled
It number remains unchanged；
Wherein, the value of the base frame number is 0 to 3.
According to one aspect of the present invention, a kind of signal processing method of multiport tributary unit is provided, uplink side is used for
To, comprising:
The received C4 data frame in each port is converted into TU12 data frame, and each end is written into the TU12 data frame
In the corresponding memory of mouth；
Poll reads the TU12 data frame in the corresponding memory in each port, and extracts E1 from the TU12 data frame
Data frame；
The E1 data frame of extraction is stored in multiport memory.
Optionally, described that the received C4 data frame in each port is converted into TU12 data frame, and by the TU12 data
Frame is written in the corresponding memory in each port, comprising:
C4 data frame data is configured to TU12 data frame；Wherein, line number is timeslot number, row number E1 in TU12 data frame
Number；
Base frame number is distributed for the base frame in TU12 data frame；
The corresponding memory in each port is written into base frame number, No. E1, timeslot number and TU12 data frame.
It is optionally, described that C4 data frame data is configured to TU12 data frame, comprising:
It is effectively indicated according to frame start mark in C4 data frame and data by the square of data configuration 9*260 in C4 data frame
Battle array；
Preceding 8 column invalid information in the matrix of 9*260 is rejected, the data frame of 9*252 is configured to；
The data frame of 9*252 is re-started ranks to calculate, is configured to the TU12 data frame of 36*63.
Optionally, the poll reads the TU12 data frame in the corresponding memory in each port, and from the TU12 number
According to extraction E1 data frame in frame, comprising:
Base frame number, No. E1 and timeslot number are extracted from the TU12 data frame, and according to data in TU12 data frame
The port numbers output end slogan at place；
Idle, expense and pointer word are rejected from the TU12 data frame according to the base frame number and the timeslot number
Section extracts E1 data frame.
It is optionally, described to store the E1 data frame of extraction in multiport memory, comprising:
It is used as write address according to the port numbers, the timeslot number and described No. E1, institute is written into the E1 data frame
It states in multiport memory.
According to one aspect of the present invention, a kind of multiport tributary unit, including memory and processor are provided；Wherein,
Executable instruction is stored in the memory；It is above-mentioned to realize when the executable instruction is executed by the processor
The signal processing method for down direction.
According to one aspect of the present invention, a kind of multiport tributary unit, including memory and processor are provided；Wherein,
Executable instruction is stored in the memory；It is above-mentioned to realize when the executable instruction is executed by the processor
The signal processing method for up direction.
According to one aspect of the present invention, a kind of computer readable storage medium, the computer-readable storage medium are provided
Matter is stored with computer-readable program, above-mentioned to realize when the computer-readable program is executed by the processor
Signal processing method for down direction.
According to one aspect of the present invention, a kind of computer readable storage medium, the computer-readable storage medium are provided
Matter is stored with computer-readable program, above-mentioned to realize when the computer-readable program is executed by the processor
Signal processing method for up direction.
The present invention has the beneficial effect that:
Multiport tributary unit, signal processing method and storage medium provided by the embodiment of the present invention, using unification
Clock signal, by time-multiplexed mode, successively poll reads or is written port number, and the low speed of multiport can be realized
Conversion between E1 signal and high speed C4 signal.The present invention implement it is very simple, effectively save FPGA logical resource and
Clock sources improve the stability of system operation.
The above description is only an overview of the technical scheme of the present invention, in order to better understand the technical means of the present invention,
And it can be implemented in accordance with the contents of the specification, and in order to allow above and other objects of the present invention, feature and advantage can
It is clearer and more comprehensible, the followings are specific embodiments of the present invention.
Detailed description of the invention
In order to illustrate the embodiments of the present invention more clearly or it is existing in scheme, below will be in embodiment or existing description
Required attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only of the invention some
Embodiment without any creative labor, can also be according to these attached drawings for ordinary people in the field
Obtain other attached drawings.
Fig. 1 is the process in the embodiment of the present invention for the signal processing method of the multiport tributary unit of down direction
Figure；
Fig. 2 is the frame structure schematic diagram of C12 data frame in the embodiment of the present invention；
Fig. 3 is the frame structure schematic diagram of TU12 data frame in the embodiment of the present invention；
Fig. 4 is the structural schematic diagram of 8 port tributary unit down directions in a specific embodiment of the invention；
Fig. 5 is 8 port polling state diagrams of a base frame in a specific embodiment of the invention；
Fig. 6 is the polling status figure of a multi-frame in the embodiment of the present invention；
Fig. 7 is the process in the embodiment of the present invention for the signal processing method of the multiport tributary unit of up direction
Figure；
Fig. 8 is the structural schematic diagram of 8 port tributary unit up directions in a specific embodiment of the invention；
Fig. 9 is the TU12 data polling read states figure of 8 ports in a specific embodiment of the invention；
Figure 10 is the functional block diagram in the embodiment of the present invention for the multiport tributary unit of down direction；
Figure 11 is the functional block diagram in the embodiment of the present invention for the multiport tributary unit of up direction.
Specific embodiment
Below in conjunction with attached drawing and embodiment, the present invention will be described in further detail.It should be appreciated that described herein
Specific embodiment be only used to explain the present invention, limit the present invention.
One embodiment of the invention provides a kind of signal processing method of multiport tributary unit, is used for down direction, such as Fig. 1
It is shown, specifically comprise the following steps:
Step 101, according to the read control signal of generation, poll reads the E1 data of each port from multiport memory
Frame；
Step 102, E1 data frame is converted into C4 data frame；
Step 103, C4 data frame is separated according to the port numbers of each port, the data frame after separation is written every
In the corresponding memory in a port.
Based on above-mentioned it is found that down direction in this embodiment, read control signal realize that the time-division is multiple by polling mode
With, in this way can to multiple ports carry out E1 data frame to the processing of C4 data frame, then C4 data frame is distributed to again each
In port.Therefore, the present invention uses unified clock signal, and multiple port E1 data frames can be realized and turn to C4 data frame
It changes, effectively saves the logical resource and clock sources of FPGA, improve the stability of system operation,
Read control signal in the embodiment of the present invention determined according to the number of port, clock signal 19.44MHz*
N, wherein N is the quantity of port.Here read control signal includes: port numbers, No. E1 and timeslot number；Wherein, port numbers
Port: the decimal system 0,1,2,3 ...；E1 colum: the label of 63 E1 in a port, value are 0 to 62；Timeslot number
36 data location labels in row: one C12 frame, value are 1 to 36.
When generating port numbers, the poll for realizing signal is polled to each port by state machine.It is held from first
Mouthful port0 a port port (N-1) to the end.
Optionally, in one embodiment of the invention, when generating E1, comprising: each port numbers of poll；It is non-most in port numbers
When big value, No. E1 constant；When port numbers are maximum value and No. E1 is 62, zero is set to by No. E1；Port numbers be maximum value and
No. E1 when not being 62, by No. E1 plus 1.
That is, after the corresponding No. m E1 data in the last one complete port of poll, m+1 starts each end of poll
No. m+1 E1 data of mouth.
Optionally, when generating timeslot number, comprising: in the non-maximum value of port numbers, or port numbers be maximum value and
No. E1 be 62 when, timeslot number is constant；Port numbers be maximum value, timeslot number be not 36 and No. E1 be 62 when, by timeslot number plus
1；Port numbers be maximum value, timeslot number be 36 and No. E1 be maximum value when, timeslot number is set to 1.
Based on above-mentioned it is found that when reading E1 data, sequentially in each port of poll identical E1 data identical time slot.?
That is the E1 data of the 1st time slot of the serial number 1 of first the 1st port of poll, then sequentially take turns according to port numbers in the sequence port
The E1 data of 1st time slot of serial number 1；When the data polling of the first time slot is complete, the serial number 1 in poll the 1st~N number of port
The E1 data of 2nd time slot, until the E1 data of the 36th time slot of the complete poll of poll the 1st~N number of port serial number 1；Then exist
The E1 data of 1st~36 time slot of the serial number 2 of the 1st~N number of port, until the 1st~serial number 1~63 of N number of port the 1st
The E1 data polling of~36 time slots is completed, successively the different time-gap of the different E1 of complete 8 ports of poll.
In a step 101, according to the read control signal of generation, poll reads the E1 of each port from multiport memory
When data frame, comprising: generate read address according to port numbers, No. E1 and timeslot number and read enable signal；Made according to read address and reading
Energy signal reads the E1 data frame of each port from multiport memory.
Each port E1 data can determine specific data by port numbers, No. E1 and timeslot number.Therefore, here will
Port numbers, No. E1 and timeslot number can accurately read all port E1 data as read address.Here, enabled letter is read
Number then for control the opportunity of reading data.Since the E1 data of reading need to meet the format of C12 data frame (such as Fig. 2 institute
Show), therefore it is required that E1 data are in the valid data region of C12 data frame.
Specifically, when reading E1 data according to read address and reading enable signal, because in 36 positions of C12 base frame,
Only 4-35 is filling valid data, thus only read when row is 4-35 it is enabled just effectively, read address for port,
Cloum, row }, when reading to enable effective, inside next clock cycle output current address { port, cloum, row }
E1 data frame.
In a step 102, the E1 data frame of multiple ports is converted into C4 data frame, comprising: be configured to E1 data frame
C12 base frame, and TU12 data frame is constructed based on C12 base frame；Idle, expense and Pointer generator C4 number are inserted into TU12 data frame
According to frame.
Wherein, it read to be gone according to C12 data frame shown in Fig. 2 (for the matrix of 9*4) structure when the data of an E1
It reads, from left to right, 36 from top to bottom successively marked as 1,2,3 ..., is indicated with row, wherein the E1 to read back is inserted in the position of 4-35
Data.Therefore, the data of E1 are inserted to the position of 4-35 according to row in construction C12 base frame here.
It when being inserted into expense to low speed signal is carried out according to the concept of multi-frame, an individual C12 data frame
A referred to as base frame, continuous 4 C12 base frame are known as a multi-frame (TU12 data frame).Continuous 4 C12 in one multi-frame
Base frame is by range in 0-3 base frame number multi_fr cyclic representation.After determining TU12 data frame, time-multiplexed side is being utilized
Method is inserted into idle bytes, expense and pointer in frame, and then generates C4 data frame.
Wherein, after generating read control signal, further comprise: base frame is generated according to port numbers, No. E1 and timeslot number
Number；Idle, expense is then inserted into TU12 data frame according to base frame number, timeslot number and pointer byte generates C4 data
Frame.Here, a C4 data frame is formed after being interleave by 63 TU12 data frames by byte.
Wherein, base frame number is generated according to port numbers, No. E1 and timeslot number, comprising: when port numbers, No. E1 and timeslot number are equal
For maximum value, and when base frame number is 3, base frame number is set to zero；When port numbers, No. E1 and timeslot number are maximum value, and
When base frame number is not 3, then base frame number adds 1；When in port numbers, No. E1 or timeslot number it is any be non-maximum value when, then
Base frame number remains unchanged.
Wherein, after generation multi_fr, port, row, colum, corresponding E1 data are returned from multiport memory
It wants evening to clap clock more, so when E1 data frame is multiplexed into C4 frame structure, is using multi_fr, port, row, when colum is wanted
First these labels evening corresponding umber of beats is reused, it could be corresponding with the data returned.
As shown in figure 3, being inserted into idle bytes in TU12 data frame, the method for expense and pointer is as follows:
Step 1: when multi_fr is equal to 0, row is inserted into pointer V1 byte for 1, and row is inserted into expense J2 word for 2
Section, row be 3 according to currently whether have bit adjustment insertion G byte (generation mechanism that the present invention is adjusted without reference to bit, when
Do no bit adjustment processing), row is inserted into idle bytes when being 36.
Step 2: when multi_fr is equal to 1, row is inserted into pointer V2 byte for 1, and row is inserted into expense N2 word for 2
Section, row be 3 according to currently whether have bit adjustment insertion G byte (generation mechanism that the present invention is adjusted without reference to bit, when
Do no bit adjustment processing), row is inserted into idle bytes when being 36.
Step 3: when multi_fr be equal to 2 when, row be 1 be inserted into pointer V3 byte (V3 is not used in practice, so
It is inserted into full 0), row is 2 to be inserted into expense K4 byte, is inserted into M, N byte according to currently whether there is bit to adjust when 3,4 row
(generation mechanism that the present invention is adjusted without reference to bit is handled as no bit adjustment), row is inserted into free word when being 36
Section.
Step 4: when multi_fr be equal to 3 when, row be 1 be inserted into pointer V4 byte (V4 is not used in practice, so
It is inserted into full 0), row is inserted into expense V5 byte for 2, and row is inserted into idle bytes when being 3, row is inserted into idle bytes when being 36.
It in step 103, can be by each port by the port numbers of C4 data frame in the corresponding memory in each port
Data store into corresponding memory.Each beat of data of C4 data frame has port numbers, is write data according to port numbers
Entering the memory of respective port, the write clock of the memory of several ports is unified 155.52MHZ clock, and from memory
The clock of middle reading is the clock of the sending side of respective port, i.e. 19.44MHz clock.
Below by taking 8 port tributary units as an example, the signal processing method of the down direction of multiport tributary unit is carried out
Explanation.
As shown in figure 4, the structural schematic diagram of 8 port tributary unit down directions.It include control letter in 8 port tributary units
C4 data frame module 43 and 8 port C4 numbers are made in number generation module 41,8 port E1 data read control modules 42, E1 data frame
Control module 44 is write according to frame；Wherein, the RAM45 (8_port_ of 8 port E1 data read control modules 42 and 8 port E1 data of storage
E1_data_ram, multiport memory) it is connected；Control the port of signal generator module 41 and 8 E1 data read control module 42, E1
C4 data frame module 43 is made in data frame, 8 port C4 data frames write control module 44 and are connected；8 port C4 data frames write control mould
Block 44 is connected with the memory 46 that C4 data frame module 43 and 8 storage C4 data frames are made in E1 data frame.
Specifically, the data of all E1 of 8 ports are stored in 8_port_E1_data_ram, each E1 distributes 32
Memory space is used to store 32 time slots respectively.8_port_E1_data_ram is written the clock of data and reads the clock of data
It is the same, is all 155.52MHz.
It controls signal generator module 41 and base frame number, port numbers, No. E1, timeslot number is generated by the method for poll.Such as Fig. 5
Shown in state machine, generate port, row, colum, when reset enters port_idle state, resets after release successively poll 8
Port, from a port port0, a port port7, each port status stop one and clap to the end.
The generation of port: No. port is the port numbers for being currently located port status.
The generation of colum: port0 to port6 is remained unchanged, and current colum value is judged when port7, is equal to 62
Otherwise plus 1 with regard to zero setting, other situations are remained unchanged.
The generation of row: port0 to port6 is remained unchanged, and is judged when port7, if current row be 36 and
Colum just sets 1 for 62, and if current row adds 1 without being 62 for 36 and colum, other situations are remained unchanged.
The generation of multi_fr: as shown in fig. 6, being in IDLE state when resetting, it is laggard to reset end by multi_fr 0
Enter FR0 state, i.e., the read states of first base frame, FR1, FR2, FR3 is respectively second and third, the read states of four base frames, each
It is judgement that state, which is in port7 in port status, if row is 36, and colum is 62 with regard to strip to next base frame state,
Multi_fr is the base frame number of current base frame state instruction.
The port that 8 port E1 data read control modules 42 are exported using control signal generator module 41, row, colum are generated
Read address and reading are enabled, and then from 8_port_E1_data_ram, (down direction stores the storage of all E1 data of 8 ports
Device, each E1 store a frame, i.e. 32 bytes) different time-gap of successively different E1 of 8 ports of poll.Because in C12 base frame
36 positions, only 4-35 is filling valid data, so only reading enabled just effective, read address when row is 4-35
For { port, cloum, row }, when reading to enable effective, 8_port_E1_data_ram can be defeated in next clock cycle
Data inside current address { port, cloum, row } out.
C4 data frame module 43 is made in E1 data frame believes according to the 8_port_E1_data_ram data returned and control
The multi_fr, port, row that number generation module 41 exports, colum are inserted into the free time using time-multiplexed method on each E1
Byte, expense and pointer.After the control generation of signal generator module 41 multi_fr, port, row, colum, from 8_port_
E1_data_ram returns to corresponding data and wants late 13 to clap clock, so using in E1 data-reusing to C4 frame structure module 103
These labels are first played 13 bats when multi_fr, port, row, colum to reuse, it could be corresponding with the data returned.For
Idle bytes are inserted into, the process of expense and pointer, I will not elaborate.
Based on above-mentioned it is found that in this embodiment, the data read back from RAM are continuous, and are the knots according to 3-7-3
Structure goes to generate No. E1, so reading the multiplexing for being just 3-7-3 when data.Need to only have accordingly in the data read back
Port numbers, No. E1 and timeslot number read back in corresponding position by filling, expense and pointer or from RAM in conjunction with base frame number
Data are inserted into C12 frame, are just configured to C4 frame.
8 port C4 data frames write control module 44 and are corresponded to the C4 data frame write-in of output according to the port numbers of current data
The memory of the storage C4 frame of the port 0-7, i.e. in port0_C4_data_fifo to port7_C4_data_fifo.This 8
The write clock of FIFO is unified 155.52MHZ clock, and the clock of reading is the sending side 19.44MHz clock of respective port.
Based on above-mentioned it is found that 8 port tributary units are in signal processing provided by the embodiment, using unified clock
Signal realizes that the low speed E1 signal of multiport is converted to the conversion between high speed C4 signal by time-multiplexed mode.This hair
It is bright to implement very simple, effective logical resource and clock sources for saving FPGA, the stability of raising system operation.
A kind of signal processing method of multiport tributary unit provided by another embodiment of the present invention is used for uplink side
To, as shown in fig. 7, comprises:
Step 701, the received C4 data frame in each port is converted into TU12 data frame, and TU12 data frame is written often
In the corresponding memory in a port；
Step 702, poll reads the TU12 data frame in the corresponding memory in each port, and mentions from TU12 data frame
Take E1 data frame；
Step 703, the E1 data frame of extraction is stored in multiport memory.
Based on above-mentioned it is found that the present invention is in up direction, C4 data frame is pre-processed under the reception clock of respective port,
TU12 data frame is constructed, then extracts the E1 data frame of multiple ports using time-multiplexed method under unified clock.In this way
Realization achieved the effect that simplified design, save the logical resource and clock sources of FPGA, improve system operation it is steady
It is fixed
Optionally, in step 701, the received C4 data frame in each port is converted into TU12 data frame, and by TU12
The corresponding memory in each port is written in data frame, comprising:
C4 data frame data is configured to TU12 data frame；Wherein, line number is timeslot number, row number E1 in TU12 data frame
Number；
Base frame number is distributed for the base frame in TU12 data frame；
The corresponding memory in each port is written into base frame number, No. E1, timeslot number and TU12 data frame.
Here, timeslot number, No. E1 are obtained by the conversion of frame format.And base frame encodes by way of beating and clapping and TU12
Base frame alignment in data frame.The information and TU12 data frame that then will acquire are written in memory again.
Wherein, C4 data frame data is constructed into TU12 data frame, comprising: according to frame start mark and number in C4 data frame
It indicates according to effective by the matrix of data configuration 9*260 in C4 data frame；Reject preceding 8 column invalid information in the matrix of 9*260, construction
For the data frame of 9*252；The data frame of 9*252 is re-started ranks to calculate, is configured to the TU12 data frame of 36*63.
Optionally, in a step 702, poll reads the TU12 data frame in the corresponding memory in each port, and from
E1 data frame is extracted in TU12 data frame, comprising:
Base frame number, No. E1 and timeslot number are extracted from TU12 data frame, and according to where data in TU12 data frame
Port numbers output end slogan；
Idle, expense and pointer byte are rejected from TU12 data frame according to base frame number, timeslot number, extracts E1 data
Frame.
Wherein, in step 701, in timeslot number, No. E1, port numbers and base frame number and TU12 data frame, in the step
In rapid, need to obtain these information from memory by way of poll, from according to information by the free time in TU12 data frame
Etc. bytes delete, obtain the E1 data frame of all of the port.
Optionally, in step 703, the E1 data frame of extraction is stored in multiport memory, comprising:
It is used as write address according to port numbers, timeslot number and No. E1, E1 data frame is written in multiport memory.
In this step, write address is used as according to the port numbers of acquisition, timeslot number and No. E1, each E1 stores a frame and is
32 time slots, 32 time slots of each E1 ceaselessly recurrent wrIting.
Below by taking 8 port tributary units as an example, the signal processing method of the up direction of multiport tributary unit is carried out
Explanation.8 ports are not limited solely in SDH network, it can also be used to the application of more or less port number.
As shown in figure 8, the structural schematic diagram of 8 port tributary unit up directions.The 8 port tributary unit includes: TU12
Data frame constructing module 81,8 port TU12 data read control modules 82, extraction E1 data module 83 and 8 port E1 data are write
Control module 84；8 TU12 data storages 85 (port0_C4_data_fifo_rx, port1_C4_data_fifo_rx ...
Port7_C4_data_fifo_rx) and
The E1 data storage 86 (multiport memory, 8_port_E1_data_ram_rx) of 8 ports；Wherein, respectively
The TU12 data frame constructing module 81 of port connects the TU12 data storage 85 of respective port；8 port TU12 data read control
Module 82 connects the TU12 data storage 85 of 8 ports；It extracts E1 data module 83 and connects 8 port TU12 data reading control mould
82,8 port E1 data of block write the connection of control module 84 and extract E1 data module 83, while connecting the E1 data storage of 8 ports
Device 86.
TU12 data frame constructing module 81 is configured to the number of 36*63 by the C4 data frame procession calculating to input
According to structure, line number is timeslot number, and row number is No. E1, while providing base frame number, then by base frame number, timeslot number, No. E1 with
And the TU12 memory of the port is written in effective TU12 data.
Specifically, there is oneself independent TU12 data frame constructing module 81 in each port, and the C4 data frame of input has sof
(frame start mark), vld (data effectively indicate), data (C4 data) and h4 (base frame number), and construct 36*63's
Then TU12 data frame format writes data into respective port TU12 memory, the specific steps are as follows:
Step 1, according to sof and vld to the matrix of the C4 data configuration 9*260 of input；
Step 2, it then takes and rejects preceding 8 column invalid information, be configured to the data frame of 9*252；
Step 3, ranks calculating is re-started on the basis of the data frame of 9*252, is configured to the data frame of 36*63, line number
For timeslot number, row number is No. E1；
Step 4, the h4 of input is beaten to the data frame alignment after clapped with 36*63.
Step 5, by base frame number, No. E1, the TU12 storage of respective port is written after timeslot number and valid data splicing
Device, port0_TU12_data_fifo_rx to port7_TU12_data_fifo_rx.
This above process is that each port is independent, is carried out under respective reception 19.44MHz clock., subsequent each
Module is extracted and is written the E1 data of 8 ports using time-multiplexed method under 155.52MHz clock.
8 port TU12 data read control modules 82 poll at high-frequency clock 155.52MHz reads the TU12 data of 8 ports
Memory 85 parses base frame number, timeslot number, No. E1 and effective TU12 data from the data of reading, while adding again
It is exported after adding port numbers.
Specifically, 8 port TU12 data read control modules 82 read 8 ports according to state machine poll shown in Fig. 9
TU12 data storage 85, each port assignment one are clapped, and memory has data to attend school, just do not read, specific steps are as follows:
Step 1, port_idle state is entered when reset, resetting terminates to enter port0 state,；
Step 2, in port0 state, port0_TU12_data_fifo_rx is read, subsequently into port1 state；
Step 3, in port1 state, port1_TU12_data_fifo_rx is read, subsequently into port2 state；
Step 4, in port2 state, port2_TU12_data_fifo_rx is read, subsequently into port3 state；
Step 5, in port3 state, port3_TU12_data_fifo_rx is read, subsequently into port4 state；
Step 6, in port4 state, port4_TU12_data_fifo_rx is read, subsequently into port5 state；
Step 7, in port5 state, port5_TU12_data_fifo_rx is read, subsequently into port6 state；
Step 8, in port6 state, port6_TU12_data_fifo_rx is read, subsequently into port7 state；
Step 9, in port7 state, port7_TU12_data_fifo_rx is read, subsequently into port0 state；
The data of reading are parsed, extract data TU12_data, data effectively indicate TU12_valid, E1 TU12_
Colum, timeslot number TU12_row, base frame number TU12_h4, while according to the port numbers output end slogan TU12_ where the data
port。
E1 data module 83 is extracted at high-frequency clock 155.52MHz according to port numbers, timeslot number and No. E1 positioning
TU12 frame removes corresponding expense, pointer and filling, extracts effective E1 data.
Specifically, the TU12 multi-frame format that E1 data module 83 combines Fig. 3 is extracted, using time-multiplexed method for each
A E1 extracts expense V5, J2, N2, K4, pointer V1, V2, V3, V4 and removal free message, finally exports E1_data (E1
Data), E1_valid (E1 data effectively indicate), E1_port (port numbers of E1 data), the E1_colum (E1 of E1 data
Number), E1_row (timeslot numbers of E1 data).
8 port E1 data write control module 84 according to effective E1 data, the port numbers of input, and No. E1 and timeslot number will
The E1 data storage 86 of 8 ports is written in effective E1 data frame.
Specifically, E1 data are written to the E1 data storage 86 (8_port_E1_data_ram_rx) of 8 ports.By E1_
It is used as write address after port, E1_colum and E1_row splicing, each E1 stores a frame i.e. 32 time slot, and 32 of each E1
Time slot ceaselessly recurrent wrIting.
Further embodiment of this invention additionally provides a kind of multiport tributary unit, is used for down direction for realizing above-mentioned
Signal processing method.As shown in Figure 10.The multiport tributary unit includes processor 12 and is stored with processor 12 and can hold
The memory 11 of row instruction.
Wherein, processor 12 can be general processor, such as central processing unit (central processing unit,
CPU), it can also be digital signal processor (digital signal processor, DSP), specific integrated circuit
(application specific integrated circuit, ASIC), or be arranged to implement the embodiment of the present invention
One or more integrated circuits.
Memory 11 is transferred to CPU for storing program code, and by the program code.Memory 11 may include easy
The property lost memory (volatile memory), such as random access memory (random access memory, RAM)；Storage
Device 11 also may include nonvolatile memory (non-volatile memory), such as read-only memory (read-only
Memory, ROM), flash memory (flash memory), hard disk (hard disk drive, HDD) or solid state hard disk
(solid-state drive, SSD)；Memory 11 can also include the combination of the memory of mentioned kind.
Yet another embodiment of the invention additionally provides a kind of multiport tributary unit, is used for up direction for realizing above-mentioned
Signal processing method.As shown in figure 11.The multiport tributary unit includes processor 22 and is stored with processor 22 and can hold
The memory 21 of row instruction.
Wherein, processor 22 can be general processor, such as central processing unit, can also be digital signal processor,
Specific integrated circuit, or be arranged to implement one or more integrated circuits of the embodiment of the present invention.Memory 21, is used for
Program code is stored, and the program code is transferred to CPU.Memory 21 may include volatile memory, such as deposit at random
Access to memory；Memory 21 also may include nonvolatile memory, such as read-only memory, flash memory, hard disk or solid
State hard disk；Memory 21 can also include the combination of the memory of mentioned kind.
The embodiment of the invention also provides a kind of computer readable storage mediums.Here computer readable storage medium is deposited
Contain one or more program.When one or more program can be by one or more in computer readable storage medium
It manages device to execute, to realize the signal processing method of the down direction of above-mentioned multiport tributary unit.It is specifically real for step
It is existing, it may refer to the detailed description in embodiment of the method, no longer repeated in this embodiment.
The embodiment of the invention also provides a kind of computer readable storage mediums.Here computer readable storage medium is deposited
Contain one or more program.When one or more program can be by one or more in computer readable storage medium
It manages device to execute, to realize the signal processing method of the up direction of above-mentioned multiport tributary unit.It is specifically real for step
It is existing, it may refer to the detailed description in embodiment of the method, no longer repeated in this embodiment.
Those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method, being can be with
Relevant hardware is instructed to complete by computer program, program can be stored in computer-readable storage medium, the journey
Sequence is when being executed, it may include such as the process of the embodiment of above-mentioned each method.
Although describing the application by embodiment, it will be apparent to one skilled in the art that the application is there are many deformation and becomes
Change without departing from the spirit and scope of the present invention.If being wanted in this way, these modifications and changes of the present invention belongs to right of the present invention
Ask and its equivalent technologies within the scope of, then the present invention is also intended to include these modifications and variations.
Claims (16)
1. a kind of signal processing method of multiport tributary unit, which is characterized in that the described method includes:
According to the read control signal of generation, poll reads the E1 data frame of each port from multiport memory；
The E1 data frame is converted into C4 data frame；
The C4 data frame is separated according to the port numbers of each port, each port pair is written into the data frame after separation
In the memory answered.
2. signal processing method as described in claim 1, which is characterized in that the read control signal includes: port numbers, No. E1
And timeslot number；
Read control signal according to generation poll from multiport memory reads the E1 data frame of each port, comprising:
Read address is generated according to port numbers, No. E1 and timeslot number and reads enable signal；
According to the read address and the E1 data frame read enable signal and read each port from multiport memory.
3. signal processing method as claimed in claim 2, which is characterized in that when generating E1, specifically include:
The each port numbers of poll；
In the non-maximum value of port numbers, described No. E1 constant；
Port numbers be maximum value and it is described No. E1 be 62 when, be set to zero for described No. E1；
Port numbers be maximum value and it is described No. E1 be not 62 when, by described No. E1 plus 1；
Wherein, No. E1 value is 0 to 62.
4. signal processing method as claimed in claim 3, which is characterized in that when generating timeslot number, comprising:
In the non-maximum value of port numbers, or port numbers be maximum value and it is described No. E1 be not 62 when, the timeslot number is constant；
Port numbers be maximum value, the timeslot number be not 36 and it is described No. E1 be 62 when, the timeslot number is added 1；
Port numbers be maximum value, the timeslot number be 36 and it is described No. E1 be maximum value when, the timeslot number is set to 1；
Wherein, the value of the timeslot number is 1 to 36.
5. the signal processing method as described in any one of claim 2 to 4, which is characterized in that convert the E1 data frame
At C4 data frame, comprising:
The E1 data frame is configured to C12 base frame, and TU12 data frame is constructed based on the C12 base frame
C4 data frame described in idle, expense and Pointer generator is inserted into the TU12 data frame.
6. signal processing method as claimed in claim 5, which is characterized in that after generating the read control signal, also wrap
It includes: according to the port numbers, No. E1 and the timeslot number generation base frame number；
The E1 data frame is converted into C4 data frame, comprising:
Idle, expense is inserted into the TU12 data frame according to the base frame number, the timeslot number and pointer byte generates
The C4 data frame.
7. signal processing method as claimed in claim 6, which is characterized in that it is described according to the port numbers, it is described No. E1 and
The timeslot number generates base frame number, comprising:
When the port numbers, No. E1 and the timeslot number are maximum value, and the base frame number is 3, by the base
Frame number is set to zero；
It is when the port numbers, No. E1 and the timeslot number are maximum value, and the base frame number is not 3, then described
Base frame number adds 1；
When in the port numbers, No. E1 or the timeslot number it is any be non-maximum value when, then the base frame number is protected
It holds constant；
Wherein, the value of the base frame number is 0 to 3.
8. a kind of signal processing method of multiport tributary unit, which is characterized in that the described method includes:
The received C4 data frame in each port is converted into TU12 data frame, and each port pair is written into the TU12 data frame
In the memory answered；
Poll reads the TU12 data frame in the corresponding memory in each port, and E1 data are extracted from the TU12 data frame
Frame；
The E1 data frame of extraction is stored in multiport memory.
9. signal processing method as claimed in claim 8, which is characterized in that described to turn the received C4 data frame in each port
It is changed to TU12 data frame, and the TU12 data frame is written in the corresponding memory in each port, comprising:
C4 data frame data is configured to TU12 data frame；Wherein, line number is timeslot number in TU12 data frame, and row number is No. E1；
Base frame number is distributed for the base frame in TU12 data frame；
The corresponding memory in each port is written into base frame number, No. E1, timeslot number and TU12 data frame.
10. signal processing method as claimed in claim 8, which is characterized in that described that C4 data frame data is configured to TU12
Data frame, comprising:
It is effectively indicated according to frame start mark in C4 data frame and data by the matrix of data configuration 9*260 in C4 data frame；
Preceding 8 column invalid information in the matrix of 9*260 is rejected, the data frame of 9*252 is configured to；
The data frame of 9*252 is re-started ranks to calculate, is configured to the TU12 data frame of 36*63.
11. signal processing method as claimed in claim 9, which is characterized in that each port of the poll reading is corresponding to deposit
TU12 data frame in reservoir, and E1 data frame is extracted from the TU12 data frame, comprising:
Base frame number, No. E1 and timeslot number are extracted from the TU12 data frame, and according to where data in TU12 data frame
Port numbers output end slogan；
Idle, expense and pointer byte are rejected from the TU12 data frame according to the base frame number and the timeslot number,
Extract E1 data frame.
12. signal processing method as claimed in claim 9, which is characterized in that the E1 data frame by extraction is more
It is stored in port store, comprising:
It is used as write address according to the port numbers, the timeslot number and described No. E1, the E1 data frame is written described more
In port store.
13. a kind of multiport tributary unit, which is characterized in that including memory and processor；Wherein, it is stored in the memory
There is executable instruction；When the executable instruction is executed by the processor, to realize any institute of claim 1~7
The signal processing method stated.
14. a kind of multiport tributary unit, which is characterized in that including memory and processor；Wherein, it is stored in the memory
There is executable instruction；When the executable instruction is executed by the processor, to realize that right 8~12 is any described
Signal processing method.
15. a kind of computer readable storage medium, which is characterized in that the computer-readable recording medium storage has computer can
Reader, when the computer-readable program is executed by the processor, to realize that claim 1~7 is any described
Signal processing method.
16. a kind of computer readable storage medium, which is characterized in that the computer-readable recording medium storage has computer can
Reader, when the computer-readable program is executed by the processor, to realize that claim 8~12 is any described
Signal processing method.
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Application publication date: 20190423 |