CN109659397B - IBC battery and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 71
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 59
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 59
- 239000010703 silicon Substances 0.000 claims abstract description 59
- 229920005591 polysilicon Polymers 0.000 claims abstract description 58
- 238000005286 illumination Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 38
- 238000005498 polishing Methods 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 239000002002 slurry Substances 0.000 abstract description 9
- 239000000969 carrier Substances 0.000 abstract description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract description 4
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 144
- 238000006243 chemical reaction Methods 0.000 description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 7
- 238000002161 passivation Methods 0.000 description 7
- 229910052698 phosphorus Inorganic materials 0.000 description 7
- 239000011574 phosphorus Substances 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000004050 hot filament vapor deposition Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
- H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The application discloses an IBC battery manufacturing method, which comprises the steps of forming an n + layer in a high-temperature propelling mode on a local area of a first surface of a silicon wafer, wherein the first surface is opposite to the surface of the silicon wafer, which receives illumination; forming a polysilicon layer on the first surface, wherein the polysilicon layer is not overlapped with the n + layer; performing film opening treatment on the film layer positioned on the first surface to form a gap; forming an electrode in the gap. According to the manufacturing method of the IBC battery, the polycrystalline silicon layer is deposited to replace printing of boron slurry, the polycrystalline silicon layer can be used as a p + layer and also can be used as an emitting layer to increase transmission of photon-generated carriers, and therefore performance of the IBC battery is improved. In addition, the application also provides the IBC battery with the advantages.
Description
Technical Field
The application relates to the technical field of solar cell manufacturing, in particular to an IBC cell and a manufacturing method thereof.
Background
The solar cell is a device capable of converting solar energy into electric energy, and has a very wide application prospect, so that the photovoltaic industry develops rapidly in recent years. With the development of the photovoltaic industry, the improvement of the photoelectric conversion efficiency of the solar cell is a target continuously pursued by photovoltaic enterprises.
An IBC (indirect Back Contact) cell is a solar cell having a front surface without a grid electrode, and positive and negative electrodes are arranged on the Back surface of the cell in a crossed manner. Because the IBC cell has the characteristics that the front side is not shielded by an electrode, and an n + structure and a p + structure are both arranged on the back side of the cell, the photoelectric conversion efficiency of the IBC cell is improved compared with that of the traditional crystalline silicon solar cell, and the IBC cell gradually becomes a research hotspot.
The existing IBC battery manufacturing method is shown in figure 1, PSG and BSG after laser ablation are not removed, and certain influence is caused on subsequent printed metal electrodes, so that the performance of the IBC battery is influenced.
Disclosure of Invention
The application aims to provide an IBC battery and a manufacturing method thereof, so as to improve the performance of the IBC battery.
In order to solve the above technical problem, the present application provides an IBC battery manufacturing method, including:
forming an n + layer in a local area of a first surface of a silicon wafer in a high-temperature propelling mode, wherein the first surface is opposite to the surface of the silicon wafer, which receives light irradiation;
forming a polysilicon layer on the first surface, wherein the polysilicon layer is not overlapped with the n + layer;
performing film opening treatment on the film layer positioned on the first surface to form a gap;
forming an electrode in the gap.
Optionally, the high-temperature advancing conditions are as follows:
under the nitrogen atmosphere, the temperature ranges from 700 ℃ to 850 ℃, and the time ranges from 20min to 60min, including all endpoints.
Optionally, before the step of forming the n + layer in the first surface local region of the silicon wafer, the method further includes:
and forming an oxide layer on the surface of the silicon wafer.
Optionally, the forming a polysilicon layer on the first surface includes:
and forming an undoped polysilicon layer and a P-type polysilicon layer on the first surface.
Optionally, the film opening treatment of the film layer on the first surface includes:
and carrying out laser film opening treatment on the film layer positioned on the first surface.
Optionally, an n + layer is formed in a local area of the first surface of the silicon wafer by using a high-temperature propulsion method, where before the first surface is opposite to the surface of the silicon wafer receiving the light, the method further includes:
performing texturing treatment on the surface receiving illumination;
and carrying out polishing treatment on the first surface.
The application also provides an IBC battery, which comprises the IBC battery manufactured by the IBC battery manufacturing method.
Optionally, the thickness of the polysilicon layer ranges from 10nm to 20nm, inclusive.
The IBC battery manufacturing method comprises the steps of forming an n + layer in a high-temperature propelling mode on a local area of a first surface of a silicon wafer, wherein the first surface is opposite to the surface, which receives light, of the silicon wafer; forming a polysilicon layer on the first surface, wherein the polysilicon layer is not overlapped with the n + layer; performing film opening treatment on the film layer positioned on the first surface to form a gap; forming an electrode in the gap. According to the manufacturing method of the IBC battery, the polycrystalline silicon layer is deposited to replace printing of boron slurry, the polycrystalline silicon layer can be used as a p + layer and also can be used as an emitting layer to increase transmission of photon-generated carriers, and therefore performance of the IBC battery is improved. In addition, the application also provides the IBC battery with the advantages.
Drawings
For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flow chart of a prior art method of manufacturing an IBC cell;
fig. 2 is a flowchart of a method for manufacturing an IBC cell according to an embodiment of the present disclosure;
fig. 3 is another flowchart of a method for manufacturing an IBC cell according to an embodiment of the present disclosure;
fig. 4 is another flowchart of a method for manufacturing an IBC cell according to an embodiment of the present disclosure.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
As described in the background art, the IBC cell manufactured in the prior art has poor performance in the aspects of photoelectric conversion efficiency, short-circuit current, open-circuit voltage, and the like, and needs to be improved.
In view of the above, the present application provides a method for manufacturing an IBC battery, please refer to fig. 2, where fig. 2 is a flowchart of a method for manufacturing an IBC battery according to an embodiment of the present application, and the method includes:
step S201: and forming an n + layer in a local area of a first surface of the silicon wafer in a high-temperature propelling manner, wherein the first surface is opposite to the surface of the silicon wafer, which receives the illumination.
Specifically, a local area of the first surface of the silicon wafer is covered with phosphorus slurry, and an n + layer is formed in the local area of the first surface of the silicon wafer by adopting a high-temperature propulsion mode. Covering a local area of the first surface of the silicon wafer with phosphorus slurry, wherein the phosphorus slurry is more easily doped into the silicon wafer to form an n + layer before the step of forming the passivation film layer; and (3) obtaining an n + layer with uniform phosphorus distribution and moderate depth by adopting a high-temperature propulsion mode.
Specifically, in an embodiment of the present application, the phosphorus paste is covered on the local area of the first surface of the silicon wafer by a printing method, but the present application is not particularly limited thereto.
Step S202: and forming a polysilicon layer on the first surface, wherein the polysilicon layer is not overlapped with the n + layer.
Specifically, a polysilicon layer is formed in a region of the silicon wafer other than the n + layer on the first surface.
It should be noted that, in the embodiment of the present application, a manner of forming the polysilicon layer is not particularly limited, and may be selected by itself. For example, the polysilicon layer may be formed by plasma enhanced chemical vapor deposition, or by low pressure chemical vapor deposition. The specific working principle of the two methods is well known to those skilled in the art, and will not be described in detail.
It should be noted that, in this embodiment, the thickness of the polysilicon layer is not particularly limited, as the case may be.
Specifically, in an embodiment of the present application, when the polysilicon layer is formed, a thickness of the polysilicon layer ranges from 10nm to 20nm, including an end point value, which prevents the polysilicon layer from being too small in thickness, so that the photoelectric conversion efficiency is limited, and simultaneously prevents the polysilicon layer from being too large in thickness, so that a required process time is prolonged, which results in low efficiency, material waste, and cost increase.
It should be noted that, in this embodiment, the number of layers for forming the polysilicon layer is not particularly limited.
Step S203: and forming an antireflection film layer on the surface receiving the illumination.
An antireflection film layer is formed on the surface of the silicon chip receiving the illumination, so that the quantity of light absorbed by the silicon chip is increased, and the photoelectric conversion efficiency is improved.
It should be noted that, in the present embodiment, the method for forming the anti-reflection film layer is not particularly limited, as the case may be.
Specifically, in one embodiment of the present application, a plasma enhanced chemical vapor deposition method is used to form an antireflective coating layer on the surface of a silicon wafer receiving light. In another embodiment of the present application, the antireflection film layer is formed on the surface of the silicon wafer receiving light by using low-pressure chemical vapor deposition. The specific working principle of the two methods is well known to those skilled in the art, and will not be described in detail.
Step S204: and forming a passivation film layer on the surfaces of the n + layer and the polycrystalline silicon layer, which are far away from the silicon wafer.
It should be noted that, in the present embodiment, the method for forming the passivation film layer is not particularly limited, and may be determined as the case may be.
Specifically, in an embodiment of the present application, a passivation film layer may be formed on the surfaces of the n + layer and the polysilicon layer away from the silicon wafer by using a plasma enhanced chemical vapor deposition method. In another embodiment of the present application, a passivation film layer is formed on the surfaces of the n + layer and the polysilicon layer facing away from the silicon wafer by hot filament chemical vapor deposition. The specific working principle of the two methods is well known to those skilled in the art, and will not be described in detail.
Step S205: and performing film opening treatment on the film layer positioned on the first surface to form a gap.
In the present embodiment, the method of the film opening treatment is not particularly limited, and may be selected.
Step S206: forming an electrode in the gap.
Specifically, the local area of the first surface of the silicon wafer is covered with the phosphorus slurry, a high-temperature propulsion mode is adopted, when an n + layer is formed in the local area of the first surface of the silicon wafer, phosphorosilicate glass is formed at the same time, furthermore, when a polycrystalline silicon layer is formed, the first surface of the silicon wafer is completely covered with the polycrystalline silicon layer, then the polycrystalline silicon layer in the area corresponding to the phosphorosilicate glass and the n + layer is removed, the influence on electrode formation can be reduced, and therefore the performance of the IBC battery is improved.
The IBC battery manufacturing method comprises the steps of forming an n + layer in a high-temperature propelling mode on a local area of a first surface of a silicon wafer, wherein the first surface is opposite to the surface, which receives illumination, of the silicon wafer; forming a polysilicon layer on the first surface, wherein the polysilicon layer is not overlapped with the n + layer; performing film opening treatment on the film layer positioned on the first surface to form a gap; forming an electrode in the gap. According to the manufacturing method of the IBC battery, the polycrystalline silicon layer is deposited to replace printing of boron slurry, the polycrystalline silicon layer can be used as a p + layer and also can be used as an emitting layer to increase transmission of photon-generated carriers, and therefore performance of the IBC battery is improved.
On the basis of any of the above embodiments, in an embodiment of the present application, the high temperature advance conditions are:
under the nitrogen atmosphere, the temperature ranges from 700 ℃ to 850 ℃, and the time ranges from 20min to 60min, including all endpoints.
On the basis of any one of the foregoing embodiments, in an embodiment of the present application, the performing a film opening process on the film layer located on the first surface includes:
and carrying out laser film opening treatment on the film layer positioned on the first surface.
In this embodiment, the film opening treatment is performed on the film layer on the first surface of the silicon wafer in a laser die opening treatment mode, so that the process is simple, and the width and the position of the gate line can be adjusted as required.
Referring to fig. 3, fig. 3 is another flow chart of a method for manufacturing an IBC cell according to an embodiment of the present disclosure.
Step S301: and forming an oxide layer on the surface of the silicon wafer.
Specifically, a silicon oxide film layer is formed on the whole surface of the silicon wafer.
Step S302: and forming an n + layer in a local area of a first surface of the silicon wafer in a high-temperature propelling manner, wherein the first surface is opposite to the surface of the silicon wafer, which receives the illumination.
Step S303: and forming a polysilicon layer on the first surface, wherein the polysilicon layer is not overlapped with the n + layer.
Step S304: and forming an antireflection film layer on the surface receiving the illumination.
Step S305: and forming a passivation film layer on the surfaces of the n + layer and the polycrystalline silicon layer, which are far away from the silicon wafer.
Step S306: and performing film opening treatment on the film layer positioned on the first surface to form a gap. In this embodiment, when the laser film opening method is selected to perform the film opening processing on the film layer on the first surface of the silicon wafer, the low-energy laser is selected when the film opening processing is performed on the region corresponding to the n + layer, the oxide layer is not removed, that is, the oxide layer is not affected, and the high-energy laser is selected when the film opening processing is performed on the region corresponding to the p + layer, so that the oxide layer is removed.
It should be noted that the high energy and the low energy of the laser are relative, for example, the power of the device for generating laser energy is a certain percentage of the power when the corresponding region of the n + layer is processed by opening the film, and the power of the device for generating laser energy is another higher percentage of the power when the corresponding region of the p + layer is processed by opening the film.
Step S307: forming an electrode in the gap.
On the basis of any one of the above embodiments, in an embodiment of the present application, the forming a polysilicon layer on the first surface includes:
and forming an undoped polysilicon layer and a P-type polysilicon layer on the first surface.
In the embodiment of the application, the undoped polysilicon layer and the P-type polysilicon layer are sequentially formed on the first surface of the silicon wafer, namely the polysilicon layer comprises two film layers serving as an emission layer, so that the transportation of photon-generated carriers is further enhanced, and the performances of the IBC cell in the aspects of photoelectric conversion efficiency, short-circuit current, open-circuit voltage and the like are improved.
Referring to fig. 4, fig. 4 is another flowchart of a method for manufacturing an IBC cell according to an embodiment of the present disclosure.
Step S401: performing texturing treatment on the surface receiving illumination; and carrying out polishing treatment on the first surface.
Step S402: and forming an n + layer in a local area of a first surface of the silicon wafer in a high-temperature propelling manner, wherein the first surface is opposite to the surface of the silicon wafer, which receives the illumination.
Step S403: and forming a polysilicon layer on the first surface, wherein the polysilicon layer is not overlapped with the n + layer.
Step S404: and forming an antireflection film layer on the surface receiving the illumination.
Step S405: and forming a passivation film layer on the surfaces of the n + layer and the polycrystalline silicon layer, which are far away from the silicon wafer.
Step S406: and performing film opening treatment on the film layer positioned on the first surface to form a gap.
Step S407: forming an electrode in the gap.
In this embodiment, the surface of the silicon wafer receiving the illumination is subjected to texturing treatment, so that the number of light absorbed by the silicon wafer is increased, and the photoelectric conversion efficiency of the IBC cell is improved.
The IBC cell fabrication method of the present application is further described in a specific case below.
The first step is as follows: texturing the surface of the silicon wafer which is irradiated by light; polishing the first surface, wherein the first surface is opposite to the surface of the silicon chip, which receives the illumination;
the second step is that: forming oxide layers on all surfaces of the silicon wafer by a chemical method;
the third step: printing phosphorus slurry in a local area of the first surface of the silicon wafer and forming an n + layer by adopting a high-temperature propulsion mode;
the fourth step: depositing an undoped polysilicon layer and a P-type polysilicon layer on the first surface of the silicon wafer in sequence by adopting a plasma enhanced chemical vapor deposition method;
the fifth step: removing the undoped polysilicon layer and the P-type polysilicon layer in the corresponding regions of the phosphorosilicate glass and the n + layer by using hydrofluoric acid;
and a sixth step: forming a silicon nitride anti-reflection film on the surface of the silicon wafer receiving illumination by adopting a plasma enhanced chemical vapor deposition method;
the seventh step: sequentially forming an alumina film layer and a silicon nitride film layer on the first surface of the silicon wafer by adopting a plasma enhanced chemical vapor deposition method;
eighth step: performing film opening treatment on the film layer on the first surface of the silicon wafer to form a gap by adopting a laser film opening mode, removing the oxide layer in the region corresponding to the p + layer without removing the oxide layer in the region corresponding to the n + layer;
the ninth step: electroplating metal nickel in the gap;
the tenth step: and (4) adopting a low-temperature annealing process for treatment, and screening out qualified IBC batteries through testing.
The application also provides an IBC battery, which comprises the IBC battery manufactured in any one of the manufacturing method embodiments of the IBC battery.
Specifically, the polysilicon layer of the IBC cell in this embodiment is an undoped polysilicon layer and a P-type polysilicon layer.
Optionally, on the basis of the above embodiment, in an embodiment of the present application, the value ranges of the thicknesses of the undoped polysilicon layer and the P-type polysilicon layer in the polysilicon layers are both 10nm to 20nm, including end values, which prevents the thicknesses of the undoped polysilicon layer and the P-type polysilicon layer from being too small, so that the photoelectric conversion efficiency is improved to be limited, and simultaneously prevents the thicknesses of the undoped polysilicon layer and the P-type polysilicon layer from being too large, so that the required process time is prolonged, the efficiency is low, and materials are wasted and the cost is increased.
The IBC battery provided by the embodiment of the application comprises an n + layer formed in a local area of a first surface of a silicon wafer in a high-temperature propelling mode, wherein the first surface is opposite to the surface of the silicon wafer, which receives light irradiation; forming a polysilicon layer on the first surface, wherein the polysilicon layer is not overlapped with the n + layer; performing film opening treatment on the film layer positioned on the first surface to form a gap; forming an electrode in the gap. In the IBC battery, the polycrystalline silicon layer replaces the printing of boron slurry to form a p + layer, and not only can be used as the p + layer, but also can be used as an emitting layer, so that the transmission of photon-generated carriers is increased, and the performance of the IBC battery is improved.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The IBC cell and the method for manufacturing the IBC cell provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
Claims (5)
1. An IBC battery manufacturing method is characterized by comprising the following steps:
forming an n + layer in a local area of a first surface of a silicon wafer in a high-temperature propelling mode, wherein the first surface is opposite to the surface of the silicon wafer, which receives light irradiation;
forming a polysilicon layer on the first surface, wherein the polysilicon layer is not overlapped with the n + layer; wherein the thickness of the polysilicon layer ranges from 10nm to 20nm, inclusive;
performing film opening treatment on the film layer positioned on the first surface to form a gap;
forming an electrode in the slit;
wherein, before the n + layer is formed on the first surface local area of the silicon wafer, the method further comprises the following steps:
forming an oxide layer on the whole surface of the silicon wafer;
the film opening treatment of the film layer on the first surface comprises the following steps:
and carrying out laser film opening treatment on the film layer positioned on the first surface, wherein the laser energy when carrying out film opening treatment on the region corresponding to the n + layer is less than that when carrying out film opening treatment on the region corresponding to the p + layer.
2. The method of fabricating an IBC cell according to claim 1, wherein the high temperature drive conditions are:
under the nitrogen atmosphere, the temperature ranges from 700 ℃ to 850 ℃, and the time ranges from 20min to 60min, including all endpoints.
3. The method of fabricating an IBC cell according to claim 2, wherein the forming a polysilicon layer on the first surface comprises:
and forming an undoped polysilicon layer and a P-type polysilicon layer on the first surface.
4. The method for manufacturing the IBC cell according to claim 1, wherein an n + layer is formed on the first surface of the silicon wafer in a high temperature driving manner, and wherein the first surface is opposite to the surface of the silicon wafer receiving light, and further comprising:
performing texturing treatment on the surface receiving illumination;
and carrying out polishing treatment on the first surface.
5. An IBC cell, comprising the IBC cell fabricated by the IBC cell fabrication method according to any one of claims 1 to 4; wherein the thickness of the polysilicon layer ranges from 10nm to 20nm, inclusive.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157717A (en) * | 2014-08-26 | 2014-11-19 | 中国电子科技集团公司第四十八研究所 | Preparation method of all-back electrode N-type crystalline silicon heterojunction solar cells |
| CN105428453A (en) * | 2014-09-18 | 2016-03-23 | 上海神舟新能源发展有限公司 | Preparation method of inter-digital back contact battery |
| CN106653887A (en) * | 2016-12-30 | 2017-05-10 | 中国科学院微电子研究所 | Back-junction back-contact solar cell |
| CN108336154A (en) * | 2018-02-02 | 2018-07-27 | 中国科学院微电子研究所 | Crystalline silicon solar cell and preparation method thereof |
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| CN104157717A (en) * | 2014-08-26 | 2014-11-19 | 中国电子科技集团公司第四十八研究所 | Preparation method of all-back electrode N-type crystalline silicon heterojunction solar cells |
| CN105428453A (en) * | 2014-09-18 | 2016-03-23 | 上海神舟新能源发展有限公司 | Preparation method of inter-digital back contact battery |
| CN106653887A (en) * | 2016-12-30 | 2017-05-10 | 中国科学院微电子研究所 | Back-junction back-contact solar cell |
| CN108336154A (en) * | 2018-02-02 | 2018-07-27 | 中国科学院微电子研究所 | Crystalline silicon solar cell and preparation method thereof |
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