CN109656846A - Electric terminal and memory can use delay parameter section optimization method and device - Google Patents
Electric terminal and memory can use delay parameter section optimization method and device Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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Abstract
The present invention provides a kind of storage medium, electric terminal and memories can use delay parameter section optimization device and method, is related to field of data storage.Determine available delay parameter section to be confirmed from delay parameter range to be regulated according to initial sweep point first, initial sweep point is that DDR controller reads and writes the delay parameter being configured when scanning successfully for the first time；Then dichotomy interative computation is carried out according to available delay parameter section to be confirmed, until determining the first limiting figure point and the second limiting figure point in available delay parameter section to be confirmed, the first limiting figure point is that start numbers, the second limiting figure point when read-write scan successfully for the last time in dichotomy interative computation is that the last one in dichotomy interative computation reads and writes end value when scanning successfully；The section for finally constructing the first limiting figure point and the second limiting figure point can use delay parameter section as memory, expend that the time is short, efficiency is very high, and the memory generated can use delay parameter section reliability height.
Description
Technical field
The present invention relates to field of data storage, available in particular to a kind of storage medium, electric terminal and memory
Delay parameter section optimization device and method.
Background technique
Double dynamic random access memory (Double Data Rat, DDR) is common Installed System Memory.For DDR
The read-write of internal storage data is needed using DDR controller realization, and DDR controller carries out the read-write of internal storage data by pulse signal,
Specifically, when pulse signal is high level, internal storage data is written and read, however the model of different DDR controllers and institute
The temperature environment at place so that the level signal, which is one, slowly rises to peak value, and maintain peak value for a period of time after again slowly under
Drop to low level signal.Normally, DDR controller can be during pulse signal slowly rise, i.e., to DDR data
It is acquired, it may not be possible to which accurate stable collects internal storage data, therefore, in order to enable DDR controller is believed in pulse just
Number high level when, to the successful scan of the internal storage data of DDR, therefore, it is necessary to configure suitable delay parameter to control to DDR
Device, to ensure that the program of electronic equipment can operate normally.
In traditional technology, need to traverse all delays from the delay parameter range presetting for a certain DDR type number
The mode of parameter selects a delay parameter to carry out DDR data and sweeps to find out available delay section in available delay section
It retouches, and confirmation can be used when being delayed section, it is necessary to all DDR memory sizes are scanned through, to ensure that every Bit can stablize
Normal read-write, consuming time is long.
Summary of the invention
In view of this, the embodiment of the present invention to be designed to provide a kind of storage medium, electric terminal and memory available
Delay parameter section optimization device and method, to improve above-mentioned problem.
In a first aspect, the embodiment of the invention provides one kind can use delay parameter section optimization method, the delay
Parameter section optimization method includes:
Available delay parameter section to be confirmed is determined from delay parameter range to be regulated according to initial sweep point, described
Beginning scanning element is that DDR controller reads and writes the delay parameter being configured when scanning successfully for the first time；
Dichotomy interative computation is carried out according to the available delay parameter section to be confirmed, until described to be confirmed available
The first limiting figure point and the second limiting figure point are determined in delay parameter section, wherein the first limiting figure point is institute
State start numbers when read-write scans successfully for the last time in dichotomy interative computation, the second limiting figure point is described two
End value when the last one read-write scans successfully in point-score interative computation；
Delay can be used using the section of the first limiting figure point and the second limiting figure point construction as memory
Parameter section.
Second aspect can use delay parameter section optimization device the embodiment of the invention also provides one kind, it is described can be with prolonging
When parameter section optimization device include:
Interval determination unit, for determining that be confirmed can be used is prolonged from delay parameter range to be regulated according to initial sweep point
When parameter section, the initial sweep point be DDR controller read and write the delay parameter being configured when scanning successfully for the first time；
Interative computation unit, for carrying out dichotomy interative computation according to the available delay parameter section to be confirmed, directly
To first limiting figure point determining in the available delay parameter section to be confirmed and the second limiting figure point, wherein described
First limiting figure point is start numbers of the read-write for the last time when scanning successfully, described second in the dichotomy interative computation
Limiting figure point is end value when the last one read-write scans successfully in the dichotomy interative computation；
Target interval structural unit, the area for constructing the first limiting figure point and the second limiting figure point
Between can use delay parameter section as memory.
The third aspect, the embodiment of the invention also provides a kind of electric terminal, the electric terminal includes DDR, DDR control
Device, BootRam, processor and delay parameter section optimization device can be used；The DDR controller respectively with the BootRam, institute
DDR and BootRam electrical connection is stated,
The software function that described device is installed in the BootRam and is executed including one or more by the processor
Unit, it is described to include: with delay parameter section optimization device
Interval determination unit, for determining that be confirmed can be used is prolonged from delay parameter range to be regulated according to initial sweep point
When parameter section, the initial sweep point be DDR controller read and write the delay parameter being configured when scanning successfully for the first time；
Interative computation unit, for carrying out dichotomy interative computation according to the available delay parameter section to be confirmed, directly
To first limiting figure point determining in the available delay parameter section to be confirmed and the second limiting figure point, wherein described
First limiting figure point is start numbers of the read-write for the last time when scanning successfully, described second in the dichotomy interative computation
Limiting figure point is end value when the last one read-write scans successfully in the dichotomy interative computation；
Target interval structural unit, the area for constructing the first limiting figure point and the second limiting figure point
Between can use delay parameter section as memory.
Fourth aspect, the embodiment of the invention also provides a kind of storage medium, the storage medium is stored with computer and refers to
It enables, wherein the computer instruction executes available delay parameter section optimization method as described above when being read and running.
Compared with prior art, storage medium provided by the invention, electric terminal and memory can use delay parameter section
Optimization device and method determine available delay parameter to be confirmed according to initial sweep point from delay parameter range to be regulated first
Section, initial sweep point are that DDR controller reads and writes the delay parameter being configured when scanning successfully for the first time；Then according to be confirmed
Dichotomy interative computation can be carried out with delay parameter section, until determining first limit in available delay parameter section to be confirmed
Numerical point and the second limiting figure point, wherein the first limiting figure point is read-write scanning for the last time in dichotomy interative computation
Start numbers, the second limiting figure point when success are end when the last one read-write scans successfully in dichotomy interative computation
Numerical value；The section that the first limiting figure point and the second limiting figure point construct finally can be used into delay parameter area as memory
Between, expend that the time is short, efficiency is very high, and the memory generated can be high with delay parameter section reliability.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.The present invention being usually described and illustrated herein in the accompanying drawings is implemented
The component of example can be arranged and be designed with a variety of different configurations.Therefore, below to the reality of the invention provided in the accompanying drawings
The detailed description for applying example is not intended to limit the range of claimed invention, but is merely representative of selected implementation of the invention
Example.Based on the embodiments of the present invention, obtained by those of ordinary skill in the art without making creative efforts
Every other embodiment, shall fall within the protection scope of the present invention.
Fig. 1 is the flow chart that memory provided in an embodiment of the present invention can use delay parameter section optimization method；
Fig. 2 is the hardware environment figure that memory provided in an embodiment of the present invention can use delay parameter section optimization method；
Fig. 3 is the specific steps flow chart of the step S103 in Fig. 1；
Fig. 4 is that memory can use the functional block diagram of delay parameter section optimization device in the embodiment of the present invention.
Icon: 101- processor；102-DDR controller；103-DDR；104-BootRam；105- electric terminal；The area 301-
Between determination unit；302- interative computation unit；303- target interval structural unit.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
Referring to Fig. 1, the embodiment of the invention provides a kind of memories can use delay parameter section optimization method, it is applied to
The processor 101 of electric terminal.As shown in Fig. 2, the electric terminal further includes DDR103, DDR controller 102, BootRam, place
Reason device 101 is electrically connected with DDR controller 102, DDR103 and BootRam respectively.In the present embodiment, DDR103, DDR controller
102, BootRam, processor 101 can integrate in a chip platform daughter board.It should be noted that in the present embodiment, delay ginseng
There are many number includes, for example, a variety of delay parameters include DQS delay parameter, PHY_DQS delay parameter, CLK delay parameter.Institute
Stating memory can include: with delay parameter section optimization method
Step S101: in turn by the corresponding preliminary delay parameter section of one of delay parameter in a variety of delay parameters
As delay parameter range to be regulated, and the corresponding preset preliminary available delay section of remaining parameter type is constant.
It should be noted that the influence due to three kinds of delay parameters for data stability is different in the present embodiment, thus
It needs to be determined that the memory of three kinds of delay parameters can use the delay determined sequencing in section, more accurately to obtain three
The memory of kind delay parameter can use delay section.Normally, PHY_DQS and DQS delay parameter is to data sampling
Same clock, only the sampling clock of DQS delay is the two divided-frequency of the sampling clock of PHY_DQS delay；And DQS and CLK is delayed
The use of clock source is not all asynchronous-sampling, data again phase transition easily occur it is unstable, so will be first by CLK delay parameter pair
The preliminary available delay section answered determines that PHY_DQS and DQS delay parameter is scanned as delay parameter range to be regulated,
DQS, PHY_DQS delay parameter are successively determined afterwards, are so recycled.
Step S102: available delay parameter area to be confirmed is determined from delay parameter range to be regulated according to initial sweep point
Between, initial sweep point is the delay parameter being configured when the first read-write of DDR controller 102 scans successfully.
Set the mode of initial sweep point are as follows: one or more, which has been generated memory, in real time can use delay parameter section
Median be updated to the initial sweep point of the parameter type, until the memory of each parameter type can use delay parameter section
Start numbers, end value fluctuation in presetting threshold range.Since preliminary delay parameter section belongs to ratio of precision
Lower and wide in range delay parameter section, and the memory generated every time can be with delay section relative to preliminary delay parameter section
Precision is higher, and therefore, one of which or two kinds, which have been generated memory, can use the corresponding storage of delay parameter in delay section
Device can use delay interval midpoint as scanning constant parameter, and can be corresponding with the delay parameter in delay section to memory is not generated
Preliminary delay parameter section reduced, also obtain a new target delay parameter section.It then proceedes to two of them
Memory can be updated to the initial sweep point of corresponding parameter type with the midrange in delay section, and deposit to another parameter
Reservoir, which can be carried out continuing to zoom out with delay section, to be obtained the new memory of corresponding one kind of the parameter type and can use the area that is delayed
Between.Above-mentioned operation is carried out to the several classes of every seed ginseng in turn, until the memory of each parameter type can use delay parameter section
Start numbers, end value fluctuation in presetting threshold range.
In the present embodiment, initial sweep point is preferably but not limited to as the midpoint of delay parameter range to be regulated, determining starting
Whether scanning element scans successful mode can be with are as follows: the DDR controller at midpoint of the control configured with delay parameter range to be regulated
102 customized self-inspection data will be written in DDR103 in advance, and record storage address；DDR controller 102 is controlled according to storage
Address reads self-inspection data；Reading self-inspection data with customized self-inspection data is consistent in advance when, by it is presetting to
The midpoint for adjusting delay parameter range is set as initial sweep point.
Wherein, to the mode of self-inspection data read-write scanning are as follows: control DDR controller 102 will preparatory customized self-checking number
According in write-in DDR103, and record storage address；Control DDR controller 102 reads self-inspection data according to storage address；It is reading
Self-inspection data out determines that read-write scans successfully with when customized self-inspection data is consistent in advance.In the present embodiment, self-inspection data
It can be the experience self-inspection data of setting, for example, can respectively " 0x00000000 ", " 0xffffffff ",
" 0xffff0000 ", " 0xa5a5a5a5 ", " 0x5a5a5a5a " can distinguish to guarantee that read-write scans successful reliability
Five last self-inspection datas are written and read scanning respectively.
In the present embodiment, determine that available delay parameter interval mode to be confirmed is but is not limited to: by delay parameter to be regulated
The midpoint of range is divided into two the first data intervals as separation, by delay time adjustable range.For example, delay time tune
The data of adjusting range are (1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19), then initial sweep point
Be 10, two the first data intervals be respectively (1,2,3,4,5,6,7,8,9,10), (11,12,13,14,15,16,17,18,
19).Take the midpoint of two the first data intervals as the starting point and end point in available delay parameter section to be confirmed respectively, i.e.,
Available delay parameter section to be confirmed is (5,15).
Step S103: carrying out dichotomy interative computation according to available delay parameter section to be confirmed, until it is to be confirmed can
With the first limiting figure point determining in delay parameter section and the second limiting figure point.
Wherein, the first limiting figure point is starting number when read-write scans successfully for the last time in dichotomy interative computation
Value, the second limiting figure point are end value when the last one read-write scans successfully in dichotomy interative computation.
Specifically, as shown in figure 3, the specific implementation of step S103 can be with are as follows:
Step 1031: available delay parameter area to be confirmed is determined from delay parameter range to be regulated according to initial sweep point
Between, initial sweep point is the delay parameter being configured when the first read-write of DDR controller 102 scans successfully.
Step 1032: respectively that the first delay point to be confirmed and the second delay point configuration to be confirmed is right to DDR controller 102
Presetting self-inspection data is written and read scanning.
Wherein, the first delay point to be confirmed is that the start numbers in available delay parameter section to be confirmed and second to be confirmed prolong
Time point is the end value in available delay parameter section to be confirmed.Specifically, read-write scanning mode is same as described above, herein not
It is again to repeat more.
Step 1033: according to read-write scanning as a result, the first division direction of confirmation and the second division direction.
Wherein, the first division direction of confirmation include: when the first delay point to be confirmed is corresponding read and write scan successfully when, acquisition
One updated first delay point to be confirmed；Updated first delay point to be confirmed is the first delay to be confirmed before update
Point is far from point (the first delay point to be confirmed and delay parameter range to be regulated before for example, updating on the direction of start numbers
Start numbers between midpoint)；When the corresponding read-write scanning failure of the first delay point to be confirmed, the first division direction packet
It includes: obtaining a updated first delay point to be confirmed；It is updated first it is to be confirmed delay point for update before first to
Point (first to be confirmed delay point and initial sweep point for example, update before of the confirmation delay point on the direction of start numbers
Between midpoint).
Confirm that the second division direction includes: the acquisition one when the corresponding read-write of the second delay point to be confirmed scan successfully
Updated second delay point to be confirmed；Updated second delay point to be confirmed leans on for the second delay point to be confirmed before updating
Point (knot of the second delay point to be confirmed with delay parameter range to be regulated before for example, updating on the direction of nearly end value
Midpoint between beam numerical value)；When the corresponding read-write scanning failure of the first delay point to be confirmed, the first division direction includes: to obtain
Obtain a updated second delay point to be confirmed；Updated second delay point to be confirmed prolongs for second before update is to be confirmed
Time point is far from the point on the direction of end value (between the second delay point and initial sweep point to be confirmed before for example, updating
Midpoint)；Take the first division direction as the iteration direction of the first delay point to be confirmed, is second to be confirmed to prolong with the second division direction
The iteration direction of time point.
Step 1034: by the updated first delay point to be confirmed as start numbers, to be confirmed by updated second
Delay point is used as end value, repeats that the first delay point to be confirmed and the second delay point to be confirmed are configured to DDR and controlled respectively
Device 102 is written and read scanning to presetting self-inspection data, until obtaining the first limiting figure point and the second limiting figure point；Its
In, the first limiting figure point is the last one successful start numbers of scanning, the second limiting figure point is that the last one is scanned into
The end value of function.
Step S104: the section that the first limiting figure point and the second limiting figure point are constructed can use delay as memory
Parameter section.
Step S105: can be in delay parameter section by the corresponding memory of multiple parameters type, logical order is corresponding
Delay parameter constructs a delay and runs array, to generate multiple delay operation arrays.
For example, when DQS delay parameter, PHY_DQS delay parameter, the corresponding memory of CLK delay parameter can use delay ginseng
Number interval is respectively (2,3,4), (2,3,4), (3,4,5), then multiple delays operation arrays respectively (2,2,3), (3,3,4),
(4,4,5).
Step S106: when DDR controller 102 runs array configured with different delays, operation, which prestores, is stored in outside
Power-up routine in Flash.
Delay operation array (2,2,3), (3,3,4), (4,4,5) are configured to DDR respectively for example, putting in different times
Controller 102.Wherein it is determined that power-up routine runs successful condition are as follows: the outer contact relay record received actually powers on
Number is consistent with the number of starts that processor 101 records and does not receive the notice of power-up routine operation collapse.
Step S107: the delay that DDR controller 102 configures when power-up routine is run successfully runs array, as preferred
Delay operation array.
For example, when in the configuration delay operation of DDR controller 102 array (2,2,3), (3,3,4), (4,4,5), only (2,
2,3), (3,3,4) can operate normally the power-up routine in external Flash, then be delayed and run array (2,2,3), (3,3,4) are
It is preferred that delay operation array.
Step S108: when DDR controller 102 runs array configured with different preferred delays, in different temperature rings
Control prestores the power-up routine operation being stored in BootRoom104 under border.
Step S109: by under all temperature environments, DDR controller 102 is configured preferred when power-up routine is run successfully
Delay operation array, runs array as optimal delay.
It is influenced in view of environment temperature has the operation of power-up routine, therefore can be in three kinds of high temperature, room temperature, low temperature temperature
Power-up routine is run under degree environment.(2,2,3), (3,3,4) are run in array for example, it is preferable to be delayed, and only DDR103 control is matched
When power-up routine can be operated normally under all temperature environments by setting preferred delay operation array (3,3,4), then (3,3,4) are optimal
Delay operation array, and the memory that the memory of DQS delay parameter can only have 3, PHY_DQS delay parameter with delay section can
Can only have 4 with delay section with the memory that delay section only has 4, CLK delay parameter.
Referring to Fig. 4, the embodiment of the invention also provides a kind of memories can use delay parameter section optimization device, need
Illustrate, memory provided by the present embodiment can use the skill of delay parameter section optimization device, basic principle and generation
Art effect is identical with above-described embodiment, and to briefly describe, the present embodiment part does not refer to place, can refer in the above embodiments
Corresponding contents.The available delay parameter section optimization device includes interval determination unit 301, interative computation unit 302 and mesh
Mark interval structure unit 303.
Interval determination unit 301 is used to be determined from delay parameter range to be regulated according to initial sweep point to be confirmed available
Delay parameter section, initial sweep point are the delay parameter being configured when the first read-write of DDR controller 102 scans successfully.
Interative computation unit 302 is used to carry out dichotomy interative computation according to available delay parameter section to be confirmed, until
The first limiting figure point and the second limiting figure point are determined in available delay parameter section to be confirmed, wherein the first limit number
Value point is that start numbers, the second limiting figure point when read-write scans successfully for the last time in dichotomy interative computation are dichotomy
End value when the last one read-write scans successfully in interative computation.
Target interval structural unit 303 be used for using the first limiting figure point and the second limiting figure point construction section as
Memory can be with delay parameter section according to initial sweep point, determining to be confirmed can be used is prolonged from delay parameter range to be regulated
When parameter section, initial sweep point is the delay parameter that is configured of read-write when scanning successfully for the first time of DDR controller 102.
Interative computation unit 302 is used to carry out dichotomy interative computation according to available delay parameter section to be confirmed, until
The first limiting figure point and the second limiting figure point are determined in available delay parameter section to be confirmed, wherein the first limit number
Value point is that start numbers, the second limiting figure point when read-write scans successfully for the last time in dichotomy interative computation are dichotomy
End value when the last one read-write scans successfully in interative computation.
Target interval structural unit 303 be used for using the first limiting figure point and the second limiting figure point construction section as
Memory can use delay parameter section.
Referring to Fig. 2, electric terminal includes DDR103, DDR controller the embodiment of the invention provides a kind of electric terminal
102, BootRam, processor 101 and memory can use delay parameter section optimization device；DDR controller 102 respectively with
BootRam, DDR103 and BootRam electrical connection, DDR103, DDR controller 102, BootRam, processor 101 can integrate
In a chip platform daughter board.The software function that device is installed in BootRam and is executed including one or more by processor 101
Unit, the available delay parameter section optimization device include:
Interval determination unit 301 is used to be determined from delay parameter range to be regulated according to initial sweep point to be confirmed available
Delay parameter section, initial sweep point are the delay parameter being configured when the first read-write of DDR controller 102 scans successfully.
It is to be appreciated that interval determination unit 301 can execute above-mentioned step S101.
Interative computation unit 302 is used to carry out dichotomy interative computation according to available delay parameter section to be confirmed, until
The first limiting figure point and the second limiting figure point are determined in available delay parameter section to be confirmed.
It is to be appreciated that interative computation unit 302 can execute above-mentioned step S102.
Wherein, the first limiting figure point is starting number when read-write scans successfully for the last time in dichotomy interative computation
Value, the second limiting figure point are end value when the last one read-write scans successfully in dichotomy interative computation.
Target interval structural unit 303 be used for using the first limiting figure point and the second limiting figure point construction section as
Memory can use delay parameter section.
It is to be appreciated that target interval structural unit 303 can execute above-mentioned step S103.
The embodiment of the invention also provides a kind of storage medium, storage medium is stored with computer instruction, wherein computer
Instruct the memory executed as described in above-described embodiment when being read and running that can use delay parameter section optimization method.
In conclusion storage medium provided in an embodiment of the present invention, electric terminal and memory can use delay parameter section
Optimization device and method determine available delay parameter to be confirmed according to initial sweep point from delay parameter range to be regulated first
Section, the initial sweep point are that DDR controller reads and writes the delay parameter being configured when scanning successfully for the first time；Then according to institute
It states available delay parameter section to be confirmed and carries out dichotomy interative computation, until in the available delay parameter section to be confirmed
Determine the first limiting figure point and the second limiting figure point, wherein the first limiting figure point is dichotomy iteration fortune
Start numbers, the second limiting figure point when read-write scans successfully for the last time in calculation are in the dichotomy interative computation
End value when the last one read-write scans successfully；Finally by the first limiting figure point and the second limiting figure point
The section of construction can use delay parameter section as memory, expend that the time is short, efficiency is very high, and the memory generated can
It is high with delay parameter section reliability.
In several embodiments provided herein, it should be understood that disclosed device and method can also pass through
Other modes are realized.The apparatus embodiments described above are merely exemplary, for example, flow chart and block diagram in attached drawing
Show the device of multiple embodiments according to the present invention, the architectural framework in the cards of method and computer program product,
Function and operation.In this regard, each box in flowchart or block diagram can represent the one of a module, section or code
Part, a part of the module, section or code, which includes that one or more is for implementing the specified logical function, to be held
Row instruction.It should also be noted that function marked in the box can also be to be different from some implementations as replacement
The sequence marked in attached drawing occurs.For example, two continuous boxes can actually be basically executed in parallel, they are sometimes
It can execute in the opposite order, this depends on the function involved.It is also noted that every in block diagram and or flow chart
The combination of box in a box and block diagram and or flow chart can use the dedicated base for executing defined function or movement
It realizes, or can realize using a combination of dedicated hardware and computer instructions in the system of hardware.
In addition, each functional module in each embodiment of the present invention can integrate one independent portion of formation together
Point, it is also possible to modules individualism, an independent part can also be integrated to form with two or more modules.
It, can be with if the function is realized and when sold or used as an independent product in the form of software function module
It is stored in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially in other words
The part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, server or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
And storage medium above-mentioned includes: that USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
The various media that can store program code such as reservoir (RAM, Random Access Memory), magnetic or disk.It needs
Illustrate, herein, relational terms such as first and second and the like be used merely to by an entity or operation with
Another entity or operation distinguish, and without necessarily requiring or implying between these entities or operation, there are any this realities
The relationship or sequence on border.Moreover, the terms "include", "comprise" or its any other variant are intended to the packet of nonexcludability
Contain, so that the process, method, article or equipment for including a series of elements not only includes those elements, but also including
Other elements that are not explicitly listed, or further include for elements inherent to such a process, method, article, or device.
In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including the element
Process, method, article or equipment in there is also other identical elements.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.It should also be noted that similar label and letter exist
Similar terms are indicated in following attached drawing, therefore, once being defined in a certain Xiang Yi attached drawing, are then not required in subsequent attached drawing
It is further defined and explained.
Claims (10)
1. a kind of memory can use delay parameter section optimization method, which is characterized in that the memory can use delay parameter area
Between optimization method include:
Available delay parameter section to be confirmed is determined from delay parameter range to be regulated according to initial sweep point, the starting is swept
Described point is that DDR controller reads and writes the delay parameter being configured when scanning successfully for the first time；
Dichotomy interative computation is carried out according to the available delay parameter section to be confirmed, until in the available delay to be confirmed
The first limiting figure point and the second limiting figure point are determined in parameter section, wherein the first limiting figure point is described two
Start numbers, the second limiting figure point when read-write scans successfully for the last time in point-score interative computation are the dichotomy
End value when the last one read-write scans successfully in interative computation；
The section of the first limiting figure point and the second limiting figure point construction can be used into delay parameter as memory
Section.
2. memory according to claim 1 can use delay parameter section optimization method, which is characterized in that described according to institute
It states available delay parameter section to be confirmed and carries out dichotomy interative computation, until in the available delay parameter section to be confirmed
Determine the first limiting figure point and the second limiting figure point, comprising:
Available delay parameter section to be confirmed is determined from delay parameter range to be regulated according to initial sweep point, the starting is swept
Described point is that DDR controller reads and writes the delay parameter being configured when scanning successfully for the first time；
The first delay point to be confirmed and the second delay point to be confirmed are configured to the DDR controller to presetting self-test respectively
Data are written and read scanning；Wherein, the first delay point to be confirmed is the start numbers and the in available delay parameter section to be confirmed
2 delay points to be confirmed are the end value in available delay parameter section to be confirmed；
According to the read-write scanning as a result, the first division direction of confirmation and the second division direction；
Wherein, the first division direction of the confirmation includes:
When the corresponding read-write of the described first delay point to be confirmed scan successfully, one updated first delay to be confirmed of acquisition
Point；The updated first delay point to be confirmed is side of the delay point to be confirmed of first before update far from the start numbers
Upward point；
When the corresponding read-write scanning failure of the described first delay point to be confirmed, first division direction includes: to obtain one
Updated first delay point to be confirmed；The updated first delay point to be confirmed is the first delay to be confirmed before update
Point of the point on the direction of the start numbers；
The second division direction of the confirmation includes:
When the corresponding read-write of the described second delay point to be confirmed scan successfully, one updated second delay to be confirmed of acquisition
Point；The updated second delay point to be confirmed is the delay point to be confirmed of second before update close to the side of the end value
Upward point；
When the corresponding read-write scanning failure of the described first delay point to be confirmed, first division direction includes: to obtain one
Updated second delay point to be confirmed；The updated second delay point to be confirmed is the second delay to be confirmed before update
Point is far from the point on the direction of the end value；
It take first division direction as the iteration direction of the described first delay point to be confirmed, using second division direction as institute
State the iteration direction of the second delay point to be confirmed；
By the updated first delay point to be confirmed as the start numbers, by the updated second delay point conduct to be confirmed
The end value repeats described respectively by the first delay point to be confirmed and the second delay point configuration to be confirmed to DDR control
Device processed is written and read scanning to presetting self-inspection data, until obtaining the first limiting figure point and the second limiting figure point；Its
In, the first limiting figure point is the last one successful start numbers of scanning, the second limiting figure point is last
A successful end value of scanning.
3. memory according to claim 1 can use delay parameter section optimization method, which is characterized in that the delay ginseng
Number determines available delay parameter to be confirmed according to initial sweep point described there are many including from delay parameter range to be regulated
It is described to use delay parameter section optimization method before the step of section further include:
Prolong in turn using the corresponding preliminary delay parameter section of one of delay parameter in a variety of delay parameters as to be regulated
When parameter area, and the corresponding preset preliminary available delay section of remaining parameter type is constant；
Set the mode of the initial sweep point are as follows: one or more, which has been generated memory, in real time can use delay parameter section
Median be updated to the initial sweep point of the parameter type, until the memory of each parameter type can use delay parameter
The start numbers in section, end value fluctuation in presetting threshold range.
4. memory according to claim 3 can use delay parameter section optimization method, which is characterized in that the memory
The step of delay parameter section optimization method can be used further include:
Can be in delay parameter section by the corresponding memory of multiple parameters type, the corresponding delay parameter of logical order constructs one
A delay runs array, to generate multiple delay operation arrays；
When DDR controller runs array configured with different delays, operation prestores the power-up routine being stored in external Flash；
The delay that DDR controller configures when power-up routine is run successfully runs array, as preferred delay operation array.
5. memory according to claim 4 can use delay parameter section optimization method, which is characterized in that it is described can be with prolonging
When parameter section optimization method the step of further include:
When DDR controller runs array configured with different preferred delays, control, which prestores, under different temperature environments is stored in
Power-up routine operation in BootRoom；
The preferred delay that under all temperature environments, DDR controller is configured when power-up routine is run successfully is run into array, as
Optimal delay runs array.
6. memory according to claim 5 can use delay parameter section optimization method, which is characterized in that determine on described
Electric program runs successful condition are as follows: the starting for actually powering on number and processor record of the outer contact relay record received
Number is consistent and does not receive the notice of power-up routine operation collapse.
7. memory according to claim 1 can use delay parameter section optimization method, which is characterized in that described to self-test
The mode of reading and writing data scanning are as follows:
Control the DDR controller customized self-inspection data will be written in DDR in advance, and record storage address；
It controls the DDR controller and reads the self-inspection data according to the storage address；
Reading self-inspection data with customized self-inspection data is consistent in advance when, determine that read-write scans successfully.
8. a kind of memory can use delay parameter section optimization device, which is characterized in that described to use the optimizing of delay parameter section
Device includes:
Interval determination unit, for determining that available delay to be confirmed is joined from delay parameter range to be regulated according to initial sweep point
Number interval, the initial sweep point are that DDR controller reads and writes the delay parameter being configured when scanning successfully for the first time；
Interative computation unit, for carrying out dichotomy interative computation, Zhi Dao according to the available delay parameter section to be confirmed
The first limiting figure point and the second limiting figure point are determined in the available delay parameter section to be confirmed, wherein described first
Limiting figure point is start numbers when read-write scans successfully for the last time in the dichotomy interative computation, second limit
Numerical point is end value when the last one read-write scans successfully in the dichotomy interative computation；
Target interval structural unit, for making the section of the first limiting figure point and the second limiting figure point construction
It can be to be confirmed available in being determined from delay parameter range to be regulated according to initial sweep point with delay parameter section for memory
Delay parameter section, the initial sweep point are that DDR controller reads and writes the delay parameter being configured when scanning successfully for the first time；
Interative computation unit, for carrying out dichotomy interative computation, Zhi Dao according to the available delay parameter section to be confirmed
The first limiting figure point and the second limiting figure point are determined in the available delay parameter section to be confirmed, wherein described first
Limiting figure point is start numbers when read-write scans successfully for the last time in the dichotomy interative computation, second limit
Numerical point is end value when the last one read-write scans successfully in the dichotomy interative computation；
Target interval structural unit, for making the section of the first limiting figure point and the second limiting figure point construction
Delay parameter section can be used for memory.
9. a kind of electric terminal, which is characterized in that the electric terminal include DDR, DDR controller, BootRam, processor and
Memory can use delay parameter section optimization device；The DDR controller respectively with the BootRam, the DDR and described
BootRam electrical connection,
The software function list that described device is installed in the BootRam and is executed including one or more by the processor
Member, it is described to include: with delay parameter section optimization device
Interval determination unit, for determining that available delay to be confirmed is joined from delay parameter range to be regulated according to initial sweep point
Number interval, the initial sweep point are that DDR controller reads and writes the delay parameter being configured when scanning successfully for the first time；
Interative computation unit, for carrying out dichotomy interative computation, Zhi Dao according to the available delay parameter section to be confirmed
The first limiting figure point and the second limiting figure point are determined in the available delay parameter section to be confirmed, wherein described first
Limiting figure point is start numbers when read-write scans successfully for the last time in the dichotomy interative computation, second limit
Numerical point is end value when the last one read-write scans successfully in the dichotomy interative computation；
Target interval structural unit, for making the section of the first limiting figure point and the second limiting figure point construction
Delay parameter section can be used for memory.
10. a kind of storage medium, which is characterized in that the storage medium is stored with computer instruction, wherein the computer refers to
Enable the memory executed as described in claim any in claim 1-7 when being read and running that can use the optimizing of delay parameter section
Method.
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