CN109656846B - Method and device for optimizing available delay parameter interval of electronic terminal and memory - Google Patents
Method and device for optimizing available delay parameter interval of electronic terminal and memory Download PDFInfo
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- CN109656846B CN109656846B CN201811562689.1A CN201811562689A CN109656846B CN 109656846 B CN109656846 B CN 109656846B CN 201811562689 A CN201811562689 A CN 201811562689A CN 109656846 B CN109656846 B CN 109656846B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
Abstract
The invention provides a storage medium, an electronic terminal and a device and a method for optimizing an available delay parameter interval of a memory, and relates to the field of data storage. Firstly, determining an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, wherein the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller is successful; then, performing dichotomy iterative operation according to the available delay parameter interval to be confirmed until a first limit value point and a second limit value point are determined in the available delay parameter interval to be confirmed, wherein the first limit value point is a starting value when the last read-write scanning in the dichotomy iterative operation is successful, and the second limit value point is an ending value when the last read-write scanning in the dichotomy iterative operation is successful; and finally, the interval constructed by the first limit value point and the second limit value point is used as the available delay parameter interval of the memory, so that the consumed time is short, the efficiency is very high, and the generated available delay parameter interval of the memory has high reliability.
Description
Technical Field
The invention relates to the field of data storage, in particular to a storage medium, an electronic terminal and a device and a method for optimizing an available delay parameter interval of a memory.
Background
Double Data Rate (DDR), a common system memory, is provided. For the read-write of the DDR memory data, the DDR controller needs to be implemented by using a DDR controller, and the DDR controller performs the read-write of the memory data through a pulse signal, specifically, when the pulse signal is at a high level, the memory data is read-written, but the level signal is a signal that slowly rises to a peak value, and slowly falls to a low level after the peak value is maintained for a period of time due to different types and temperature environments of the DDR controller. Generally, the DDR controller may not accurately and stably acquire the memory data during the slow rising of the pulse signal, that is, the DDR controller acquires the DDR data, and therefore, in order to enable the DDR controller to successfully scan the memory data of the DDR just at the high level of the pulse signal, it is necessary to configure an appropriate delay parameter to the DDR controller to ensure that the program of the electronic device can normally run.
In the conventional technology, a mode of traversing all delay parameters from a delay parameter range preset for a certain DDR model is required to find out an available delay interval, select one delay parameter in the available delay interval to perform DDR data scanning, and when the available delay interval is confirmed, all DDR memory capacities must be scanned to ensure that each Bit of Bit can be stably and normally read and written, and the consumed time is long.
Disclosure of Invention
It is therefore an object of the present invention to provide a storage medium, an electronic terminal, and an apparatus and method for optimizing an available delay parameter interval of a memory, so as to improve the above-mentioned problems.
In a first aspect, an embodiment of the present invention provides an available delay parameter interval optimization method, where the available delay parameter interval optimization method includes:
determining an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, wherein the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller is successful;
performing bisection iteration operation according to the available delay parameter interval to be confirmed until a first limit value point and a second limit value point are determined in the available delay parameter interval to be confirmed, wherein the first limit value point is a starting value when the last read-write scanning in the bisection iteration operation is successful, and the second limit value point is an ending value when the last read-write scanning in the bisection iteration operation is successful;
and taking the interval constructed by the first limit value point and the second limit value point as an available delay parameter interval of a memory.
In a second aspect, an embodiment of the present invention further provides an apparatus for optimizing an available delay parameter interval, where the apparatus for optimizing an available delay parameter interval includes:
the interval determining unit is used for determining an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, wherein the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller is successful;
the iterative operation unit is used for performing bisection iterative operation according to the available delay parameter interval to be confirmed until a first limit value point and a second limit value point are determined in the available delay parameter interval to be confirmed, wherein the first limit value point is a starting value when the last read-write scanning in the bisection iterative operation is successful, and the second limit value point is an ending value when the last read-write scanning in the bisection iterative operation is successful;
and the target interval construction unit is used for taking the interval constructed by the first limit value points and the second limit value points as an available delay parameter interval of the memory.
In a third aspect, an embodiment of the present invention further provides an electronic terminal, where the electronic terminal includes a DDR controller, a BootRam, a processor, and an available delay parameter interval optimizing device; the DDR controller is electrically connected with the Bootram, the DDR and the Bootram respectively,
the apparatus is installed in the Bootram and comprises one or more software functional units executed by the processor, and the available delay parameter interval optimizing apparatus comprises:
the interval determining unit is used for determining an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, wherein the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller is successful;
the iterative operation unit is used for performing bisection iterative operation according to the available delay parameter interval to be confirmed until a first limit value point and a second limit value point are determined in the available delay parameter interval to be confirmed, wherein the first limit value point is a starting value when the last read-write scanning in the bisection iterative operation is successful, and the second limit value point is an ending value when the last read-write scanning in the bisection iterative operation is successful;
and the target interval construction unit is used for taking the interval constructed by the first limit value points and the second limit value points as an available delay parameter interval of the memory.
In a fourth aspect, an embodiment of the present invention further provides a storage medium, where the storage medium stores computer instructions, where the computer instructions, when read and executed, perform the method for optimizing an available delay parameter interval as described above.
Compared with the prior art, the device and the method for optimizing the available delay parameter interval of the storage medium, the electronic terminal and the memory, provided by the invention, have the advantages that firstly, the available delay parameter interval to be confirmed is determined from the delay parameter range to be adjusted according to the initial scanning point, and the initial scanning point is the configured delay parameter when the initial read-write scanning of the DDR controller is successful; then, performing dichotomy iterative operation according to the available delay parameter interval to be confirmed until a first limit value point and a second limit value point are determined in the available delay parameter interval to be confirmed, wherein the first limit value point is a starting value when the last read-write scanning in the dichotomy iterative operation is successful, and the second limit value point is an ending value when the last read-write scanning in the dichotomy iterative operation is successful; and finally, the interval constructed by the first limit value point and the second limit value point is used as the available delay parameter interval of the memory, so that the consumed time is short, the efficiency is very high, and the generated available delay parameter interval of the memory has high reliability.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
FIG. 1 is a flowchart illustrating a method for optimizing an available delay parameter interval of a memory according to an embodiment of the present invention;
FIG. 2 is a diagram of a hardware environment for a method for optimizing an available delay parameter interval of a memory according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating the detailed steps of step S103 in FIG. 1;
FIG. 4 is a functional block diagram of an apparatus for optimizing an available delay parameter interval of a memory according to an embodiment of the present invention.
Icon: 101-a processor; 102-DDR controller; 103-DDR; 104-Bootram; 105-an electronic terminal; 301-an interval determination unit; 302-an iterative operation unit; 303-target interval construction unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, an embodiment of the present invention provides a method for optimizing an available delay parameter interval of a memory, which is applied to a processor 101 of an electronic terminal. As shown in fig. 2, the electronic terminal further includes a DDR103, a DDR controller 102, and a BootRam, and the processor 101 is electrically connected to the DDR controller 102, the DDR103, and the BootRam, respectively. In this embodiment, the DDR103, the DDR controller 102, the BootRam, and the processor 101 may be integrated into a chip platform daughter board. It should be noted that, in this embodiment, the delay parameters include multiple types, for example, the multiple delay parameters include a DQS delay parameter, a PHY _ DQS delay parameter, and a CLK delay parameter. The method for optimizing the available delay parameter interval of the memory comprises the following steps:
step S101: and taking the preliminary delay parameter interval corresponding to one of the multiple delay parameters as the range of the delay parameter to be adjusted in turn, and keeping the corresponding preset preliminary available delay intervals of the other parameter types unchanged.
It should be noted that, in this embodiment, since the three delay parameters have different influences on the data stability, the order in which the available memory delay intervals of the three delay parameters are determined needs to be determined, so as to more accurately obtain the available memory delay intervals of the three delay parameters. Usually, the same clock is used for data sampling by the PHY _ DQS and DQS delay parameters, except that the DQS delayed sampling clock is a halving of the PHY _ DQS delayed sampling clock; the difference of the clock source used by the DQS and the CLK for the delay is asynchronous sampling, and the data is easy to be unstable in the second-stage conversion, so that a preliminary available delay interval corresponding to the CLK delay parameter is taken as a delay parameter range to be adjusted, the PHY _ DQS and the DQS delay parameters are determined for scanning, then the DQS and the PHY _ DQS delay parameters are determined in sequence, and the process is repeated.
Step S102: and determining an available delay parameter interval to be confirmed from the delay parameter range to be adjusted according to an initial scanning point, wherein the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller 102 is successful.
The way of setting the initial scanning point is as follows: and updating the middle values of one or more generated available memory delay parameter intervals to the initial scanning points of the parameter types in real time until the fluctuation of the initial values and the ending values of the available memory delay parameter intervals of each parameter type is within the preset threshold range. The initial delay parameter interval belongs to a delay parameter interval with lower precision and wider range, and the available delay interval of the memory generated each time has higher precision relative to the initial delay parameter interval, so the midpoint of the available delay interval of the memory corresponding to one or two delay parameters of which the available delay interval of the memory is generated is used as a fixed scanning parameter, and the initial delay parameter interval corresponding to the delay parameter of which the available delay interval of the memory is not generated is reduced, and a new target delay parameter interval is also obtained. Then, the midpoint value of the available delay intervals of the two memories is continuously updated to the initial scanning point of the corresponding parameter type, and the available delay interval of the memory of the other parameter is continuously reduced to obtain a new available delay interval of the memory corresponding to the parameter type. The above operations are performed for each parameter type in turn until the fluctuation of the start value and the end value of the available delay parameter interval of the memory of each parameter type is within the preset threshold value range.
In this embodiment, the starting scanning point is preferably but not limited to a middle point of the range of the delay parameter to be adjusted, and the manner for determining whether the starting scanning point scans successfully may be: controlling a DDR controller 102 configured with a middle point of a delay parameter range to be adjusted to write self-defined data into a DDR103 in advance, and recording a storage address; controlling the DDR controller 102 to read out the self-test data according to the storage address; and when the read self-checking data is consistent with the self-checking data defined in advance, setting the middle point of the preset delay parameter range to be adjusted as an initial scanning point.
The self-checking data reading and writing scanning mode is as follows: controlling the DDR controller 102 to write self-check data defined in advance into the DDR103, and recording a storage address; controlling the DDR controller 102 to read out the self-test data according to the storage address; and when the read self-checking data is consistent with the self-checking data defined in advance, determining that the read-write scanning is successful. In this embodiment, the self-test data may be set empirical self-test data, for example, "0 x00000000," "0 xfffffffff," "0 xfffff 0000," "0 xa5a5a5a5," and "0 x5a5a5a5a," and in order to ensure the reliability of successful read-write scanning, the previous five self-test data may be read-write scanned respectively.
In this embodiment, the manner of determining the available delay parameter interval to be confirmed is, but not limited to: and taking the middle point of the delay parameter range to be adjusted as a separation point, and separating the delay time adjustment range into two first data intervals. For example, if the data of the delay time adjustment range is (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19), the initial scan point is 10, and the two first data intervals are (1, 2, 3, 4, 5, 6, 7, 8, 9, 10), (11, 12, 13, 14, 15, 16, 17, 18, 19), respectively. And respectively taking the middle points of the two first data intervals as the starting point and the end point of the available delay parameter interval to be confirmed, namely the available delay parameter interval to be confirmed is (5, 15).
Step S103: and performing dichotomy iterative operation according to the available delay parameter interval to be confirmed until a first limit value point and a second limit value point are determined in the available delay parameter interval to be confirmed.
The first limit value point is a starting value when the last read-write scanning is successful in the dichotomy iterative operation, and the second limit value point is an ending value when the last read-write scanning is successful in the dichotomy iterative operation.
Specifically, as shown in fig. 3, the specific implementation manner of step S103 may be:
step 1031: and determining an available delay parameter interval to be confirmed from the delay parameter range to be adjusted according to an initial scanning point, wherein the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller 102 is successful.
Step 1032: the first delay time point to be confirmed and the second delay time point to be confirmed are respectively configured to the DDR controller 102 to perform read-write scanning on the preset self-test data.
The first to-be-confirmed delay time point is a starting value of the to-be-confirmed available delay parameter interval, and the second to-be-confirmed delay time point is an ending value of the to-be-confirmed available delay parameter interval. Specifically, the read/write scanning manner is the same as that described above, and will not be described herein again.
Step 1033: and confirming the first division direction and the second division direction according to the result of the read-write scanning.
Wherein confirming the first division direction comprises: when the read-write scanning corresponding to the first to-be-confirmed delay point is successful, obtaining an updated first to-be-confirmed delay point; the updated first delay time to be confirmed is a point in a direction in which the first delay time to be confirmed before updating is far away from the initial value (for example, a midpoint between the first delay time to be confirmed before updating and the initial value of the delay parameter range to be adjusted); when the read-write scanning corresponding to the first to-be-confirmed delay point fails, the first division direction includes: obtaining an updated first to-be-confirmed delay point; the updated first to-be-confirmed delay time point is a point in a direction in which the first to-be-confirmed delay time point before updating is close to the start value (for example, a midpoint between the first to-be-confirmed delay time point before updating and the start scanning point).
Confirming the second division direction includes: when the read-write scanning corresponding to the second delay point to be confirmed is successful, obtaining an updated second delay point to be confirmed; the updated second delay point to be confirmed is a point in the direction in which the second delay point to be confirmed before updating is close to the end value (for example, a midpoint between the second delay point to be confirmed before updating and the end value of the delay parameter range to be adjusted); when the read-write scanning corresponding to the first to-be-confirmed delay point fails, the first division direction includes: obtaining an updated second time delay point to be confirmed; the updated second to-be-confirmed delay time point is a point in a direction in which the second to-be-confirmed delay time point before updating is far from the end value (for example, a midpoint between the second to-be-confirmed delay time point before updating and the initial scanning point); and taking the first division direction as the iteration direction of the first delay point to be confirmed and the second division direction as the iteration direction of the second delay point to be confirmed.
Step 1034: taking the updated first delay point to be confirmed as a starting value and the updated second delay point to be confirmed as an ending value, repeatedly and respectively configuring the first delay point to be confirmed and the second delay point to be confirmed to the DDR controller 102 to perform read-write scanning on the preset self-checking data until a first limit value point and a second limit value point are obtained; the first limit value point is the initial value of the last scanning success, and the second limit value point is the ending value of the last scanning success.
Step S104: and taking the interval constructed by the first limit value point and the second limit value point as the available delay parameter interval of the memory.
Step S105: and constructing a delay operation array by using the delay parameters corresponding to the logic sequence in the available delay parameter intervals of the memories corresponding to the multiple parameter types, thereby generating multiple delay operation arrays.
For example, when the available delay parameter intervals of the memory corresponding to the DQS delay parameter, the PHY _ DQS delay parameter, and the CLK delay parameter are (2, 3, 4), and (3, 4, 5), respectively, the delay operation arrays are (2, 2, 3), (3, 3, 4), (4, 4, 5), respectively.
Step S106: when the DDR controller 102 is configured with different delay running arrays, a power-on program prestored in the external Flash is run.
For example, the delay run arrays (2, 2, 3), (3, 3, 4), (4, 4, 5) are configured to the DDR controller 102 at different time points, respectively. Wherein, the condition for determining the successful operation of the power-on program is as follows: the received actual power-on times recorded by the external relay are consistent with the startup times recorded by the processor 101, and no notification of power-on program operation breakdown is received.
Step S107: and taking the delay operation array configured by the DDR controller 102 when the power-on program is successfully operated as the preferred delay operation array.
For example, when the DDR controller 102 configures the delayed operation arrays (2, 2, 3), (3, 3, 4) and (4, 4, 5), only (2, 2, 3) and (3, 3, 4) can normally operate the power-on program in the external Flash, the delayed operation arrays (2, 2, 3) and (3, 3, 4) are the preferred delayed operation arrays.
Step S108: when the DDR controller 102 is configured with different preferred delayed running arrays, the power-on program pre-stored in the BootRam104 is controlled to run under different temperature environments.
Step S109: and taking the optimal delay operation array configured by the DDR controller 102 when the power-on program is successfully operated in all temperature environments as the optimal delay operation array.
Considering that the environment temperature has influence on the operation of the power-on program, the power-on program can be operated in three temperature environments of high temperature, normal temperature and low temperature. For example, when the preferred delayed operation array (2, 2, 3), (3, 3, 4) is configured only by the DDR103 control in the preferred delayed operation array (3, 3, 4) to normally operate the power-on program under all temperature environments, (3, 3, 4) is the optimal delayed operation array, while the memory available delay interval of the DQS delay parameter is only 3, the memory available delay interval of the PHY _ DQS delay parameter is only 4, and the memory available delay interval of the CLK delay parameter is only 4.
Referring to fig. 4, an embodiment of the present invention further provides an apparatus for optimizing an available delay parameter interval of a memory, and it should be noted that the basic principle and the generated technical effect of the apparatus for optimizing an available delay parameter interval of a memory provided in the embodiment are the same as those of the above embodiment, and for brief description, reference may be made to corresponding contents in the above embodiment for parts that are not mentioned in the embodiment. The available delay parameter interval optimizing device comprises an interval determining unit 301, an iterative operation unit 302 and a target interval constructing unit 303.
The interval determining unit 301 is configured to determine an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, where the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller 102 is successful.
The iterative operation unit 302 is configured to perform a bisection iterative operation according to the to-be-confirmed available delay parameter interval until a first limit value point and a second limit value point are determined in the to-be-confirmed available delay parameter interval, where the first limit value point is a starting value when the last read-write scanning in the bisection iterative operation is successful, and the second limit value point is an ending value when the last read-write scanning in the bisection iterative operation is successful.
The target interval construction unit 303 is configured to determine an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, where the interval constructed by the first limit value point and the second limit value point is used as an available delay parameter interval of the memory, and the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller 102 is successful.
The iterative operation unit 302 is configured to perform a bisection iterative operation according to the to-be-confirmed available delay parameter interval until a first limit value point and a second limit value point are determined in the to-be-confirmed available delay parameter interval, where the first limit value point is a starting value when the last read-write scanning in the bisection iterative operation is successful, and the second limit value point is an ending value when the last read-write scanning in the bisection iterative operation is successful.
The target interval construction unit 303 is configured to use an interval constructed by the first limit value point and the second limit value point as a delay parameter interval available for the memory.
Referring to fig. 2, an embodiment of the present invention provides an electronic terminal, which includes a DDR103, a DDR controller 102, a BootRam, a processor 101, and a device for optimizing an available delay parameter interval of a memory; the DDR controller 102 is electrically connected to the BootRam, the DDR103 and the BootRam, respectively, and the DDR103, the DDR controller 102, the BootRam and the processor 101 may be integrated into a chip platform daughter board. The device is installed in Bootram and comprises one or more software functional units executed by a processor 101, and the available delay parameter interval optimizing device comprises:
the interval determining unit 301 is configured to determine an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, where the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller 102 is successful.
It is to be understood that the section determining unit 301 may perform the above-described step S101.
The iterative operation unit 302 is configured to perform a binary iterative operation according to the to-be-confirmed available delay parameter interval until a first limit value point and a second limit value point are determined in the to-be-confirmed available delay parameter interval.
It is to be understood that the iterative operation unit 302 may perform step S102 described above.
The first limit value point is a starting value when the last read-write scanning is successful in the dichotomy iterative operation, and the second limit value point is an ending value when the last read-write scanning is successful in the dichotomy iterative operation.
The target interval construction unit 303 is configured to use an interval constructed by the first limit value point and the second limit value point as a delay parameter interval available for the memory.
It is to be understood that the target section construction unit 303 may perform the above-described step S103.
The embodiment of the present invention further provides a storage medium, where the storage medium stores a computer instruction, where the computer instruction, when being read and executed, executes the method for optimizing the available delay parameter interval of the memory according to the above embodiment.
In summary, the device and method for optimizing an available delay parameter interval of a storage medium, an electronic terminal, and a memory according to embodiments of the present invention determine an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, where the initial scanning point is a configured delay parameter when initial read-write scanning of a DDR controller succeeds; then, performing bisection iteration operation according to the available delay parameter interval to be confirmed until a first limit value point and a second limit value point are determined in the available delay parameter interval to be confirmed, wherein the first limit value point is a starting value when the last read-write scanning in the bisection iteration operation is successful, and the second limit value point is an ending value when the last read-write scanning in the bisection iteration operation is successful; and finally, the interval constructed by the first limit value point and the second limit value point is used as an available delay parameter interval of the memory, so that the consumed time is short, the efficiency is very high, and the reliability of the generated available delay parameter interval of the memory is high.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes. It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Claims (9)
1. A method for optimizing an available delay parameter interval of a memory is characterized by comprising the following steps:
determining an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, wherein the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller is successful;
performing bisection iteration operation according to the available delay parameter interval to be confirmed until a first limit value point and a second limit value point are determined in the available delay parameter interval to be confirmed, wherein the first limit value point is a starting value when the last read-write scanning in the bisection iteration operation is successful, and the second limit value point is an ending value when the last read-write scanning in the bisection iteration operation is successful;
taking an interval constructed by the first limit value point and the second limit value point as an available delay parameter interval of a memory;
performing a bisection iterative operation according to the to-be-confirmed available delay parameter interval until a first limit value point and a second limit value point are determined in the to-be-confirmed available delay parameter interval, including:
determining an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, wherein the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller is successful;
respectively configuring a first delay point to be confirmed and a second delay point to be confirmed to the DDR controller to perform read-write scanning on preset self-checking data; the first to-be-confirmed delay time point is a starting value of the to-be-confirmed available delay parameter interval, and the second to-be-confirmed delay time point is an ending value of the to-be-confirmed available delay parameter interval;
confirming a first division direction and a second division direction according to the reading and writing scanning result;
wherein the confirming the first division direction comprises:
when the read-write scanning corresponding to the first to-be-confirmed delay point is successful, obtaining an updated first to-be-confirmed delay point; the updated first to-be-confirmed delay time point is a point in the direction in which the first to-be-confirmed delay time point before updating is far away from the initial value;
when the read-write scanning corresponding to the first delay point to be confirmed fails, the first dividing direction includes: obtaining an updated first to-be-confirmed delay point; the updated first to-be-confirmed delay time point is a point in the direction in which the first to-be-confirmed delay time point before updating is close to the initial value;
the confirming the second division direction includes:
when the read-write scanning corresponding to the second delay point to be confirmed is successful, obtaining an updated second delay point to be confirmed; the updated second delay point to be confirmed is a point in the direction that the second delay point to be confirmed before updating is close to the ending value;
when the read-write scanning corresponding to the first delay point to be confirmed fails, the first dividing direction includes: obtaining an updated second time delay point to be confirmed; the updated second to-be-confirmed delay time point is a point in the direction in which the second to-be-confirmed delay time point before updating is far away from the end value;
taking the first division direction as the iteration direction of the first delay point to be confirmed, and taking the second division direction as the iteration direction of the second delay point to be confirmed;
taking the updated first delay point to be confirmed as the initial value and the updated second delay point to be confirmed as the end value, and repeatedly configuring the first delay point to be confirmed and the second delay point to be confirmed to the DDR controller respectively to perform read-write scanning on preset self-checking data until a first limit value point and a second limit value point are obtained; the first limit value point is a starting value of the last scanning success, and the second limit value point is an ending value of the last scanning success.
2. The method as claimed in claim 1, wherein the delay parameter includes a plurality of types, and before the step of determining the available delay parameter interval to be confirmed from the range of delay parameter to be adjusted according to the starting scanning point, the method further comprises:
taking a preliminary delay parameter interval corresponding to one of the multiple delay parameters as a delay parameter range to be adjusted in turn, and keeping the corresponding preset preliminary available delay intervals of the other parameter types unchanged;
the mode of setting the initial scanning point is as follows: and updating the middle values of one or more generated available memory delay parameter intervals to the starting scanning point of the parameter category in real time until the fluctuation of the starting value and the ending value of the available memory delay parameter interval of each parameter category is within a preset threshold range.
3. The method of claim 2, wherein the step of optimizing the available delay parameter interval further comprises:
constructing a delay operation array by using delay parameters corresponding to a logic sequence in a delay parameter interval available for a memory corresponding to a plurality of parameter types, thereby generating a plurality of delay operation arrays;
when the DDR controller is configured with different delay operation arrays, operating a power-on program prestored in an external Flash;
and taking the delay operation array configured by the DDR controller when the power-on program is successfully operated as the preferred delay operation array.
4. The method of claim 3, wherein the step of optimizing the available delay parameter interval further comprises:
when the DDR controller is configured with different optimal delay operation arrays, controlling a power-on program prestored in Bootram to operate under different temperature environments;
and taking the optimal delay operation array configured by the DDR controller when the power-on program is successfully operated in all temperature environments as the optimal delay operation array.
5. The method of claim 4, wherein the condition for determining the success of the power-on procedure is: and the received actual power-on times recorded by the external relay are consistent with the starting times recorded by the processor, and a notification of power-on program operation breakdown is not received.
6. The method according to claim 1, wherein the self-test data is read/written and scanned in a manner that:
controlling the DDR controller to write self-defined self-check data into the DDR, and recording a storage address;
controlling the DDR controller to read the self-checking data according to the storage address;
and when the read self-checking data is consistent with the self-checking data defined in advance, determining that the read-write scanning is successful.
7. An apparatus for optimizing an available delay parameter interval of a memory, the apparatus comprising:
the interval determining unit is used for determining an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, wherein the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller is successful;
the iterative operation unit is used for performing bisection iterative operation according to the available delay parameter interval to be confirmed until a first limit value point and a second limit value point are determined in the available delay parameter interval to be confirmed, wherein the first limit value point is a starting value when the last read-write scanning in the bisection iterative operation is successful, and the second limit value point is an ending value when the last read-write scanning in the bisection iterative operation is successful;
a target interval construction unit, configured to use an interval constructed by the first limit value point and the second limit value point as an available delay parameter interval of the memory;
the device comprises an iterative operation unit, a data processing unit and a data processing unit, wherein the iterative operation unit is specifically used for determining an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, and the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller is successful;
respectively configuring a first delay point to be confirmed and a second delay point to be confirmed to the DDR controller to perform read-write scanning on preset self-checking data; the first to-be-confirmed delay time point is a starting value of the to-be-confirmed available delay parameter interval, and the second to-be-confirmed delay time point is an ending value of the to-be-confirmed available delay parameter interval;
confirming a first division direction and a second division direction according to the reading and writing scanning result;
wherein the confirming the first division direction comprises:
when the read-write scanning corresponding to the first to-be-confirmed delay point is successful, obtaining an updated first to-be-confirmed delay point; the updated first to-be-confirmed delay time point is a point in the direction in which the first to-be-confirmed delay time point before updating is far away from the initial value;
when the read-write scanning corresponding to the first delay point to be confirmed fails, the first dividing direction includes: obtaining an updated first to-be-confirmed delay point; the updated first to-be-confirmed delay time point is a point in the direction in which the first to-be-confirmed delay time point before updating is close to the initial value;
the confirming the second division direction includes:
when the read-write scanning corresponding to the second delay point to be confirmed is successful, obtaining an updated second delay point to be confirmed; the updated second delay point to be confirmed is a point in the direction that the second delay point to be confirmed before updating is close to the ending value;
when the read-write scanning corresponding to the first delay point to be confirmed fails, the first dividing direction includes: obtaining an updated second time delay point to be confirmed; the updated second to-be-confirmed delay time point is a point in the direction in which the second to-be-confirmed delay time point before updating is far away from the end value;
taking the first division direction as the iteration direction of the first delay point to be confirmed, and taking the second division direction as the iteration direction of the second delay point to be confirmed;
taking the updated first delay point to be confirmed as the initial value and the updated second delay point to be confirmed as the end value, and repeatedly configuring the first delay point to be confirmed and the second delay point to be confirmed to the DDR controller respectively to perform read-write scanning on preset self-checking data until a first limit value point and a second limit value point are obtained; the first limit value point is a starting value of the last scanning success, and the second limit value point is an ending value of the last scanning success.
8. An electronic terminal is characterized by comprising a DDR controller, a Bootram controller, a processor and a device for optimizing available delay parameter intervals of a memory; the DDR controller is electrically connected with the Bootram, the DDR and the Bootram respectively,
the apparatus is installed in the Bootram and comprises one or more software functional units executed by the processor, and the available delay parameter interval optimizing apparatus comprises:
the interval determining unit is used for determining an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, wherein the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller is successful;
the iterative operation unit is used for performing bisection iterative operation according to the available delay parameter interval to be confirmed until a first limit value point and a second limit value point are determined in the available delay parameter interval to be confirmed, wherein the first limit value point is a starting value when the last read-write scanning in the bisection iterative operation is successful, and the second limit value point is an ending value when the last read-write scanning in the bisection iterative operation is successful;
a target interval construction unit, configured to use an interval constructed by the first limit value point and the second limit value point as an available delay parameter interval of the memory;
the device comprises an iterative operation unit, a data processing unit and a data processing unit, wherein the iterative operation unit is specifically used for determining an available delay parameter interval to be confirmed from a delay parameter range to be adjusted according to an initial scanning point, and the initial scanning point is a configured delay parameter when the initial read-write scanning of the DDR controller is successful;
respectively configuring a first delay point to be confirmed and a second delay point to be confirmed to the DDR controller to perform read-write scanning on preset self-checking data; the first to-be-confirmed delay time point is a starting value of the to-be-confirmed available delay parameter interval, and the second to-be-confirmed delay time point is an ending value of the to-be-confirmed available delay parameter interval;
confirming a first division direction and a second division direction according to the reading and writing scanning result;
wherein the confirming the first division direction comprises:
when the read-write scanning corresponding to the first to-be-confirmed delay point is successful, obtaining an updated first to-be-confirmed delay point; the updated first to-be-confirmed delay time point is a point in the direction in which the first to-be-confirmed delay time point before updating is far away from the initial value;
when the read-write scanning corresponding to the first delay point to be confirmed fails, the first dividing direction includes: obtaining an updated first to-be-confirmed delay point; the updated first to-be-confirmed delay time point is a point in the direction in which the first to-be-confirmed delay time point before updating is close to the initial value;
the confirming the second division direction includes:
when the read-write scanning corresponding to the second delay point to be confirmed is successful, obtaining an updated second delay point to be confirmed; the updated second delay point to be confirmed is a point in the direction that the second delay point to be confirmed before updating is close to the ending value;
when the read-write scanning corresponding to the first delay point to be confirmed fails, the first dividing direction includes: obtaining an updated second time delay point to be confirmed; the updated second to-be-confirmed delay time point is a point in the direction in which the second to-be-confirmed delay time point before updating is far away from the end value;
taking the first division direction as the iteration direction of the first delay point to be confirmed, and taking the second division direction as the iteration direction of the second delay point to be confirmed;
taking the updated first delay point to be confirmed as the initial value and the updated second delay point to be confirmed as the end value, and repeatedly configuring the first delay point to be confirmed and the second delay point to be confirmed to the DDR controller respectively to perform read-write scanning on preset self-checking data until a first limit value point and a second limit value point are obtained; the first limit value point is a starting value of the last scanning success, and the second limit value point is an ending value of the last scanning success.
9. A storage medium storing computer instructions, wherein the computer instructions when read and executed perform a method for optimizing a memory usable delay parameter interval according to any one of claims 1 to 6.
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