CN109638026B - Deep trench isolation structure of CMOS image sensor and manufacturing method thereof - Google Patents
Deep trench isolation structure of CMOS image sensor and manufacturing method thereof Download PDFInfo
- Publication number
- CN109638026B CN109638026B CN201710976676.8A CN201710976676A CN109638026B CN 109638026 B CN109638026 B CN 109638026B CN 201710976676 A CN201710976676 A CN 201710976676A CN 109638026 B CN109638026 B CN 109638026B
- Authority
- CN
- China
- Prior art keywords
- layer
- trench isolation
- trenches
- isolation structure
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 105
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000011049 filling Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims description 40
- 238000005468 ion implantation Methods 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000005137 deposition process Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 154
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 229920005591 polysilicon Polymers 0.000 description 15
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 9
- 229910052721 tungsten Inorganic materials 0.000 description 9
- 239000010937 tungsten Substances 0.000 description 9
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 8
- 239000011733 molybdenum Substances 0.000 description 8
- 229910052750 molybdenum Inorganic materials 0.000 description 8
- 238000002161 passivation Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052593 corundum Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention discloses a deep trench isolation structure of a CMOS image sensor and a manufacturing method thereof. The first trench isolation structure is formed in the first surface of the substrate, wherein the first trench isolation structure comprises a first filling layer and a first dielectric liner layer wrapping the surface of the first filling layer. The second trench isolation structure is formed in a second surface of the substrate opposite to the first surface, and the second trench isolation structure comprises a second filling layer and a second dielectric liner layer wrapping the surface of the second filling layer, wherein the bottom surface of the second dielectric liner layer is in direct contact with the bottom surface of the first dielectric liner layer.
Description
Technical Field
The present invention relates to a CMOS (complementary metal oxide semiconductor) image sensor technology, and more particularly, to a Deep Trench Isolation (DTI) structure of a CMOS image sensor and a method for fabricating the same.
Background
The deep trench isolation structure in the CMOS image sensor is used for isolating light and charges between the CMOS image sensors to reduce crosstalk (crosstalk) between pixels.
The DTI of the prior art still occupies a considerable element area when the pixel size (pixel size) is reduced due to the limitation of the manufacturing process. But such a width allows the area of the photo sensing area to be relatively reduced, resulting in a lower potential well capacity (FWC).
In addition, a back side DTI commonly used in the prior art cannot extend to the front surface and cannot achieve complete isolation, especially for long wavelength light and charge crosstalk. In addition, in the formation of the back-wafer DTI, in order to avoid the influence of high temperature on the device formed on the front surface of the chip in the back-end-of-line (BEOL), it is necessary to control the temperature of heat transfer to the metal wiring of the BEOL to be 400 ℃ or lower in the annealing step in the passivation step when forming the back-wafer DTI, so that it is difficult to control the heat source inputted from the back-wafer and it is difficult to achieve the purpose of activating the DTI surface doping at high temperature. Therefore, it is difficult to effectively passivate silicon damage (silicon Damage) caused by DTI etching in the deeper region of the crystal-backed DTI by thermal annealing (thermal annealing).
Disclosure of Invention
The invention provides a deep trench isolation structure of a CMOS image sensor, which has a narrow deep trench isolation structure and can improve the capacity of a potential well.
The invention also provides a method for manufacturing the deep trench isolation structure of the CMOS image sensor, which can manufacture a narrow deep trench isolation structure to keep a larger light sensing area.
The deep trench isolation structure of the CMOS image sensor comprises a substrate containing a plurality of light sensing areas and a plurality of isolation structures respectively positioned between the light sensing areas. Each isolation structure includes first and second trench isolation structures. The first trench isolation structure is formed in the first surface of the substrate, wherein the first trench isolation structure comprises a first filling layer and a first dielectric liner layer wrapping the surface of the first filling layer. The second trench isolation structure is formed in a second surface of the substrate, and the second surface is opposite to the first surface. The second trench isolation structure comprises a second filling layer and a second dielectric liner layer wrapping the surface of the second filling layer, and the bottom surface of the second dielectric liner layer is in direct contact with the bottom surface of the first dielectric liner layer.
In an embodiment of the invention, the first and second filling layers each independently include a conductive layer or a dielectric layer.
In an embodiment of the invention, the first filling layer includes a polysilicon layer or a doped polysilicon layer.
In an embodiment of the invention, the second filling layer includes a titanium nitride liner and a tungsten layer or a titanium nitride liner and a molybdenum layer.
In an embodiment of the invention, the thickness of the first dielectric liner layer is 0.5nm to 50 nm.
In an embodiment of the invention, the thickness of the second dielectric liner layer is 0.5nm to 50 nm.
In an embodiment of the invention, a width of the first trench isolation structure is equal to a width of the second trench isolation structure.
In an embodiment of the invention, a width of the first trench isolation structure is greater than a width of the second trench isolation structure.
In an embodiment of the invention, a difference between depths of the first trench isolation structure and the second trench isolation structure is less than 50% of a depth of each of the isolation structures.
In an embodiment of the invention, the first trench isolation structure and the second trench isolation structure are respectively a multi-layer structure of a dielectric layer and a conductive layer or a structure composed of dielectric layers.
The manufacturing method of the deep trench isolation structure of the CMOS image sensor comprises the following steps. A substrate including a plurality of light sensing regions is provided, and a plurality of first trenches are formed in a first surface of the substrate between the light sensing regions. A first dielectric liner layer is formed on the surface of the first trench, and a first filling layer is filled in the first trench to form a plurality of first trench isolation structures including the first dielectric liner layer and the first filling layer. A plurality of second trenches corresponding to the first trench isolation structures are formed in the second surface of the substrate, and the bottom surfaces of the first dielectric liners of the first trench isolation structures are exposed. And forming a second dielectric liner layer on the surface of the second trench, and filling a second filling layer in the second trench to form a plurality of second trench isolation structures comprising the second dielectric liner layer and the second filling layer.
In another embodiment of the present invention, an ion implantation step may be further performed after the first trench is formed, so as to passivate the surface of the first trench.
In another embodiment of the present invention, a method of forming the first dielectric liner layer includes a thermal oxidation method, a nitridation method, a dielectric layer deposition process, or a combination thereof.
In another embodiment of the present invention, an ion implantation step may be further performed after the second trench is formed, so as to passivate the surface of the second trench.
In another embodiment of the present invention, the method of forming the second dielectric liner layer includes a thermal oxidation method, a nitridation method, a dielectric layer deposition process, or a combination thereof.
In another embodiment of the present invention, the step of forming the first trench includes simultaneously forming a trench as a positioning mark in the substrate outside the photo sensing region.
In another embodiment of the present invention, before forming the second trench, an infrared alignment instrument may be used to align the positioning mark to align the second trench with the first trench.
In another embodiment of the present invention, the first trench isolation structure and the second trench isolation structure are formed independently as a multi-layer structure of a dielectric layer and a conductive layer or a structure composed of dielectric layers.
In another embodiment of the present invention, after the second trench isolation structure is formed, a passivation process may be performed on the second surface of the substrate.
In another embodiment of the present invention, an ion implantation step may be further performed after the second trench is formed, so as to simultaneously passivate the surface of the second trench and the second surface.
In another embodiment of the present invention, after the first trench isolation structure is formed, a bottom surface of the substrate opposite to the first surface may be polished or etched to the second surface.
In another embodiment of the present invention, the second surface of the substrate may be passivated after the grinding or etching step.
Based on the above, the shallow trench isolation structures are formed from the front and the back of the substrate respectively, which is beneficial to performing the trench surface doping procedure, the trench filling procedure and the thermal annealing procedure, and thus the width of the deep trench isolation structure can be reduced, the area of the photodiode can be increased, and meanwhile, the problem that the conventional back-side DTI cannot effectively isolate long-wavelength light and charges and thermally anneal the long-wavelength light and the charges is solved, so that the shallow trench isolation structure is suitable for the CIS structure with the increased potential well capacity.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic cross-sectional view of a CMOS image sensor including a deep trench isolation structure according to a first embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view illustrating a deep trench isolation structure of a CMOS image sensor according to a second embodiment of the present invention;
fig. 3A to fig. 3G are schematic cross-sectional views illustrating a manufacturing process of a deep trench isolation structure of a CMOS image sensor according to a third embodiment of the present invention.
Description of the symbols
100. 300, and (2) 300: substrate
100a, 300 a: first surface
100b, 300 c: second surface
102. 302: light sensing area
104: isolation structure
106. 200, 312: first trench isolation structure
108. 328: second trench isolation structure
110. 310: first filling layer
110a, 114a, 306a, 322a surface
112. 308: first dielectric liner
112a, 116a, 300b, 308 a: bottom surface
114. 326: second filling layer
116. 324: second dielectric liner
118: transistor with a metal gate electrode
120. 316: grid electrode
122. 314: gate dielectric layer
124. 126, 319a, 319 b: p + region
128. 330: anti-reflection layer
130. 332: color filter
132. 344: micro-lens
304. 320, and (3) respectively: hard mask layer
306: first trench
318: interlayer dielectric layer
322: second trench
d1, d 2: depth of field
t1, t 2: thickness of
V1, V2: bias voltage
w1, w 2: width of
Detailed Description
Some embodiments are listed below and described in detail with reference to the attached drawings, but the embodiments are not provided to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, like elements in the following description will be described with like reference numerals. In addition, the terms "including", "having", and the like, as used herein, are open-ended terms; that is, including but not limited to. Also, directional phrases used herein, such as: the terms "upper" and "lower" are used only in reference to the direction of the drawings. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting.
FIG. 1 is a cross-sectional view of a CMOS Image Sensor (CIS) including a deep trench isolation structure (DTI) according to a first embodiment of the present invention.
Referring to fig. 1, the deep trench isolation structure of the present embodiment is used for a CMOS image sensor, and includes a substrate 100 having a plurality of photo sensing regions 102 and a plurality of isolation structures 104 respectively located between the photo sensing regions 102. Each isolation structure 104 includes a first trench isolation structure 106 and a second trench isolation structure 108. The first trench isolation structure 106 is formed in the first surface 100a of the substrate 100, wherein the first trench isolation structure 106 includes a first filling layer 110 and a first dielectric liner layer 112 covering the surface 110a of the first filling layer 110, wherein the first dielectric liner layer 112 is, for example, SiO2、Si3N4、SiON、 TiO2、Al2O3Etc. or combinations thereof. The first filling layer 110 may be a dielectric layer or a conductive layer. If the first filling layer 110 is a conductive layer, it is made of a material such as a polysilicon layer, a doped polysilicon layer, a tungsten layer, a molybdenum layer, or a combination thereof; preferably a polysilicon layer or a doped polysilicon layer. The second trench isolation structure 108 is formed on the substrate 100The second surface 100b is opposite to the first surface 100 a. The second trench isolation structure 108 includes a second filling layer 114 and a second dielectric liner layer 116 covering a surface 114a of the second filling layer 114, and a bottom surface 116a of the second dielectric liner layer 116 is in direct contact with a bottom surface 112a of the first dielectric liner layer 112. In one embodiment, the second dielectric liner 116 is, for example, SiO2、Si3N4、SiON、TiO2、Al2O3Etc. or combinations thereof. The second filling-up layer 114 can be a dielectric layer or a conductive layer. If the second filling layer 114 is a conductive layer, it is made of a material such as a polysilicon layer, a doped polysilicon layer, a tungsten layer, a molybdenum layer, or a combination thereof; preferably tungsten layer, molybdenum layer, etc. having heat-resistant, corrosion-resistant and wear-resistant characteristics, and may be combined with a barrier layer such as a titanium nitride liner (TiN liner). If the first filling layer 110 and the second filling layer 114 are conductive layers, the first filling layer 110 may be biased with a voltage V1 and the second filling layer 114 may be biased with a voltage V2 to reduce dark current (dark current) and signal delay (signal lag), wherein V1 and V2 may be the same or different. If the first filling layer 110 and/or the second filling layer 114 are dielectric layers, the effect of isolating light and charges between the light sensing regions 102 can be achieved. In addition, the thickness t1 of the first dielectric liner 112 is, for example, 0.5nm to 50 nm; the thickness t2 of the second dielectric liner 116 is, for example, 0.5nm to 50 nm; within the thickness range, the film structure and the capacitance characteristic can be considered at the same time. Therefore, the first trench isolation structure 106 and the second trench isolation structure 108 may be a multi-layer structure of a dielectric layer and a conductive layer or a structure composed of dielectric layers. In the present embodiment, the depth difference between the first trench isolation structure 106 and the second trench isolation structure 108 (i.e., the absolute value of the depth d1 minus the depth d2) is, for example, less than 50% of the depth of each isolation structure 104 (i.e., the depth d1 plus the depth d 2). Therefore, the first trench isolation structure 106 and the second trench isolation structure 108 can meet the threshold of the manufacturing process, and have narrower widths w1 and w2 than the conventional deep trench isolation structure, and can increase the area of the photo sensing region 102, thereby increasing the well capacitance (FWC).
In the CMOS image sensor of fig. 1, the transistor 118 is disposed on the first surface 100a, and may include a gate 120, a gate dielectric layer 122 between the gate 120 and the first surface 100a, the substrate 100 (e.g., P-type region), and the light sensing region 102 (e.g., N-type region). P + regions 124 and 126, which are present after passivation, may also be included on both sides of the light sensing region 102 of the CMOS image sensor, such as the first surface 100a and the second surface 100 b. In addition, the CMOS image sensor may further include an anti-reflection layer (ARC)128 disposed on the second surface 100b, a color filter (color filter)130 disposed on the anti-reflection layer 128, and a micro lens (micro lenses) 132 disposed on the color filter 130. However, the deep trench isolation structure of the present invention is not limited to be used in the above-mentioned CMOS image sensor; in other embodiments, the transistors 118 on the first surface 100a and the optical components on the second surface 100b may be changed or increased or decreased as required, and various front-end-of-line (FEOL) and back-end-of-line (BEOL) circuits (not shown) may be disposed on the substrate 100.
In the first embodiment, the width w1 of the first trench isolation structure 106 is substantially equal to the width w2 of the second trench isolation structure 108, but the invention is not limited thereto. Fig. 2 is a cross-sectional view of a deep trench isolation structure of a CMOS image sensor according to a second embodiment of the present invention. Reference numerals and parts of the first embodiment are used in fig. 2, wherein the same reference numerals are used to designate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the description of the embodiments is not repeated.
In fig. 2, the width w1 of the first trench isolation structure 200 is greater than the width w2 of the second trench isolation structure 108, so that the alignment of the second trench isolation structure 108 can be facilitated after the first trench isolation structure 200 is formed, and the deep trench isolation structure can maintain its function even if the position of the second trench isolation structure 108 is slightly shifted.
FIGS. 3A to 3G are schematic cross-sectional views illustrating a process for fabricating a deep trench isolation structure of a CMOS image sensor according to a third embodiment of the present invention.
Referring to FIG. 3A, a substrate 300 including a plurality of photo sensing regions 302 is provided, wherein the substrate 300 is, for example, a P-type substrate, and the photo sensing regions 302 are, for example, N-type doped regions. Then, a plurality of first trenches 306 may be formed in the first surface 300a of the substrate 300 between the light sensing regions 302 using a hard mask layer 304 as an etching mask; in addition, the light sensing region 302 may also be formed after the first trench 306 is etched. In the present embodiment, after the first trench 306 is formed, an ion implantation process may be performed to passivate the surface 306a (including the side and bottom surfaces) of the first trench 306 after the first trench 306 is cleaned, for example, a p-type dopant is implanted, and the method further includes plasma doping (PLAD). Then, a thermal annealing process is performed to activate the implanted dopants. In another embodiment, the ion implantation step to passivate the surface 306a of the first trench 306 may be omitted if the structure in the first trench 306 in the subsequent pass has a line circumscribing.
Then, referring to fig. 3B, a first dielectric liner layer 308 is formed on the surface 306a of the first trench 306 by a method such as thermal oxidation (oxidation), nitridation (nitridation), dielectric layer deposition (deposition), or a combination thereof; the material of the first dielectric liner 308 is, for example, SiO2、Si3N4、SiON、 TiO2、Al2O3These materials or combinations thereof, preferably SiO by oxidation2. Subsequently, a first filling layer 310 is filled in the first trench 306, and steps such as Chemical Mechanical Polishing (CMP) and removing the hard mask layer 304 are performed to form a plurality of first trench isolation structures 312 including the first dielectric liner layer 308 and the first filling layer 310. The first filling-up layer 310 may be a dielectric layer or a conductive layer. The first filling layer 310 is a conductive layer, such as a polysilicon layer, a doped polysilicon layer, a tungsten layer, a molybdenum layer, or a combination thereof. The first filling layer 310 may be formed by a deposition process, such as a Chemical Vapor Deposition (CVD) process or a Physical Vapor Deposition (PVD) process, preferably a doped polysilicon deposition process. In one embodiment, the first filling layer 310 is, for example, a conductive layer or a dielectric layer. For example, the first filling layer 310 can be a conductive layer (e.g., a polysilicon layer, a doped polysilicon layer, a tungsten layer, a molybdenum layer, etc.), which can cooperate with the first filling layerThe first dielectric liner layer 308 reflects light and biases the first fill layer 310 during subsequent operations to reduce dark current and signal delay, thereby eliminating the ion implantation step described above to passivate the surface of the first trench 306. In another embodiment, the first filling layer 310 can be a dielectric layer to isolate the photo-sensing regions 302 from each other. Therefore, the first trench isolation structure 312 is a multi-layer structure of dielectric layer and conductive layer or a structure composed of dielectric layers.
Next, referring to fig. 3C, before the bottom surface 300b of the substrate 300 is processed, the first surface 300a may be passivated to form a passivation region such as a p + region 319a, and then transistors are first fabricated on the first surface 300 a; such as gate dielectric 314, gate 316, interlayer dielectric 318, etc., are formed, and then the front end of line (FEOL) and back end of line (BEOL) processes of the CMOS image sensor are typically performed.
Then, referring to fig. 3D, the bottom surface (300 b of fig. 3C) of the substrate 300 opposite to the first surface 300a is polished or etched to the second surface 300C. Subsequently, the second surface 300c of the substrate 300 may be passivated (e.g., a p-type ion implantation step); also referred to as back side passivation, while a passivation region such as p + region 319b is formed at the second surface 300 c.
Then, referring to fig. 3E, a plurality of second trenches 322 corresponding to the first trench isolation structures 312 are formed in the second surface 300c of the substrate 300 by using a hard mask layer 320 as an etching mask, and the bottom surface 308a of the first dielectric liner layer 308 of each first trench isolation structure 312 is exposed. In the present embodiment, the width of the first trench isolation structure 312 is equal to the width of the second trench 322; in another embodiment, the width of the first trench isolation structure 312 may be larger than the width of the second trench 322 to facilitate the alignment of the second trench 322, even if the position of the second trench 322 is slightly shifted, without affecting the function of the subsequently formed isolation structure. And the hard mask layer 320 may be removed first after the second trench 322 is formed. In this embodiment, the second trench 322 may be further followed by an ion implantation step to passivate the surface 322a of the second trench 322, for example, the ion implantation of p-type dopant includes PLAD. In another embodiment, an ion implantation step is performed after forming the second trench to simultaneously passivate the surface 322a and the second surface 300c of the second trench 322.
In an embodiment, the step of forming the first trench 306 (as shown in fig. 3A) can also form a trench as an alignment mark in the substrate 300 outside the light sensing region 302. Since the trench as the alignment mark has the same shape as the first trench 306, the alignment mark can be aligned by an infrared alignment instrument (IR-alignment device) before forming the second trench 322 (as shown in fig. 3E) to align the second trench 322 and the first trench isolation structure 312.
Next, referring to fig. 3F, a second dielectric liner 324 is formed on the surface of the second trench 322, wherein the second dielectric liner 324 is formed by an oxidation (oxidation), a nitridation (nitridation), a deposition (deposition) process, or a combination thereof; the material of the second dielectric liner 324 is, for example, SiO2、Si3N4、SiON、TiO2、Al2O3These materials or combinations thereof, preferably deposition processes with lower process temperatures, such as Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD), to avoid high temperatures on existing lines. Then, a second filling layer 326 is filled in the second trenches 322, and a Chemical Mechanical Polishing (CMP) step is performed to form a plurality of second trench isolation structures 328 including the second dielectric liner layer 324 and the second filling layer 326. The second filling-up layer 326 can be a dielectric layer or a conductive layer. If the second filling layer 326 is a conductive layer, it is made of a material such as a polysilicon layer, a doped polysilicon layer, a tungsten layer, a molybdenum layer, or a combination thereof; preferably tungsten layer, molybdenum layer, etc. having heat-resistant, corrosion-resistant and wear-resistant characteristics, and may be combined with a barrier layer such as a titanium nitride liner (TiN liner). The second filling-up layer 326 is preferably formed by a deposition process, such as Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD), and preferably is filled with tungsten in the second trench 322. The second filling-up layer 326, such as a conductive layer, can be biased to reduce dark current and signal delay. In another embodiment, the second filling-up layer 326 may beThe dielectric layer is used to isolate the photo-sensing regions 302 from each other. The second trench isolation structure 328 is a multi-layer structure of dielectric layers and conductive layers or a structure composed of dielectric layers. The fabrication process is completed to complete the isolation structure including the first trench isolation structure 312 and the second trench isolation structure 328. In addition, if the backside passivation has not been performed, the passivation and subsequent processes may be performed on the second surface 300c of the substrate 300 after the formation of the second trench isolation structure 328.
Then, referring to fig. 3G, an anti-reflection layer 330, a color filter 332 and a microlens 324 are further sequentially formed on the second surface 300c of the substrate 300 having the deep trench isolation structure, so as to complete the CMOS image sensor. However, the manufacturing method of the deep trench isolation structure of the present invention is not limited to the process for manufacturing the above-mentioned CMOS image sensor; in other embodiments, the manufacturing processes related to the manufacturing sequence of the transistors or front end of line (FEOL) and back end of line (BEOL) on the first surface 300a and the optical components on the second surface 300c may be changed or increased or decreased as required.
In summary, the trench isolation structures are respectively formed on both sides of the substrate, so that the DTI width can be reduced by forming a shallow trench isolation structure, the area of the photodiode can be maintained while the device size is reduced, the potential well capacity can be increased, and the defects that the conventional backside DTI cannot effectively isolate long-wavelength light from charges and is difficult to thermally anneal and effectively passivate can be overcome.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (11)
1. A method for manufacturing a deep trench isolation structure of a CMOS image sensor comprises:
providing a substrate, wherein the substrate comprises a plurality of light sensing areas;
forming a plurality of first grooves in the first surface of the substrate between the light sensing regions;
forming a first dielectric liner layer on the surfaces of the first trenches;
filling a first filling layer in the first trenches to form a plurality of first trench isolation structures including the first dielectric liner and the first filling layer, wherein the first filling layer comprises a first conductive layer;
forming a plurality of second trenches corresponding to the first trench isolation structures in the second surface of the substrate, and exposing the bottom surfaces of the first dielectric liners of the first trench isolation structures;
forming a second dielectric liner layer on the surfaces of the second trenches; and
filling a second filling layer in the second trenches to form a plurality of second trench isolation structures including the second dielectric liner and the second filling layer, wherein the second filling layer includes a second conductive layer,
wherein the forming of the second trench isolation structures further comprises passivating the second surface of the substrate.
2. The method of claim 1, further comprising performing an ion implantation step after forming the first trenches to passivate the surfaces of the first trenches.
3. The method of claim 1, wherein the first dielectric liner is formed by a thermal oxidation process, a nitridation process, a dielectric deposition process, or a combination thereof.
4. The method of claim 1, further comprising performing an ion implantation step after forming the second trenches to passivate the surfaces of the second trenches.
5. The method of claim 1, wherein the second dielectric liner layer is formed by a thermal oxidation process, a nitridation process, a dielectric layer deposition process, or a combination thereof.
6. The method as claimed in claim 1, wherein the step of forming the first trenches comprises forming trenches as alignment marks in the substrate outside the light sensing regions.
7. The method of claim 6, further comprising, before forming the second trenches: and aligning the positioning marks by using an infrared alignment instrument to align the second grooves with the first grooves.
8. The method of claim 1, wherein the first trench isolation structure and the second trench isolation structure are formed independently as a multi-layer structure of dielectric layer and conductive layer or a structure composed of dielectric layer.
9. The method of claim 1, further comprising performing an ion implantation step after forming the second trenches to passivate the surface and the second surface of the second trenches.
10. The method of claim 1, further comprising polishing or etching a bottom surface of the substrate opposite the first surface to the second surface after forming the first trench isolation structures.
11. The method of claim 10, further comprising passivating the second surface of the substrate after the polishing or etching step.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106134619 | 2017-10-06 | ||
| TW106134619A TWI645554B (en) | 2017-10-06 | 2017-10-06 | Deep trench isolation of cmos image sensor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109638026A CN109638026A (en) | 2019-04-16 |
| CN109638026B true CN109638026B (en) | 2021-03-12 |
Family
ID=65431754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710976676.8A Active CN109638026B (en) | 2017-10-06 | 2017-10-19 | Deep trench isolation structure of CMOS image sensor and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109638026B (en) |
| TW (1) | TWI645554B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11171206B2 (en) * | 2019-07-11 | 2021-11-09 | Micron Technology, Inc. | Channel conduction in semiconductor devices |
| US11114443B2 (en) * | 2019-08-29 | 2021-09-07 | Micron Technology, Inc. | Semiconductor structure formation |
| CN113764258B (en) * | 2020-06-05 | 2024-05-31 | 联华电子股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN115775766B (en) * | 2023-02-02 | 2023-05-05 | 合肥晶合集成电路股份有限公司 | Forming method of shallow trench isolation structure and forming method of semiconductor device |
| CN116053289B (en) * | 2023-03-06 | 2023-06-27 | 合肥新晶集成电路有限公司 | Image sensor and method for manufacturing the same |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479711A (en) * | 2010-11-25 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Method for forming PMOS (P-channel metal oxide semiconductor) transistor |
| CN103824805A (en) * | 2014-03-11 | 2014-05-28 | 武汉新芯集成电路制造有限公司 | Rear surface isolation device and preparation method thereof |
| CN104217987A (en) * | 2013-05-31 | 2014-12-17 | 爱思开海力士有限公司 | Isolation structure and method for forming the same, and image sensor including the isolation structure and method for fabricating the image sensor |
| US9559134B2 (en) * | 2014-12-09 | 2017-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Deep trench spacing isolation for complementary metal-oxide-semiconductor (CMOS) image sensors |
| CN107039471A (en) * | 2015-11-16 | 2017-08-11 | 台湾积体电路制造股份有限公司 | Imaging sensor and its manufacture method |
| CN107123658A (en) * | 2016-02-25 | 2017-09-01 | 台湾积体电路制造股份有限公司 | Semiconductor image sensor part and its manufacture method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7148525B2 (en) * | 2004-01-12 | 2006-12-12 | Micron Technology, Inc. | Using high-k dielectrics in isolation structures method, pixel and imager device |
-
2017
- 2017-10-06 TW TW106134619A patent/TWI645554B/en active
- 2017-10-19 CN CN201710976676.8A patent/CN109638026B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479711A (en) * | 2010-11-25 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Method for forming PMOS (P-channel metal oxide semiconductor) transistor |
| CN104217987A (en) * | 2013-05-31 | 2014-12-17 | 爱思开海力士有限公司 | Isolation structure and method for forming the same, and image sensor including the isolation structure and method for fabricating the image sensor |
| CN103824805A (en) * | 2014-03-11 | 2014-05-28 | 武汉新芯集成电路制造有限公司 | Rear surface isolation device and preparation method thereof |
| US9559134B2 (en) * | 2014-12-09 | 2017-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Deep trench spacing isolation for complementary metal-oxide-semiconductor (CMOS) image sensors |
| CN107039471A (en) * | 2015-11-16 | 2017-08-11 | 台湾积体电路制造股份有限公司 | Imaging sensor and its manufacture method |
| CN107123658A (en) * | 2016-02-25 | 2017-09-01 | 台湾积体电路制造股份有限公司 | Semiconductor image sensor part and its manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109638026A (en) | 2019-04-16 |
| TWI645554B (en) | 2018-12-21 |
| TW201916334A (en) | 2019-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109638026B (en) | Deep trench isolation structure of CMOS image sensor and manufacturing method thereof | |
| EP3224866B1 (en) | Monolithic integration techniques for fabricating photodetectors with transistors on same substrate | |
| KR101738248B1 (en) | Image sensor and fabricating the same | |
| TWI509781B (en) | Semiconductor device and method for fabricating the same | |
| US11869761B2 (en) | Back-side deep trench isolation structure for image sensor | |
| US20220384496A1 (en) | Back-side deep trench isolation structure for image sensor | |
| TW201344894A (en) | Semiconductor image sensor device and method | |
| TWI532159B (en) | Image sensor apparatus and method for manufacturing the same and image sensor array device | |
| CN106972037A (en) | Semiconductor devices and forming method thereof | |
| CN109148492A (en) | Optical sensing means | |
| TWI834935B (en) | Method for passivating full front-side deep trench isolation structure | |
| TWI796625B (en) | Integrated circuit, image sensor, and method of forming the same | |
| CN116013940B (en) | Method of forming image sensor device and semiconductor device | |
| US10497736B2 (en) | Backside illuminated image sensor | |
| TWI556423B (en) | Image sensor device and semiconductor structure | |
| CN114664875A (en) | Backside illuminated image sensor | |
| US20150206789A1 (en) | Method of modifying polysilicon layer through nitrogen incorporation for isolation structure | |
| KR20100076257A (en) | Semiconductor device and method for manufacturing the same | |
| US20090256224A1 (en) | Integrated circuit comprising mirrors buried at different depths | |
| CN107195646B (en) | Image sensor and manufacturing method thereof | |
| TWI796083B (en) | Image sensor and manufacturing method thereof | |
| KR100806786B1 (en) | Image Sensor and Manufacturing Method Thereof | |
| JP2006278690A (en) | Solid-state image pickup element and manufacturing method thereof | |
| KR20060077244A (en) | Cmos image sensor and method for manufacturing the same | |
| KR20080011550A (en) | Method for manufacturing a image sensor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20210111 Address after: Hsinchu Science Industrial Park, Taiwan, China Applicant after: Powerchip Technology Corp. Address before: Hsinchu Science Industrial Park, Taiwan, China Applicant before: Powerchip Technology Corp. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |