CN103824805A - Rear surface isolation device and preparation method thereof - Google Patents
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- CN103824805A CN103824805A CN201410087481.4A CN201410087481A CN103824805A CN 103824805 A CN103824805 A CN 103824805A CN 201410087481 A CN201410087481 A CN 201410087481A CN 103824805 A CN103824805 A CN 103824805A
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- 238000002955 isolation Methods 0.000 title claims abstract description 148
- 238000002360 preparation method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 239000000463 material Substances 0.000 claims description 23
- 230000004888 barrier function Effects 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims description 12
- 150000004706 metal oxides Chemical class 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229910052755 nonmetal Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000000945 filler Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract 2
- 239000000969 carrier Substances 0.000 abstract 1
- 239000002800 charge carrier Substances 0.000 description 8
- 230000005611 electricity Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000000007 visual effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000007170 pathology Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000035479 physiological effects, processes and functions Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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Abstract
The invention discloses a rear surface isolation device which comprises a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface opposite to the first surface and at least comprises two device unit regions and isolation regions; each isolation region is positioned between each two adjacent device unit regions; the first surface in each isolation region is provided with a first isolation structure; the second surface in each isolation region is provided with a second isolation structure. Furthermore, the invention also provides a preparation method for the rear surface isolation device. By the adoption of the rear surface isolation device disclosed by the invention, the second isolation structures can effectively prevent charge current carriers in one device unit region from flowing into another device unit region adjacent to the device unit region, so that electric crosstalk between each two adjacent devices can be alleviated or avoided, and the electrical property of the device is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of back side isolated device and preparation method thereof.
Background technology
Imageing sensor grows up on photoelectric technology basis, and so-called imageing sensor can be experienced exactly optical image information and convert thereof into the transducer of exportable signal.Imageing sensor can improve the visual range of human eye, the microcosmos and the macrocosm that make people see that naked eyes cannot be seen, see that people temporarily cannot arrival place occurrence, see the various physics, the chemical change process that exceed naked eyes visual range, the generation evolution of life, physiology, pathology, etc.Visual picture transducer plays very important effect in people's culture, physical culture, production, life and scientific research.Can say, modern humans's activity cannot have been left imageing sensor.
The principle that imageing sensor can adopt according to it and divide into charge coupled device (Charge-Coupled Device) imageing sensor (that is being commonly called as ccd image sensor) and CMOS (Complementary Metal Oxide Semiconductor) imageing sensor, wherein cmos image sensor is manufactured based on CMOS (Complementary Metal Oxide Semiconductor) (CMOS) technology.Because cmos image sensor is to adopt traditional cmos circuit technique to make, therefore can by imageing sensor with and needed peripheral circuit integrated, thereby make cmos image sensor there is wider application prospect.
According to the difference of the position of reception light, cmos image sensor can be divided into front according to the cmos image sensor of formula and the cmos image sensor of back-illuminated type.But, no matter be front according to the cmos image sensor of formula or the cmos image sensor of back-illuminated type, crosstalking is the serious problems in imageing sensor.Conventionally there is crosstalking of three kinds of compositions: a) electricity is crosstalked, b) optical crosstalk, and c) frequency spectrum is crosstalked.Wherein, it is to produce in the time that the electric charge carrier generating in a pixel at imageing sensor is collected by the neighbor of imageing sensor that electricity is crosstalked, and has a strong impact on the image quality of imageing sensor.
Therefore, how to provide a kind of back side isolated device and preparation method thereof, can reduce or avoid the electricity between adjacent pixel to crosstalk, become the problem that those skilled in the art need to solve.
Summary of the invention
The object of the invention is to, a kind of back side isolated device and preparation method thereof is provided, can reduce or avoid the electricity between adjacent device to crosstalk.
For solving the problems of the technologies described above, the invention provides a kind of back side isolated device, comprising:
Semiconductor base, described semiconductor base has first surface and second surface on the other side;
Described semiconductor base comprises at least two device cell regions and area of isolation, and described area of isolation is between adjacent described device cell region;
Described first surface in described area of isolation has the first isolation structure, and the described second surface in described area of isolation has the second isolation structure.
Further, in described back side isolated device, described the second isolation structure is deep groove isolation structure.
Further, in described back side isolated device, described the second isolation structure contacts described the first isolation structure.
Further, in described back side isolated device, the filler in described the second isolation structure is electronics barrier material, and described electronics barrier material is nonmetal oxide, non-impurity-doped polysilicon, nitride or metal oxide, wherein, the dielectric constant of described metal oxide is more than or equal to 20.
Further, in described back side isolated device, described electronics barrier material is silica, silicon nitride or the hafnium oxide of chemical vapour deposition (CVD) or boiler tube growth.
Further, in described back side isolated device, the degree of depth of described the second isolation structure is 0.5 μ m～4 μ m.
Further, in described back side isolated device, described the first isolation structure is shallow groove isolation structure or carrying out local oxide isolation structure.
Further, in described back side isolated device, described back side isolated device is imageing sensor.
According to another side of the present invention, the present invention also provides a kind of preparation method of back side isolated device, comprising:
Semiconductor base is provided, described semiconductor base has first surface and second surface on the other side, described semiconductor base comprises at least two device cell regions and area of isolation, described area of isolation is between adjacent described device cell region, and the described first surface in described area of isolation has the first isolation structure;
Described second surface in described area of isolation is prepared the second isolation structure.
Further, in the preparation method of described back side isolated device, the step that described described second surface in described area of isolation is prepared the second isolation structure comprises:
Prepare mask layer at described second surface;
Prepare mask pattern at described mask layer, described mask pattern is positioned at the described mask layer of described area of isolation;
Take described mask pattern as mask, described semiconductor base is carried out to etching, form a groove at the second surface of described semiconductor base;
In described groove, fill electronics barrier material;
Remove remaining described mask layer, form described the second isolation structure.
Further, in the preparation method of described back side isolated device, adopt high-aspect-ratio process technique in described groove, to fill electronics barrier material.
Further, in the preparation method of described back side isolated device, described electronics barrier material is nonmetal oxide, non-impurity-doped polysilicon, nitride or metal oxide, and wherein, the dielectric constant of described metal oxide is more than or equal to 20.
Further, in the preparation method of described back side isolated device, described electronics barrier material is silica, silicon nitride or the hafnium oxide of chemical vapour deposition (CVD) or boiler tube growth.
Further, in the preparation method of described back side isolated device, described the second isolation structure is deep groove isolation structure.
Further, in the preparation method of described back side isolated device, described the second isolation structure contacts described the first isolation structure.
Further, in the preparation method of described back side isolated device, the degree of depth of described the second isolation structure is 0.5 μ m～4 μ m.
Further, in the preparation method of described back side isolated device, described the first isolation structure is shallow groove isolation structure or carrying out local oxide isolation structure.
Further, in the preparation method of described back side isolated device, described back side isolated device is imageing sensor.
Compared with prior art, back side isolated device provided by the invention and preparation method thereof has the following advantages:
In back side isolated device provided by the invention, described first surface in described area of isolation has the first isolation structure, described second surface in described area of isolation has the second isolation structure, compared with prior art, described back side isolated device in use, described the second isolation structure can prevent that the electric charge carrier in described device cell region from flowing in adjacent described device cell region effectively, thereby can reduce or avoid the electricity between adjacent device to crosstalk, improve the electric property of device.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the back side isolated device in one embodiment of the invention;
Fig. 2 is the preparation method's of the back side isolated device in one embodiment of the invention flow chart;
Fig. 3 a-Fig. 3 f is the schematic diagram of device architecture in the preparation method of the back side isolated device in one embodiment of the invention.
Embodiment
Below in conjunction with schematic diagram, back side isolated device of the present invention and preparation method thereof is described in more detail, the preferred embodiments of the present invention are wherein represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the present invention is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, a kind of back side isolated device is provided, and comprising: semiconductor base, and described semiconductor base has first surface and second surface on the other side; Described semiconductor base comprises at least two device cell regions and area of isolation, and described area of isolation is between adjacent described device cell region; Described first surface in described area of isolation has the first isolation structure, and the described second surface in described area of isolation has the second isolation structure.Described back side isolated device in use, described the second isolation structure can prevent that the electric charge carrier in described device cell region from flowing in adjacent described device cell region effectively, thereby can reduce or avoid the electricity between adjacent device to crosstalk, improve the electric property of device.
In conjunction with above-mentioned core concept, the present invention also provides a kind of preparation method of back side isolated device, comprising:
Semiconductor base is provided, described semiconductor base has first surface and second surface on the other side, described semiconductor base comprises at least two device cell regions and area of isolation, described area of isolation is between adjacent described device cell region, and the described first surface in described area of isolation has the first isolation structure;
Described second surface in described area of isolation is prepared the second isolation structure.
Below please refer to the described back side isolated device that Fig. 1 describes one embodiment of the invention in detail, in the present embodiment, described back side isolated device is imageing sensor, and described imageing sensor can be front according to the imageing sensor of formula or the imageing sensor of back-illuminated type.
As shown in Figure 1, described back side isolated device comprises semiconductor base 100, and described semiconductor base 100 has first surface 101 and second surface on the other side 102.Wherein, described first surface 101 is generally the front of wafer, and described first surface 101 generally has the device architecture such as grid structure and interconnection structure, and described second surface 102 is generally the back side of wafer, this common practise that is this area, and therefore not to repeat here.
Described semiconductor base 100 comprises at least two device cell regions 110 and area of isolation 120, and described area of isolation 120 is between adjacent described device cell region 110.Described in each, device cell region 110 is for the preparation of a device cell, and in the present embodiment, described back side isolated device is imageing sensor, so, described in each, device cell region 110 is for the preparation of a pixel, this common practise that is this area, and therefore not to repeat here.Wherein, quantity and the arrangement mode in described device cell region 110 do not do special restriction, and in the present embodiment, multiple described pel arrays are arranged, so, described device cell region 110 arrayed.General, described semiconductor base 100 can also comprise the structures such as doped region.
Described first surface 101 in described area of isolation 120 has the first isolation structure 121, and the described second surface 102 in described area of isolation 120 has the second isolation structure 122.Wherein, described the first isolation structure 121 is for isolating the device architecture in adjacent described device cell region 110, and in the present embodiment, described the first isolation structure 121 is for by the isolation of neighbor.Preferably, described the first isolation structure 121 is shallow groove isolation structure (Shallow Trench Isolation is called for short STI) or carrying out local oxide isolation structure (LocalOxidation of Silicon is called for short LOCOS).
Preferably, described the second isolation structure 122 is deep groove isolation structure, and deep groove isolation structure is conducive to better isolate crosstalking of electric charge carrier between adjacent described device cell region 110.The degree of depth of described the second isolation structure 122 is larger, and the ability of anti-crosstalk is better, but the degree of depth of described the second isolation structure 122 is larger, and the preparation of described the second isolation structure 122 is more difficult.Preferably, the depth H of described the second isolation structure 122 is 0.5 μ m～4 μ m, for example, 1 μ m, 2 μ m, 3 μ m etc., still, it is 0.5 μ m～4 μ m that the depth H of described the second isolation structure 122 is not limited to, and can arrange as required.
Preferably, described the second isolation structure 122 contacts described the first isolation structure 121, make can isolate completely between adjacent described device cell region 110, make described in one electric charge carrier between device cell region 110 cannot enter in adjacent described device cell region 110, wherein, the width of described the second isolation structure 122 and described the first isolation structure 121 does not do concrete restriction, and the width of described the second isolation structure 122 can be greater than, be equal to or less than the width of described the first isolation structure 121.And, described the second isolation structure 122 can only contact the bottom of described the first isolation structure 121, and as shown in Figure 1, described the second isolation structure 122 can also contact bottom and the sidewall of described the first isolation structure 121, this is what it will be appreciated by those skilled in the art that, and therefore not to repeat here.
Filler in described the second isolation structure 122 is electronics barrier material, and described electronics barrier material can be nonmetal oxide, non-impurity-doped polysilicon, nitride or metal oxide, and wherein, the dielectric constant of described metal oxide is more than or equal to 20.Preferably, described electronics barrier material is silica (for example TEOS, HDP, the HARP of chemical vapour deposition (CVD) or boiler tube growth, this is the common practise of this area), silicon nitride or hafnium oxide etc., all can well isolate described electric charge carrier.
Illustrate the preparation method of back side isolated device in the present embodiment below in conjunction with Fig. 2 and Fig. 3 a-Fig. 3 f.Wherein, Fig. 2 is the preparation method's of the back side isolated device in one embodiment of the invention flow chart, and Fig. 3 a-Fig. 3 f is the schematic diagram of device architecture in the preparation method of the back side isolated device in one embodiment of the invention.
First, carry out step S11, semiconductor base 100 as above is provided, as shown in Figure 3 a, described semiconductor base 100 has first surface 101 and second surface on the other side 102, described semiconductor base 100 comprises at least two device cell regions 110 and area of isolation 120, and described area of isolation 120 is between adjacent described device cell region 110, and the described first surface 101 in described area of isolation 120 has the first isolation structure 120.In addition, on described first surface 101, can also comprise the device architecture such as grid structure and interconnection structure.
Carrying out between step S12, generally can also carry out reduction processing to described semiconductor base 100, this common practise that is this area, therefore not to repeat here.
Then, carry out step S12, the described second surface 102 in described area of isolation 120 is prepared the second isolation structure.Concrete, step S12 can comprise following sub-step:
Sub-step 1: prepare mask layer 200 at described second surface 102, as shown in Figure 3 b.The material of described mask layer 200 can be silicon dioxide or silicon nitride, and as hardmask, still, the material of described mask layer 200 can also be other mask material;
Sub-step 2: prepare mask pattern 210 at described mask layer 200, described mask pattern 210 is positioned at the described mask layer 200 of described area of isolation 120, as shown in Figure 3 c.Wherein, described mask pattern 210 can be prepared by photoetching process, this common practise that is this area, and therefore not to repeat here;
Sub-step 3: take described mask pattern 210 as mask, described semiconductor base 100 is carried out to etching, form a groove 122a at the second surface 102 of described semiconductor base 100, as shown in Figure 3 d.The general dry etching technology that adopts carries out etching, such as plasma etching etc.;
Sub-step 4: at the interior filling of described groove 122 electronics barrier material 330 as above, as shown in Figure 3 e.Preferably, adopt high-aspect-ratio process technique (high aspect ratio process, be called for short HARP) in described groove 122a, fill electronics barrier material 300, to guarantee good filling effect, but, be not limited to adopt high-aspect-ratio process technique to fill, can also adopt high density ion processes (high density plasma is called for short HDP) etc.;
Sub-step 5: remove remaining described mask layer 200, in this process, also together removed unnecessary described electronics barrier material 330, thereby formed described the second isolation structure 122, as shown in Fig. 3 f.
The described back side isolated device of the present embodiment in use, the described device cell region 110 that described the second isolation structure 122 is adjacent with the common isolation of described the first isolation structure 122, effectively prevent that the electric charge carrier in a described device cell region 110 from flowing in adjacent described device cell region 110, thereby can reduce or avoid the electricity between adjacent pixel to crosstalk, improve the Presentation Function of imageing sensor.
Preferred embodiment of the present invention is described above, but the present invention is not limited to above-described embodiment, for example, described back side isolated device is not limited to as imageing sensor, as long as need to be to the device architecture of isolating between device cell, all can adopt described the second isolation structure of the present invention to strengthen isolation; In addition, described step S12 is not limited to sub-step 1-sub-step 5, as long as can prepare described the second isolation structure, all within thought range of the present invention.
In sum, the invention provides a kind of back side isolated device and preparation method thereof, described back side isolated device comprises that semiconductor base comprises semiconductor base, and described semiconductor base has first surface and second surface on the other side; Described semiconductor base comprises at least two device cell regions and area of isolation, and described area of isolation is between adjacent described device cell region; Described first surface in described area of isolation has the first isolation structure, and the described second surface in described area of isolation has the second isolation structure.Compared with prior art, back side isolated device provided by the invention and preparation method thereof has the following advantages:
Back side isolated device provided by the invention in use, described the second isolation structure can prevent that the electric charge carrier in described device cell region from flowing in adjacent described device cell region effectively, thereby can reduce or avoid the electricity between adjacent device to crosstalk, improve the electric property of device.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (18)
1. a back side isolated device, comprising:
Semiconductor base, described semiconductor base has first surface and second surface on the other side;
Described semiconductor base comprises at least two device cell regions and area of isolation, and described area of isolation is between adjacent described device cell region;
Described first surface in described area of isolation has the first isolation structure, and the described second surface in described area of isolation has the second isolation structure.
2. back side isolated device as claimed in claim 1, is characterized in that, described the second isolation structure is deep groove isolation structure.
3. back side isolated device as claimed in claim 2, is characterized in that, described the second isolation structure contacts described the first isolation structure.
4. back side isolated device as claimed in claim 1, it is characterized in that, filler in described the second isolation structure is electronics barrier material, described electronics barrier material is nonmetal oxide, non-impurity-doped polysilicon, nitride or metal oxide, wherein, the dielectric constant of described metal oxide is more than or equal to 20.
5. back side isolated device as claimed in claim 4, is characterized in that, described electronics barrier material is silica, silicon nitride or the hafnium oxide of chemical vapour deposition (CVD) or boiler tube growth.
6. back side isolated device as claimed in claim 1, is characterized in that, the degree of depth of described the second isolation structure is 0.5 μ m～4 μ m.
7. back side isolated device as claimed in claim 1, is characterized in that, described the first isolation structure is shallow groove isolation structure or carrying out local oxide isolation structure.
8. back side isolated device as claimed in claim 1, is characterized in that, described back side isolated device is imageing sensor.
9. a preparation method for back side isolated device, comprising:
Semiconductor base is provided, described semiconductor base has first surface and second surface on the other side, described semiconductor base comprises at least two device cell regions and area of isolation, described area of isolation is between adjacent described device cell region, and the described first surface in described area of isolation has the first isolation structure;
Described second surface in described area of isolation is prepared the second isolation structure.
10. the preparation method of back side isolated device as claimed in claim 9, is characterized in that, the step that described described second surface in described area of isolation is prepared the second isolation structure comprises:
Prepare mask layer at described second surface;
Prepare mask pattern at described mask layer, described mask pattern is positioned at the described mask layer of described area of isolation;
Take described mask pattern as mask, described semiconductor base is carried out to etching, form a groove at the second surface of described semiconductor base;
In described groove, fill electronics barrier material;
Remove remaining described mask layer, form described the second isolation structure.
The preparation method of 11. back side isolated devices as claimed in claim 10, is characterized in that, adopts high-aspect-ratio process technique in described groove, to fill electronics barrier material.
The preparation method of 12. back side isolated devices as claimed in claim 10, it is characterized in that, described electronics barrier material is nonmetal oxide, non-impurity-doped polysilicon, nitride or metal oxide, and wherein, the dielectric constant of described metal oxide is more than or equal to 20.
The preparation method of 13. back side isolated devices as claimed in claim 10, is characterized in that, described electronics barrier material is silica, silicon nitride or the hafnium oxide of chemical vapour deposition (CVD) or boiler tube growth.
The preparation method of 14. back side isolated devices as claimed in claim 9, is characterized in that, described the second isolation structure is deep groove isolation structure.
The preparation method of 15. back side isolated devices as claimed in claim 9, is characterized in that, described the second isolation structure contacts described the first isolation structure.
The preparation method of 16. back side isolated devices as claimed in claim 9, is characterized in that, the degree of depth of described the second isolation structure is 0.5 μ m～4 μ m.
The preparation method of 17. back side isolated devices as claimed in claim 9, is characterized in that, described the first isolation structure is shallow groove isolation structure or carrying out local oxide isolation structure.
The preparation method of 18. back side isolated devices as claimed in claim 9, is characterized in that, described back side isolated device is imageing sensor.
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| CN109638026B (en) * | 2017-10-06 | 2021-03-12 | 力晶积成电子制造股份有限公司 | Deep trench isolation structure of CMOS image sensor and manufacturing method thereof |
| CN108281439A (en) * | 2018-01-23 | 2018-07-13 | 德淮半导体有限公司 | Imaging sensor and forming method thereof |
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