CN109637939A - The packaging method of semiconductor packaging mold, semiconductor devices and semiconductor devices - Google Patents
The packaging method of semiconductor packaging mold, semiconductor devices and semiconductor devices Download PDFInfo
- Publication number
- CN109637939A CN109637939A CN201710931404.6A CN201710931404A CN109637939A CN 109637939 A CN109637939 A CN 109637939A CN 201710931404 A CN201710931404 A CN 201710931404A CN 109637939 A CN109637939 A CN 109637939A
- Authority
- CN
- China
- Prior art keywords
- chip
- accommodating chamber
- encapsulating material
- semiconductor devices
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000000463 material Substances 0.000 claims abstract description 189
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000002347 injection Methods 0.000 claims abstract description 33
- 239000007924 injection Substances 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 238000012856 packing Methods 0.000 claims description 26
- 238000007669 thermal treatment Methods 0.000 claims description 2
- 241000208340 Araliaceae Species 0.000 claims 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 claims 1
- 235000003140 Panax quinquefolius Nutrition 0.000 claims 1
- 235000008434 ginseng Nutrition 0.000 claims 1
- 230000000694 effects Effects 0.000 description 21
- 238000010438 heat treatment Methods 0.000 description 10
- 239000003822 epoxy resin Substances 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 108060008539 Transglutaminase Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 102000003601 transglutaminase Human genes 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses the packaging methods of a kind of semiconductor packaging mold, semiconductor devices and semiconductor devices.Method for packaging semiconductor includes providing package substrate, and multiple chips are stacked in package substrate；Encapsulating mould is covered into chip, so that chip accommodating chamber is accommodated all chips, and the contour surface shape of the chip of the contour surface shape and stacking of chip accommodating chamber is adapted；By injection orifice to injecting encapsulating material inside chip accommodating chamber.The outer contour surface of chip accommodating chamber and stacked chips fits so that the encapsulating material thinner thickness that is subsequently formed and uniformly, avoids chip and warpage occurs for encapsulating material.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of semiconductor packaging mold, semiconductor devices and partly lead
The packaging method of body device.
Background technique
Currently, the appearance of chip 3D stack manner reduces occupied by chip two dimensional arrangement in the technique of chip package
Area.3D stacking is to fold chip stack to be placed on package substrate, is then packaged again.In the prior art, using having
The encapsulating mould of single rectangular chip accommodating chamber covers chip stack structure, is then packaged.
It is packaged using encapsulating mould in the prior art, after heat treatment solidifies encapsulating material, encapsulating material or core
Warpage easily occurs for piece, causes to remove between encapsulating material and chip, and then cannot chip effectively be encapsulated and be protected
Shield.
Therefore, the prior art needs one kind and is avoided that warpage, and then peeling-off encapsulation occur for encapsulating material or chip
Method.
Summary of the invention
The present invention provides the packaging methods of a kind of semiconductor packaging mold, semiconductor devices and semiconductor devices, effectively
The phenomenon that avoiding encapsulating material or warpage occur for chip, and then removing.
A kind of semiconductor packaging mold is provided in technical solution of the present invention, comprising: shell allows the core of multiple stackings
The opening that piece passes through；The chip of the chip accommodating chamber being set in shell, the profile of chip accommodating chamber and multiple stackings is adapted,
At least one shape along the section of the depth direction of chip accommodating chamber of the profile of chip accommodating chamber includes corresponding with opening
Bottom edge, top margin corresponding with chip accommodating chamber top and the two sides for being separately connected bottom edge corresponding endpoint with top margin, top margin
Length be less than bottom edge length.
According to an aspect of the present invention, from bottom edge to top margin, the length that two sides are parallel to the line on bottom edge reduces.
According to an aspect of the present invention, at least one side is in step-like.
According to an aspect of the present invention, further includes: injection orifice, injection orifice runs through shell, and connects chip accommodating chamber.
According to an aspect of the present invention, injection orifice is set to the top of shell, connects the top of chip accommodating chamber.
According to an aspect of the present invention, when the chip of multiple stackings is accommodated in chip accommodating chamber, chip is accommodated
The depth direction of chamber is consistent with the stacking direction of the chip of multiple stackings.
According to an aspect of the present invention, the chip of multiple stackings can be accommodated in chip accommodating chamber by opening.
Technical solution of the present invention provides a kind of semiconductor devices, comprising: package substrate；It is stacked in the more of package substrate
A chip；Encapsulating material, encapsulating material cover the outer contour surface of the chip of multiple stackings, the outer profile of encapsulating material at least one
The shape in the section of a chip stacking direction along multiple stackings includes bottom edge corresponding with package substrate surface and package material
The corresponding top margin in material top and the two sides for being separately connected bottom edge endpoint corresponding with top margin, the length of top margin are less than bottom edge
Length.
According to an aspect of the present invention, from bottom edge to top margin, the length that two sides are parallel to the line on bottom edge reduces.
According to an aspect of the present invention, at least one side is in step-like.
According to an aspect of the present invention, the distance between the corresponding position on encapsulating material surface and chip outer contour surface
For the thickness of encapsulating material.
According to an aspect of the present invention, thickness range is 0.5mm~1.5mm.
According to an aspect of the present invention, further includes: packing material and metal interconnection structure, packing material and metal interconnection
Structure is between package substrate and the chip adjacent with package substrate and between adjacent chip.
According to an aspect of the present invention, the width dimensions of at least two chips are different.
According to an aspect of the present invention, the width dimensions of upper layer chip are less than or equal to the width of lower layer chip adjacent thereto
Spend size.
According to an aspect of the present invention, side of the edge of upper layer chip without departing from lower layer chip adjacent thereto
Edge.
The present invention also provides a kind of packaging methods of semiconductor devices, comprising: provides package substrate, multiple chips stack
In package substrate；Previously described any semiconductor packaging mold is provided；Encapsulating mould is covered into chip, accommodates chip
Chamber accommodates the chip of multiple stackings, and the chip of the chamfered shape of chip accommodating chamber and stacking is adapted；By injection orifice to core
Encapsulating material is injected inside piece accommodating chamber.
According to an aspect of the present invention, between the contour surface of chip accommodating chamber and corresponding chip outer contour surface
Distance range is 0.5mm~1.5mm.
According to an aspect of the present invention, the width dimensions of at least two chips are different.
According to an aspect of the present invention, the width dimensions of upper layer chip are less than or equal to the width of lower layer chip adjacent thereto
Spend size.
According to an aspect of the present invention, side of the edge of upper layer chip without departing from lower layer chip adjacent thereto
Edge.
According to an aspect of the present invention, injection orifice runs through shell, and is connected with chip accommodating chamber.
According to an aspect of the present invention, injection orifice is set to the top of shell, and is connected with the top of chip accommodating chamber.
According to an aspect of the present invention, further includes: connect two adjacent chips and connection with metal interconnection structure
Package substrate and the chip adjacent with package substrate；It is infused in gap between chip and package substrate and between adjacent chips
Enter packing material, packing material covers metal interconnection structure.
According to an aspect of the present invention, after injecting encapsulating material, further includes: be heat-treated to encapsulating material.
According to an aspect of the present invention, it is 170 DEG C~300 DEG C that process of thermal treatment parameter, which includes: temperature, and the time is
90s~220s.
Compared with prior art, the advantages of technical solution of the embodiment of the present invention has is as follows:
In the semiconductor packaging mold that technical solution of the present invention provides, the profile of chip accommodating chamber and multiple stackings
Chip is adapted.This design is so that chip accommodating chamber profile is closer with chip surface, so that finally formed package material
A possibility that expecting that thickness is smaller, reducing encapsulating material and peeling-off chip.
Further, at least one side in chip accommodating chamber section is in step-like.This ensure that chip accommodating chamber
It fits with chip surface, further reduces the thickness of encapsulating material.
The present invention also provides semiconductor devices, the outer contour surface for the chip that encapsulating material covering stacks, encapsulating material
Outer profile at least one shape along the section of the chip stacking direction of multiple stackings include corresponding with package substrate surface
Bottom edge, with corresponding top margin at the top of encapsulating material and be separately connected the two sides of bottom edge corresponding endpoint with top margin, top margin
Length be less than bottom edge length.Encapsulating material with this shape reduces the thickness of encapsulating material, reduces package material
A possibility that material is peeling-off with chip.
Further, the thickness range of encapsulating material is 0.5mm~1.5mm.The thickness of encapsulating material is smaller, so that solid
The volume change generated during changing is also smaller, avoids encapsulating material peeling-off with chip.
The present invention also provides the packaging method of semiconductor devices, the chip phases of the chamfered shape and stacking of chip accommodating chamber
It adapts to.This design so that the profile of chip accommodating chamber and the surface distance of chip are closer, the encapsulating material thickness of formation compared with
It is small, and then avoid because the volume expansion of heat treatment process encapsulating material is excessive, so that chip is peeling-off with encapsulating material.
Detailed description of the invention
Fig. 1-Fig. 4 is semiconductor packaging mold, semiconductor devices and semiconductor device according to an embodiment of the invention
The schematic diagram of the section structure of the packaging method of part；
Figure 5-8 is semiconductor packaging mold, semiconductor devices and semiconductor in accordance with another embodiment of the present invention
The schematic diagram of the section structure of the packaging method of device；
Fig. 9-Figure 11 is the semiconductor packaging mold, semiconductor devices and semiconductor of another embodiment according to the present invention
The schematic diagram of the section structure of the packaging method of device；
Figure 12-Figure 14 is the semiconductor packaging mold, semiconductor devices of further embodiment and partly to lead according to the present invention
The schematic diagram of the section structure of the packaging method of body device.
Specific embodiment
As previously mentioned, existing encapsulation technology encapsulating material is chip surface can there is a phenomenon where warpages, and then lead
The problem for causing the two peeling-off.
It has been investigated that the reason of causing the above problem are as follows: using the encapsulating mould with single rectangular chip accommodating chamber
It is packaged, there are biggish remaining space between the profile of chip accommodating chamber and the chip of stacking, in final semiconductor devices
Encapsulating material is more, thicker.Due to the difference of encapsulating material and chip CTE, in heat treatment, more, thicker envelope
Package material volume expansion and expansion rate after heated is larger, and chip volume expansion and expansion rate are smaller, finally lead
It causes encapsulating material that warpage occurs in chip surface, and then causes peeling-off between the two.
In order to solve this problem, the present invention provides a kind of method for packaging semiconductor, encapsulating mould chip accommodating chamber and heaps
The surface of folded chip fits, and reduces the quantity of encapsulating material in semiconductor devices, and after heat treatment, less encapsulating material produces
Raw lesser volume expansion amount is allowed to be adapted with the amount that chip expands, avoids that warpage occurs between encapsulating material and chip
With removing.
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should be understood that unless in addition specific
Illustrate, the component and the positioned opposite of step, numerical expression and numerical value otherwise illustrated in these embodiments is not understood that
For limitation of the scope of the invention.
In addition, it should be understood that for ease of description, the size of all parts shown in attached drawing is not necessarily according to reality
The proportionate relationship on border is drawn, such as certain layers of thickness or width can be exaggerated relative to other layers.
The description of exemplary embodiment is merely illustrative below, in any sense all not as to the present invention and
Its any restrictions applied or used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of these technologies, method and apparatus, these technologies, method and apparatus should be considered as a part of this specification.
It should be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined or illustrates in attached drawing, then will not need that it is further discussed in the explanation of subsequent attached drawing.
First embodiment.
Referring to FIG. 1, multiple chips 130 are stacked in package substrate 100.
Package substrate 100 plays the role of to support, protection chip 130.The material of package substrate 100 includes but unlimited
In: epoxy resin, polyimides etc..Specifically, in embodiments of the present invention, the material of package substrate 100 is epoxy resin.
The shape of chip 130 be it is rectangular, round etc., be not specifically limited herein.Specifically, in the embodiment of the present invention
In, the shape of chip 130 is rectangular.The basis material of chip 130 is silicon.
Each chip 130 includes opposite first surface and second surface.Specifically, in embodiments of the present invention, the
One surface refers to that the top surface of each chip 130, second surface refer to the bottom surface of each chip 130.
It should be noted that the number of the chip 130 stacked is not specifically limited.The direction that chip 130 stacks is in Fig. 1
Shown in arrow direction.Specifically, in embodiments of the present invention, the number of the chip 130 of stacking is 3, it is respectively from bottom to top
130a, 130b, 130c.
In the chip 130 of stacking, the width dimensions of at least two chips 130 are different, and the broad-ruler of upper layer chip 130
The very little width dimensions less than or equal to lower layer chip 130 adjacent thereto.In embodiments of the present invention, the size of chip 130 is complete
It is different.When various sizes of chip 130 is stacked on package substrate 100, the chip 130 of relatively large width dimensions is under
Side, above, i.e. the width dimensions of chip 130a, 130b, 130c are sequentially reduced the chip 130 of relatively small width dimensions.And
And in embodiments of the present invention, edge of the edge of upper layer chip 130 without departing from adjacent lower chip 130.Meanwhile institute
There is the surface keeping parallelism of the corresponding side wall of chip 130.
Again because 130 width dimensions of chip are different, so that rank is presented in the outer contour surface of at least side of chip 130 stacked
Scalariform.Specifically, in embodiments of the present invention, the 130 two sides outer contour surface of chip of stacking presents ladder-like.Herein, it needs
It is noted that the outer profile of chip 130 refers to that chip 130 is exposed to external surface after being stacked, and it is subsequent will be in core
Encapsulating material is formed on the outer profile of piece 130.The meaning of the chip outer profile hereinafter stacked is identical as meaning herein.
It in embodiments of the present invention, further include metal interconnection structure 120.The purpose of metal interconnection structure 120 is to connect
Two adjacent chips 130, and connection package substrate 100 and the chip 130 adjacent with package substrate 100, to reach core
The purpose that piece is connected to chip, chip with package substrate, and then realize the specific function of entire semiconductor devices.
In embodiments of the present invention, the chip adjacent with package substrate 100 is 130a, so chip 130a and package substrate
It include metal interconnection structure 120, the second table of the first surface of lower layer chip 130 upper layer chip 130 adjacent thereto between 100
Also include metal interconnection structure 120 between face, is i.e. also includes metal interconnection structure between 130b and 130c between 130a and 130b
120。
It should be noted that the tie point of metal interconnection structure 120 and chip 130 is related with the specific structure of chip 130,
So the embodiment of the present invention is not specifically limited the number of metal interconnection structure 120 with position.
Metal interconnection structure 120 includes: copper wire, tin ball etc..Specifically, in embodiments of the present invention, metal interconnection structure
120 be copper wire.
In embodiments of the present invention, in the gap between adjacent chips 130 and chip 130a and package substrate 100 it
Between gap in further include packing material 110.
The effect of packing material 110 is adjacent chips 130, package substrate 100 and the core adjacent with package substrate 100
Piece 130 is adhesively fixed, and prevents semiconductor devices from sliding or dislocation occurs.In embodiments of the present invention, packing material 110 will also be golden
Belong to interconnection structure 120 to cover, to also act as the effect of protection metal interconnection structure 120.
In embodiments of the present invention, the size phase of the area of each layer of packing material 110 and adjacent upper chip 130
It adapts to.
Referring to FIG. 2, the chip 130 that the covering of encapsulating mould 140 is stacked.
The chip 130 that the covering of encapsulating mould 140 stacks is to be subsequently stuffed into encapsulating material.Chip accommodating chamber accommodates all
Chip 130, the profile of the chip accommodating chamber of encapsulating mould 140 and the chip 130 of stacking are adapted.
Specifically, in embodiments of the present invention, being adapted outside the chip accommodating chamber for referring to encapsulating mould 140 and chip 130
The distance between contour surface is closer, can reduce the dosage of subsequent encapsulating material.Hereinafter the profile of chip accommodating chamber with
The adaptable meaning of the chip of stacking is identical as meaning herein.
Encapsulating material area 150 is after encapsulating mould 140 covers stacked chips 130, and the distance between chip 130 is used for
Subsequent filling encapsulating material.
Referring to FIG. 3, injecting encapsulating material 151 to encapsulating material area 150 by injection orifice 146.
Encapsulating material 151 plays the role of protecting stacked structure.The material of encapsulating material 151 includes: epoxy resin, modification
Epoxy resin etc..Specifically, in embodiments of the present invention, the material of encapsulating material 151 is modified epoxy resin.With do not change
The epoxy resin of property is compared, and modified epoxy resin reduces the thermal expansion coefficient of encapsulating material 151 to a certain extent
(Coefficient of Thermal Expansion, CTE), reduces the difference of CTE between encapsulating material 151 and chip 130
It is different, the generation of chip 130 Yu 151 peeling of encapsulating material can be prevented to a certain extent.
Herein, it should be noted that in other embodiments of the invention, encapsulating material 151 can also be other materials
Material, as long as not influencing the condition of performance of semiconductor device after meeting encapsulation.
It in embodiments of the present invention, further include being heat-treated to encapsulating material 151 after injecting encapsulating material 151.At heat
Managing encapsulating material 151 is to make 151 curing molding of encapsulating material.The process conditions for being heat-treated encapsulating material 151 will be according to it
Type determines.Specifically, in embodiments of the present invention, the technological parameter of heat treatment encapsulating material 151 includes: that temperature range is
170 DEG C~300 DEG C (herein, temperature is to be less than or equal to 300 DEG C, i.e. range includes endpoint value, subsequent more than or equal to 170 DEG C
Range table predicate meaning herein it is identical), time range is 90s~220s.Such as in one embodiment of the invention, at heat
Managing temperature is 190 DEG C, heat treatment time 200s.
Correspondingly, with continued reference to FIG. 3, the present invention provides semiconductor devices, comprising: package substrate 100 is stacked in envelope
Fill multiple chips 130, packing material 110, metal interconnection structure 120 and the encapsulating material 151 of substrate 100.
In the chip 130 of stacking, the width dimensions of at least two chips 130 are different.And the broad-ruler of upper layer chip 130
The very little width dimensions less than or equal to lower layer chip 130 adjacent thereto.The edge of upper layer chip 130 is without departing from adjacent thereto
Lower layer chip 130 edge.The surface keeping parallelism of the corresponding side wall of all chips 130.In embodiments of the present invention, heap
Folded chip 130 shares 3, is respectively from bottom to top: chip 130a, chip 130b, chip 130c, and chip 130a,
The size of 130b, 130c are sequentially reduced.130 outer contour surface of chip of stacking is in step-like.
Packing material 110 and metal interconnection structure 120 between adjacent chips 130 and package substrate 100 and with envelope
It fills between the adjacent chip 130 of substrate 100, and packing material 110 covers metal interconnection structure 120.
Encapsulating material 151 covers the outer contour surface of stacked chips 130, at least one edge of the outer profile of encapsulating material 151
The shape in the section of multiple chip stacking directions includes that bottom edge corresponding with 100 surface of package substrate and encapsulating material 151 push up
The corresponding top margin in portion and the two sides for being separately connected bottom edge endpoint corresponding with top margin, the length of top margin are less than the length on bottom edge
Degree.
From bottom edge to top margin, the length that two sides are parallel to the line on bottom edge reduces the profile of encapsulating material 151.
Correspondingly, referring to FIG. 4, the embodiment of the invention also provides semiconductor packaging molds 140.
The effect of encapsulating mould 140 is covering stacked structure, to make encapsulating material to its type intracavitary administration encapsulating material
Molding.
Encapsulating mould 140 includes shell 141, the opening 142 for allowing the chip of multiple stackings to pass through, is located in shell 141
Chip accommodating chamber 143 and injection orifice 146.
Opening 142 enables the chip to can smoothly enter into inside chip accommodating chamber 143.After mold 140 covers chip, Suo Youxin
Piece is located at the inside of chip accommodating chamber 143.
The profile of chip accommodating chamber 143 and the chip of multiple stackings are adapted.Herein, it is adapted and refers to chip accommodating chamber
The distance between the outer contour surface of 143 profile and stacked chips is closer.
At least one shape along the section of 143 depth direction of chip accommodating chamber of the profile of chip accommodating chamber 143 include with
Be open 142 corresponding bottom edges, with 144 corresponding top margins at the top of chip accommodating chamber and to be separately connected bottom edge corresponding with top margin
The side 145a and 145b of endpoint.Significantly the bottom edge of chip accommodating chamber 143, top margin and side 145a and 145b are collectively formed
The profile of chip accommodating chamber 143.
Herein, it should be noted that the depth of chip accommodating chamber 143 is d, and the depth direction of chip accommodating chamber 143 is such as
Shown in Fig. 4.And in embodiments of the present invention, the length of top margin is less than the length on bottom edge.
145a and 145b constitute the shape of 143 outline of chip accommodating chamber for side.And from bottom edge to top margin, side
The length that 145a and 145b is parallel to the line on bottom edge reduces.From bottom edge to top margin, side 145a and 145b are parallel to bottom edge
The length of line is respectively l1、l2And l3, it will be apparent that, in embodiments of the present invention, l1> l2> l3。
The effect of injection orifice 146 is to be subsequent to 143 internal injection encapsulating material of type chamber.Injection orifice 146 runs through shell
141, and be connected with chip accommodating chamber 143.Since encapsulating material is liquid, so in the present invention is implemented, injection orifice 146 is set
It is placed in the top 147 of shell 141, and is connected with the top of chip accommodating chamber 143 144.Setting injection orifice 146 is in this way convenient for envelope
Package material flows downward naturally, covers the surface of entire stacked chips.
Herein, it should be noted that size, the shape of injection orifice 146 are not specifically limited.
Second embodiment.
Second embodiment and first embodiment the difference is that, the chip accommodating chamber chamfered shape of encapsulating mould is not
Together, the positional relationship between other positions and position is consistent with first embodiment.
Referring to FIG. 5, the chip 230 that the covering of encapsulating mould 240 is stacked.
Package substrate 200, metal interconnection structure 210, the effect of packing material 220 and positional relationship are implemented with first
Example is consistent, and this will not be repeated here.
Shape, stack manner, positional relationship and the width dimensions size of chip 230 please refer to first embodiment.
The chip 230 that the covering of encapsulating mould 240 stacks is to be subsequently stuffed into encapsulating material.Chip accommodating chamber accommodates all
Chip 230, the profile of the chip accommodating chamber of encapsulating mould 240 and the chip 230 of stacking are adapted.
Specifically, in embodiments of the present invention, the profile of 240 chip accommodating chamber of encapsulating mould and the chip outer profile of stacking
Surface fits.Herein, it fits outside the chip 230 of the chamfered shape and stacking that refer to 240 chip accommodating chamber of encapsulating mould
Contour surface shape is adapted, and it is not Encapsulation Moulds that the profile of chip accommodating chamber and 230 surface distance of chip of stacking are closer
Have the profile of 240 chip accommodating chambers and 230 intimate surface contact of chip of stacking.
Encapsulating material area 250 is that the profile of 240 chip accommodating chamber of encapsulating mould and the chip outer contour surface of stacking are affixed
Space after conjunction, between the profile of chip accommodating chamber and the chip outer contour surface of stacking.Encapsulating material area 250 is subsequent filling
The space of encapsulating material.It will be evident that due to fitting above-mentioned, encapsulating material area 250 is relatively narrow, so the package material after subsequent forming
The thickness of material is smaller, negligible amounts.
Specifically, in embodiments of the present invention, the range of the width s in encapsulating material area 250 is 0.5mm~1.5mm, and
And the width in encapsulating material area 250 is uniform.
Herein, it should be noted that due to existing between chip accommodating chamber profile and the contour surface of stacked chips 230
Certain space, i.e. encapsulating material area 250.So encapsulating mould 240 have in the chip 230 that covering stacks certain activity away from
From in actual production process, the width for being extremely difficult to 250 different parts of encapsulating material area is uniform.So herein uniformly
Referring to the numerical value that the width in encapsulating material area 250 is substantially secured between 0.5mm~1.5mm, error is no more than 5%, after
Continuous uniform statement is identical as meaning herein.As in one embodiment of the invention, the width s in encapsulating material area 250 is solid
It is scheduled on 1mm, maximum distance is no more than 1.05mm, and minimum range is not less than 0.95mm.
Referring to FIG. 6, injecting encapsulating material 251 to encapsulating material area 250 by injection orifice 246.
The effect of encapsulating material 251, position, the selection of material and subsequent heat treatment technique with first embodiment one
It causes.
Referring to FIG. 7, obtaining semiconductor devices after removing encapsulating mould after cure package material 251.
In general, 70≤γ≤80 thermal expansion coefficient (CTE) of encapsulating material 251, and the thermal expansion coefficient γ of chip 230
≤20.There are larger differences by thermal expansion coefficient γ between encapsulating material 251 and chip 230.During heat treatment, package material
Material 251 is different from the volume expansion size or expansion rate of chip 230, leads to solidify post package material 251 in 230 table of chip
Warpage occurs for face, and then occurs the phenomenon that removing between the two, the chip 230 being unable in effective protection semiconductor devices.
In general, when the quantity of semiconductor device surface encapsulating material 251 is fewer, encapsulating material during heat treatment
251 from chip 230 because thermal expansion coefficient is different generate the difference of volume expansion size or expansion rate will be smaller.Therefore
The amount for reducing encapsulating material 251 can effectively avoid encapsulating material 251 and chip 230 that warpage occurs, and then occur removing shows
As.Specifically, in embodiments of the present invention, the profile of the chip accommodating chamber of encapsulating mould 240 and 230 outer profile of chip of stacking
The fitting on surface so that the width in encapsulating material area 150 reduces, and then reduces the amount of encapsulating material 251, what encapsulating material 251 became
It is thinner and more evenly.
If the thickness h of encapsulating material 251 is blocked up, foregoing chip 230 will often occur and shelled with encapsulating material 251
From the phenomenon that.If the thickness h of encapsulating material is too small, such as thickness h < 0.5mm, after subsequent treatment process is easily destroyed solidification
Encapsulating material 251, exposure chip 230, and then keep chip 230 damaged, influence the electric property of semiconductor devices.
As previously mentioned, in embodiments of the present invention, due to the range of the width s in encapsulating material area 150 be 0.5mm~
1.5mm, therefore the range of the thickness h of the encapsulating material 251 after subsequent forming is also 0.5mm~1.5mm, and thickness is uniform.
As in one embodiment of the invention, encapsulating material thickness h=1mm, thickness h error is no more than 5% everywhere, such as preceding institute
It states.Herein, the thickness of encapsulating material refers to the distance between the corresponding position on encapsulating material surface Yu chip outer contour surface.
In conclusion in the second embodiment of the present invention, the profile and stacking core of the chip accommodating chamber of encapsulating mould 240
The outer contour surface of piece 230 fits, and reduces the width s in encapsulating material area 250, reduces the thickness h of encapsulating material 251, reduces
The amount of encapsulating material 251.After heat treatment, avoids volume expansion size occur because of thermal expansion coefficient difference or expansion rate is poor
Different phenomenon prevents solidification post package material 251 from warpage occurs, and then encapsulating material 251 occurs and show with what chip 230 was removed
As.
Correspondingly, with continued reference to FIG. 7, the present invention provides semiconductor devices, comprising: package substrate 200 is stacked in envelope
Fill multiple chips 230, packing material 210, metal interconnection structure 220 and the encapsulating material 251 of substrate 200.
In the chip 230 of stacking, the stack manner of chip 230, width dimensions size are consistent with first embodiment,
This is not repeated them here.
Packing material 210 and metal interconnection structure 220 between adjacent chips 230 and package substrate 200 and with envelope
It fills between the adjacent chip 230 of substrate 200, and packing material 210 covers metal interconnection structure 220.
Encapsulating material 251 covers the outer contour surface of stacked chips 230, at least one edge of the outer profile of encapsulating material 251
The shape in the section of multiple stacked chips stacking directions includes bottom edge corresponding with 200 surface of package substrate and encapsulating material
The corresponding top margin in 251 tops and the two sides for being separately connected bottom edge endpoint corresponding with top margin, the length of top margin are less than bottom edge
Length.
From bottom edge to top margin, the length that two sides are parallel to the line on bottom edge reduces the profile of encapsulating material 251.And two sides
At least one side is in step-like in side.Specifically, in embodiments of the present invention, two sides of 251 profile of encapsulating material are equal
In step-like.The top and bottom of semiconductor devices, as shown in Figure 7.
In embodiments of the present invention, the thickness of encapsulating material 251 is uniform, and the range of thickness h is 0.5mm~1.5mm, thickness
Error is as previously described.
In conclusion being bonded for encapsulating material 251 and the outer contour surface of stacked chips 230, reduces encapsulating material
Amount, keeps encapsulating material thickness relatively thin, can effectively avoid 230 encapsulating material 251 of chip after solidification that warpage occurs.
Correspondingly, referring to FIG. 8, the embodiment of the invention also provides semiconductor packaging molds 240.
The effect of encapsulating mould 240 is covering stacked structure, to make encapsulating material to its type intracavitary administration encapsulating material
Molding.
The effect of encapsulating mould 240 please refers to first embodiment.Encapsulating mould 240 includes: shell 241, opening 242, core
The top 247 of 244, side 245a and 245b, aperture 246 and encapsulating mould 240 at the top of piece accommodating chamber 243, chip accommodating chamber.
Its effect please refers to first embodiment.
245a and 245b constitute the shape of 243 outline of chip accommodating chamber for side.And from bottom edge to top margin, side
The length that 245a and 245b is parallel to the line on bottom edge reduces.From bottom edge to top margin, side 245a and 245b are parallel to bottom edge
The length of line is respectively l1、l2And l3, it will be apparent that, in embodiments of the present invention, l1> l2> l3。
At least one side is in step-like in side 245.Specifically, in embodiments of the present invention, two side 245a with
245b is in step-like.
The effect of injection orifice 246 please refers to first embodiment.
3rd embodiment.
3rd embodiment and second embodiment the difference is that the chamfered shape of encapsulating mould chip accommodating chamber and
The stack manner of chip.Encapsulating mould chip accommodating chamber is plane in the cross-section profile shape side of depth direction, is stacked simultaneously
All chip-side faces keep concordant.The effect of the other component of 3rd embodiment, positional relationship please refer to second embodiment.
Referring to FIG. 9, multiple chips 330 are stacked in package substrate 300.
The effect of package substrate 300, material are consistent with second embodiment, and this will not be repeated here.
Chip 330 is stacked on package substrate 300.Between effect that chip 330 stacks, different chip 330 and chip
Connection type between 330 and package substrate 300 is consistent with second embodiment, and therefore not to repeat here.
In embodiments of the present invention, the chip 330 of different width dimensions is when stacking, the corresponding side of all chips 330
Keep concordant, i.e., in embodiments of the present invention, chip 330a, 330b are concordant with the corresponding side holding of 330c.Chip 330 other
The stacking shape at position is consistent with second embodiment.
In the embodiment of the present invention, further includes: packing material 310 and metal interconnection structure 320.The effect of the two, position are closed
It is and consistent with second embodiment with the positional relationship of other component, this will not be repeated here.
Referring to FIG. 10, multiple chips 330 that the covering of encapsulating mould 340 is stacked.
The profile of 340 chip accommodating chamber of encapsulating mould and the chip 330 of stacking are adapted, such as second embodiment, herein not
It repeats.Likewise, the profile of 240 chip accommodating chamber of encapsulating mould and 330 outer contour surface of chip of stacking fit.
It will be evident that in embodiments of the present invention, a side of the chip accommodating chamber of encapsulating mould 340 is plane, with core
The concordant side that piece 330 stacks is adapted.The profile of chip accommodating chamber is at a distance from 330 outer contour surface of chip of stacking, i.e.,
The width in encapsulating material area please refers to second embodiment.
It further include that encapsulating material 351 is injected to encapsulating material area by injection orifice 346 in the embodiment of the present invention.Injection orifice
346 effect, position are consistent with second embodiment, and this will not be detailed here.
The technological parameter of cure package material 351 please refers to second embodiment, and I will not elaborate.Solidify post package material
351 thickness is consistent with second embodiment, and which is not described herein again.
Correspondingly, with continued reference to FIG. 10, the embodiment of the invention provides semiconductor devices, comprising: package substrate 300,
Packing material 310, metal interconnection structure 320, the multiple chips 330 and encapsulating material 351 for being stacked in package substrate 300.
The width dimensions size of chip 330 please refers to second embodiment.In embodiments of the present invention, different chip 330
Corresponding side keeps concordant.It will be evident that other contour surfaces presentation of different chips 330 is step-like.
The positional relationship of packing material 310 and metal interconnection structure 320 is consistent with second embodiment.
Encapsulating material 351 fits over the outer contour surface of stacked chips 330.The effect of encapsulating material 351, thickness with
Second embodiment is consistent, and this will not be repeated here.
Correspondingly, please referring to Figure 11, the present invention also provides semiconductor packaging molds 340, comprising: shell 341, permission are more
Opening 342, chip accommodating chamber 343 and the injection orifice 346 that a stacked chips pass through.
In embodiments of the present invention, since encapsulating mould 340 will cover the chip 330 of stacking, so encapsulating mould 340
The chamfered shape of chip accommodating chamber 330 also accordingly changes, and the chip accommodating chamber 330 of encapsulating mould 340 is along its depth direction
The side of the profile of upper section is plane.
It should be noted that the profile of 340 chip accommodating chamber 330 of encapsulating mould at least one along the section of depth direction
Shape include with 342 corresponding bottom edges of opening, with chip accommodating chamber 344 corresponding top margins of top and be separately connected bottom edge
The side 345a and 345b of endpoint corresponding with top margin.And from bottom edge to top margin, side 345a and 345b is parallel to the line on bottom edge
Length reduces.And the side of at least side is in step-like.Specifically, in embodiments of the present invention, in chip accommodating chamber 330 along depth
It spends in the cross sectional shape in direction, side 345b is in step-like.
Injection orifice 346 is additionally provided on the shell of encapsulating mould 340.Setting position, effect and the shape of injection orifice 346
Size is consistent with second embodiment, and this will not be repeated here.
Encapsulating mould 340 cover stacked chips 330 mode, encapsulating material 351 material selection and thickness, and heat at
The condition of reason is consistent with second embodiment, and therefore not to repeat here.
Fourth embodiment.
Fourth embodiment is with second embodiment and 3rd embodiment the difference is that there are adjacent in the chip of stacking
The width dimensions of chip are identical.Meanwhile encapsulating mould chip accommodating chamber is also different along depth direction cross sectional shape.Fourth embodiment
In, the state being bonded between connection type and encapsulating mould and stacked chips between chip, between chip and package substrate is equal
Second embodiment is consistent with 3rd embodiment.
Figure 12 is please referred to, multiple chips 430 are stacked in package substrate 400.
Connection type between chip 430, between chip 430 and envelope transglutaminase substrate 400 is real with second embodiment and third
The identical of example is applied, therefore not to repeat here.
Specifically, in embodiments of the present invention, chip 430 is four, it is respectively: chip 430a, chip 430b, chip
430c, chip 430d.Wherein, the size of chip 430b and chip 430c are essentially equal, and the width dimensions of 430a are greater than 430b,
The width dimensions of 430b are greater than 430d.
Herein, it should be noted that in an embodiment of the present invention, when adjacent chips 430 are equal sized, it is desirable that core
The number more than two of piece 430.Because if only there are two the equal chip of width dimensions in the chip 430 stacked, then chip
The structure of accommodating chamber with it is in the prior art identical, as section be rectangle chip accommodating chamber.
In embodiments of the present invention, the stack manner of chip 430 can be consistent with second embodiment, i.e. stacked chips
The contour surface of 430 two sides occurs step-like；The stack manner of chip 430 can also be consistent with 3rd embodiment, i.e., all
The corresponding side of chip 430 keeps concordant, is not specifically limited herein.Specifically, in embodiments of the present invention, chip 430
Stack manner and second embodiment it is consistent.
Please refer to Figure 13, the chip 430 that the covering of encapsulating mould 440 stacks.
After the chip 430 that the covering of encapsulating mould 440 stacks, the chip accommodating chamber profile and stacked chips of encapsulating mould 440
430 outer contour surface fits.
The embodiment of the invention also includes: encapsulating material is injected to encapsulating material area by injection orifice 446.Injection orifice 446
Effect, position are consistent with second embodiment, and this will not be detailed here.
The technological parameter of cure package material 451 please refers to second embodiment, and I will not elaborate.Solidify post package material
451 thickness is consistent with second embodiment, and which is not described herein again.
Correspondingly, the present invention also provides semiconductor devices please continue to refer to Figure 13, comprising: package substrate 400 stacks
The different chip 430 of multiple width dimensions on package substrate 400, packing material 410, metal interconnection structure 420 and envelope
Package material 451.
In embodiments of the present invention, chip shares 4 in stacked structure, is respectively: chip 430a, chip 430b, chip
430c, chip 430d.Wherein, the size of chip 430b and chip 430c are essentially equal, and the width dimensions of 430a are greater than 430b,
The width dimensions of 430b are greater than 430d.
The positional relationship of packing material 410 and metal interconnection structure 420 is consistent with second embodiment.
Encapsulating material 451 fits over the outer contour surface of stacked chips 430.The effect of encapsulating material 451, thickness with
Second embodiment is consistent, and this will not be repeated here.
Correspondingly, please referring to Figure 14, the present invention also provides semiconductor packaging molds 440, comprising: shell 441, permission are more
Opening 442, chip accommodating chamber 443 and the injection orifice 446 that a stacked chips pass through.
In embodiments of the present invention, since encapsulating mould 440 will cover the chip 430 of stacking, so encapsulating mould 440
The chamfered shape of chip accommodating chamber 430 also accordingly changes, the profile of chip accommodating chamber 430 at least one along chip accommodating chamber
The shape in the section of 430 depth directions includes and 442 corresponding bottom edges of opening, corresponding with chip accommodating chamber top 444
Top margin and the side 445a and 445b for being separately connected bottom edge endpoint corresponding with top margin.And from bottom edge to top margin, side 445a with
The wire length that 445b is parallel to bottom edge reduces.And the side of at least side is in step-like.Specifically, in the embodiment of the present invention
In, in cross sectional shape of the chip accommodating chamber 430 along its depth direction, side 445a and 445b is in step-like.
Injection orifice 446 is additionally provided on the shell of encapsulating mould 440.Setting position, effect and the shape of injection orifice 446
Size is consistent with second embodiment, and this will not be repeated here.
Encapsulating mould 440 cover stacked chips 430 mode, encapsulating material 451 material selection and thickness, and heat at
The condition of reason is consistent with second embodiment, and therefore not to repeat here.
So far, the present invention is described in detail.In order to avoid covering design of the invention, it is public that this field institute is not described
The some details known.Those skilled in the art as described above, completely it can be appreciated how implementing technology disclosed herein
Scheme.
Although some specific embodiments of the invention are described in detail by example, the skill of this field
Art personnel it should be understood that above example merely to being illustrated, the range being not intended to be limiting of the invention.The skill of this field
Art personnel are it should be understood that can without departing from the scope and spirit of the present invention modify to above embodiments.This hair
Bright range is defined by the following claims.
Claims (26)
1. a kind of semiconductor packaging mold characterized by comprising
Shell,
The opening for allowing the chip of multiple stackings to pass through；With
The chip accommodating chamber being set in the shell, the profile of the chip accommodating chamber are mutually fitted with the chip of multiple stackings
Answer, at least one shape along the section of the chip accommodating chamber depth direction of the profile of the chip accommodating chamber include with it is described
Be open corresponding bottom edge, with top margin corresponding at the top of the chip accommodating chamber and be separately connected the bottom edge and the top
Side corresponds to the two sides of endpoint, and the length of the top margin is less than the length on the bottom edge.
2. semiconductor packaging mold according to claim 1, which is characterized in that described from the bottom edge to the top margin
The length that two sides are parallel to the line on the bottom edge reduces.
3. semiconductor packaging mold according to claim 2, which is characterized in that at least one described side is in step-like.
4. semiconductor packaging mold according to claim 1, which is characterized in that further include: injection orifice, the injection orifice pass through
The shell is worn, and connects the chip accommodating chamber.
5. semiconductor packaging mold according to claim 4, which is characterized in that the injection orifice is set to the shell
Top connects the top of the chip accommodating chamber.
6. semiconductor packaging mold according to claim 1, which is characterized in that when the chip of the multiple stacking is received
When in the chip accommodating chamber, the stacking direction one of the chip of the depth direction and the multiple stacking of the chip accommodating chamber
It causes.
7. semiconductor packaging mold according to claim 1, which is characterized in that the chip of the multiple stacking can pass through
The opening is accommodated in the chip accommodating chamber.
8. a kind of semiconductor devices characterized by comprising
Package substrate；
It is stacked in multiple chips of the package substrate；With
Encapsulating material, the encapsulating material cover the outer contour surface of the chip of the multiple stacking, the encapsulating material it is outer
At least one shape along the section of the chip stacking direction of the multiple stacking of profile includes and package substrate surface phase
Corresponding bottom edge, with top margin corresponding at the top of the encapsulating material and be separately connected the bottom edge and the top margin corresponding end
The two sides of point, the length of the top margin are less than the length on the bottom edge.
9. semiconductor devices according to claim 8, which is characterized in that from the bottom edge to the top margin, the two sides
While the length for being parallel to the line on the bottom edge reduces.
10. semiconductor packing device according to claim 9, which is characterized in that at least one described side is in step-like.
11. semiconductor packing device according to claim 10, which is characterized in that the encapsulating material surface and the core
The distance between corresponding position of piece outer contour surface is the thickness of the encapsulating material.
12. semiconductor devices according to claim 11, which is characterized in that the thickness range is 0.5mm~1.5mm.
13. semiconductor devices according to claim 8, which is characterized in that further include: packing material and metal mutually link
Structure, the packing material and the metal interconnection structure are located at the package substrate and the core adjacent with the package substrate
Between piece and between the adjacent chip.
14. semiconductor devices according to claim 8, which is characterized in that the width dimensions of at least two chips are not
Together.
15. semiconductor devices according to claim 14, which is characterized in that the width dimensions of chip described in upper layer be less than etc.
The width dimensions of the chip described in lower layer adjacent thereto.
16. semiconductor devices according to claim 15, which is characterized in that the edge of chip described in upper layer without departing from
The edge of chip described in lower layer adjacent thereto.
17. a kind of packaging method of semiconductor devices characterized by comprising
Package substrate is provided, multiple chips are stacked in the package substrate；
Semiconductor packaging mold described in any one of claim 1-7 is provided；
The encapsulating mould is covered into the chip, so that the chip accommodating chamber is accommodated the chip of the multiple stacking, and described
The contour surface shape of the chip of the contour surface shape and stacking of chip accommodating chamber is adapted；With
By the injection orifice to injecting encapsulating material inside the chip accommodating chamber.
18. the packaging method of semiconductor devices according to claim 17, which is characterized in that the wheel of the chip accommodating chamber
Wide surface is 0.5mm~1.5mm with the distance between corresponding chip outline surface range.
19. the packaging method of semiconductor devices according to claim 17, which is characterized in that at least two chips
Width dimensions are different.
20. the packaging method of semiconductor devices according to claim 19, which is characterized in that the width of chip described in upper layer
Size is less than or equal to the width dimensions of chip described in lower layer adjacent thereto.
21. the packaging method of semiconductor devices according to claim 20, which is characterized in that the edge of chip described in upper layer
Edge of the position without departing from chip described in lower layer adjacent thereto.
22. the packaging method of semiconductor devices according to claim 17, which is characterized in that the injection orifice is through described
Shell, and be connected with the chip accommodating chamber.
23. the packaging method of semiconductor devices according to claim 22, which is characterized in that the injection orifice is set to institute
The top of shell is stated, and is connected with the top of the chip accommodating chamber.
24. the packaging method of semiconductor devices according to claim 17, which is characterized in that further include:
With metal interconnection structure connect two adjacent chips and the connection package substrate and with the package substrate
The adjacent chip；
Packing material is injected in gap between the chip and the package substrate and between the adjacent chip, it is described
Packing material covers the metal interconnection structure.
25. the packaging method of semiconductor devices according to claim 17, which is characterized in that inject the encapsulating material
Afterwards, further includes: the encapsulating material is heat-treated.
26. the packaging method of semiconductor devices according to claim 25, which is characterized in that the process of thermal treatment ginseng
Number includes: that temperature is 170 DEG C~300 DEG C, and the time is 90s~220s.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710931404.6A CN109637939B (en) | 2017-10-09 | 2017-10-09 | Semiconductor packaging mold, semiconductor device and packaging method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710931404.6A CN109637939B (en) | 2017-10-09 | 2017-10-09 | Semiconductor packaging mold, semiconductor device and packaging method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109637939A true CN109637939A (en) | 2019-04-16 |
| CN109637939B CN109637939B (en) | 2020-08-18 |
Family
ID=66051199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710931404.6A Active CN109637939B (en) | 2017-10-09 | 2017-10-09 | Semiconductor packaging mold, semiconductor device and packaging method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109637939B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809024A (en) * | 2020-06-16 | 2021-12-17 | 美光科技公司 | Capped microelectronic device packages and related systems, apparatus, and methods of manufacture |
| CN114823549A (en) * | 2022-06-27 | 2022-07-29 | 北京升宇科技有限公司 | Packaging structure and packaging method of longitudinal semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130001755A1 (en) * | 2006-04-17 | 2013-01-03 | Elpida Memory, Inc. | Stacked semiconductor device and fabrication method for same |
| CN104485291A (en) * | 2014-12-23 | 2015-04-01 | 南通富士通微电子股份有限公司 | Stacked semiconductor packaging method |
-
2017
- 2017-10-09 CN CN201710931404.6A patent/CN109637939B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130001755A1 (en) * | 2006-04-17 | 2013-01-03 | Elpida Memory, Inc. | Stacked semiconductor device and fabrication method for same |
| CN104485291A (en) * | 2014-12-23 | 2015-04-01 | 南通富士通微电子股份有限公司 | Stacked semiconductor packaging method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809024A (en) * | 2020-06-16 | 2021-12-17 | 美光科技公司 | Capped microelectronic device packages and related systems, apparatus, and methods of manufacture |
| CN114823549A (en) * | 2022-06-27 | 2022-07-29 | 北京升宇科技有限公司 | Packaging structure and packaging method of longitudinal semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109637939B (en) | 2020-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20170092634A1 (en) | Semiconductor Package, Semiconductor Device and Method of Forming the Same | |
| US9024448B2 (en) | Lower semiconductor molding die, semiconductor package, and method of manufacturing the semiconductor package | |
| CN109637939A (en) | The packaging method of semiconductor packaging mold, semiconductor devices and semiconductor devices | |
| US8629567B2 (en) | Integrated circuit packaging system with contacts and method of manufacture thereof | |
| TW200532871A (en) | Resin-sealed semiconductor device and method of manufacturing the same | |
| US6830954B2 (en) | Transfer molding and underfilling method and apparatus | |
| CN102593090B (en) | There is the leadframe package of the tube core on the pedestal that is arranged on isolation lead-in wire | |
| CN103972185A (en) | Integrated device and fabrication process thereof | |
| SG176512A1 (en) | Thermally enhanced semiconductor package and method of producing the same | |
| CN103358467A (en) | Mold apparatus for packaging semiconductor assembly | |
| TW200935527A (en) | Chip package apparatus and chip package process | |
| CN109671834A (en) | A kind of the LED chip CSP encapsulating structure and its packaging method of two-sided light out | |
| KR102576139B1 (en) | Molding mold, resin molding device, and manufacturing method of resin molding | |
| TW200304190A (en) | Method for producing a protection for chip edges and arrangement for the protection of chip edges | |
| CN107958877A (en) | Substrat structure, method for packing and semiconductor package | |
| TW201530665A (en) | Manufacturing method of selective electronic packaging device | |
| JP5758823B2 (en) | Manufacturing method of resin-sealed molded product of electronic component, lower mold for compression molding, and resin sealing device | |
| KR100653607B1 (en) | Resin-molding apparatus having a plural sub-runner for semiconductor chip package | |
| JPH02163953A (en) | Semiconductor device | |
| JP2016162767A (en) | Manufacturing method of mold package | |
| TW561601B (en) | Process for fabricating semiconductor package | |
| TW201128718A (en) | Mold array packaging method and mold tool utilizied for the same | |
| TW525276B (en) | Semiconductor package with molding compound flange and fabrication method thereof | |
| TWI531035B (en) | Semiconductor device of eliminating encapsulating stress | |
| JP3221971B2 (en) | Resin molding equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |