CN109615580A - Digital processing circuit - Google Patents
Digital processing circuit Download PDFInfo
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- CN109615580A CN109615580A CN201811438482.3A CN201811438482A CN109615580A CN 109615580 A CN109615580 A CN 109615580A CN 201811438482 A CN201811438482 A CN 201811438482A CN 109615580 A CN109615580 A CN 109615580A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T3/00—Geometric image transformation in the plane of the image
- G06T3/40—Scaling the whole image or part thereof
- G06T3/4007—Interpolation-based scaling, e.g. bilinear interpolation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/10—Image acquisition modality
- G06T2207/10004—Still image; Photographic image
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
- G06T2207/30148—Semiconductor; IC; Wafer
Abstract
A kind of digital processing circuit is disclosed, which includes: storage unit, and for storing multiple subarrays, each subarray is to extract to obtain from basic lattice array, and each basic point in basic lattice array has corresponding basic point coordinate and basic point value；Multiple first selectors, the coordinate of at least one reference point for choosing neighbouring insertion point in each subarray；Multiple second selectors choose the coordinate of multiple boundary points of target interval where insertion point for the coordinate according to each reference point in basic lattice array；And processing unit, insertion point value is determined based on the corresponding basic point value of coordinate of multiple boundary points.The circuit chooses reference point by first selector, boundary point is chosen from reference point by second selector, target interval where determining insertion point in such a way that two class selectors are cascade simultaneously obtains insertion point value by basic lattice array, the quantity for reducing selector, the power consumption for reducing circuit improve the stability of circuit.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of digital processing circuit.
Background technique
One-dimensional or multi-dimensional interpolation carries out inserted value by certain rule between the basic point of different dimensions, with basis
Existing look-up table obtains the value changed in region.Linear interpolation is based on insertion point co-ordinate, boundary point coordinate, boundary point value, passes through
Insertion point value is linearly calculated in weight.
Existing interpolation method, typically directly chooses the boundary point of insertion point, and then obtains the value of insertion point.Such as Fig. 1 institute
The schematic illustration for the method for one-dimensional interpolation in the prior art shown, the look-up table provided include 17 basic point P1-P17, are searched
The basic point information embodied in table includes basic point coordinate and corresponding basic point value.When the coordinate of insertion point 10 passes through
When two boundary points of P13, P14 limit, selections P13 is left margin point, and P14 is right margin point, and then based on two boundary points
Point value carries out linear weight and obtains insertion point value 20.The boundary point that above-mentioned interpolation method directly chooses insertion point obtains insertion point value
20, i.e., left margin point is chosen in 16 left reference points respectively, right margin point is chosen in 16 right reference points.However it realizes and is somebody's turn to do
The hardware integration circuit devcie quantity of method is more, circuit connection is complicated, therefore realizes the hardware circuit of this method in the prior art
Power consumption is big, at high cost, stability is poor.
Summary of the invention
In view of the above problems, the purpose of the present invention is to provide a kind of digital processing circuits, to make to realize interpolation method
The power consumption of hardware circuit, cost reduces, and reduces the connection line between device to improve the stability of hardware circuit.
A kind of digital processing circuit provided according to the present invention, comprising: storage unit, for storing basic lattice array, from
It is extracted in the basis lattice array and obtains multiple subarrays, each basic point in the basis lattice array has corresponding basis
Point coordinate and basic point value；Multiple first selectors, for choosing at least the one of neighbouring insertion point in each subarray
The coordinate of a reference point；Multiple second selectors, for the coordinate according to each reference point in the basic lattice array
The coordinate of multiple boundary points of target interval where choosing the insertion point；And processing unit, it is based on the multiple boundary point
The corresponding basic point value of coordinate determine insertion point value corresponding with insertion point, wherein the base at least one described subarray
Plinth point number is less than the basic point number in the basic lattice array.
Optionally, the basic point between multiple subarrays does not overlap.
Optionally, when the basic lattice array is that n ties up array, the target interval has 2nA boundary point, the n
For positive integer.
Optionally, the quantity of the subarray is equal to the quantity for determining the boundary point of the target interval.
Optionally, the multiple first selector in each subarray for choosing at least one described reference point
Coordinate.
Optionally, when the basic lattice array is one-dimensional array, the first subarray is by the on line direction or column direction
Odd number basic point is constituted, and the second subarray is made of the even number basic point on line direction or column direction.
Optionally, when the basic lattice array is two-dimensional array, the row coordinate of the basic point in the first subarray is surprise
Number and column coordinate are odd number, and the row coordinate of the basic point in the second subarray is even number and column coordinate is odd number, third subarray
In the row coordinate of basic point be odd number and column coordinate is even number, the row coordinate of the basic point in the 4th subarray is even number and column
Coordinate is even number, wherein the row coordinate of the basic point in each subarray is the basic point in the basic lattice array
Corresponding line number, the row coordinate of the basic point in each subarray are that the basic point is corresponding in the basic lattice array
Columns.
Optionally, the corresponding basic point value of coordinate of the processing unit based on the multiple boundary point, by linearly weighing
Re-computation obtains the insertion point value.
Optionally, the first selector and/or the second selector are alternative selector.
Digital processing circuit provided by the invention chooses neighbouring insertion point by first selector in each subarray
The coordinate of multiple reference points chooses insertion point institute according to the coordinate of each reference point by second selector in basic lattice array
In the coordinate of multiple boundary points of target interval, is realized in such a way that two class selectors are cascade and limit insertion in basic lattice array
The target interval of point, and insertion point value is determined based on the corresponding basic point value of the coordinate of multiple boundary points.The digital processing circuit
The space for storing the memory of basic lattice array is saved, and digital processing circuit provided by the invention passes through two class selectors
Determine that the target interval of insertion point can reduce the quantity of selector, and then the power consumption for reducing circuit improves the stabilization of circuit
Property.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows the schematic illustration of one-dimensional interpolation method according to prior art；
Fig. 2 shows the structural schematic diagrams of digital processing circuit according to an embodiment of the present invention；
Fig. 3 shows the flow diagram that digital processing circuit according to embodiments of the present invention carries out interpolation operation；
Fig. 4 shows the schematic illustration that digital processing circuit according to a first embodiment of the present invention carries out interpolation operation；
Fig. 5 shows the schematic illustration that digital processing circuit according to a second embodiment of the present invention carries out interpolation operation.
Specific embodiment
The various embodiments that the present invention will be described in more detail that hereinafter reference will be made to the drawings.In various figures, identical element
It is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
With reference to the accompanying drawings and examples, specific embodiments of the present invention will be described in further detail.
Fig. 2 shows the structural schematic diagrams of digital processing circuit according to an embodiment of the present invention.Fig. 3 shows real according to the present invention
Apply the flow diagram that a digital processing circuit carries out interpolation operation.
In conjunction with shown in Fig. 2,3, digital processing circuit 300 of the invention includes storage unit 301, multiple first selectors
302, multiple second selectors 303 and processing unit 304.Storage unit 301 is for storing multiple subarrays, each subarray
It is to extract to obtain from basic lattice array, each basic point in basic lattice array has corresponding basic point coordinate and basis
Point value, basic lattice array, subarray storage in semiconductor memory, for example including but be not limited to read-only memory (ROM,
Read-only Memory), appointing in random access memory (RAM, Random Access Memory) and flash chip
It is a kind of.The input terminal of multiple first selectors 302 connects the address port of basic point in each subarray in storage unit 301,
For choosing the coordinate of at least one reference point of neighbouring insertion point in each subarray.Multiple second selectors 303 it is defeated
Enter the output end that end for example connects first selector 302, for choosing in basic lattice array according to the coordinate of each reference point
The coordinate of multiple boundary points of target interval where insertion point.The output end that processing unit 304 connects second selector 303 is used for
Multiple boundary point coordinates are received, and corresponding basic point value, and then determining and insertion point are read based on the coordinate of multiple boundary points
Corresponding insertion point value.
When basic lattice array is that n ties up array, the target interval of insertion point has 2nA boundary point, n are positive integer.Its
In, it is preferable that the basic point number in subarray is less than the basic point number in basic lattice array；Preferably, multiple sons
Basic point between array does not overlap；Preferably, the quantity of subarray is equal to the number for determining the boundary point of target interval
Amount；Preferably, multiple first selectors in each subarray for choosing at least one reference point coordinate；Preferably, work as base
When plinth dot matrix is classified as one-dimensional array, the first subarray is made of the odd number basic point on line direction or column direction, the second son
Array is made of the even number basic point on line direction or column direction；Preferably, when basic lattice array is two-dimensional array, the
The row coordinate of basic point in one subarray is odd number and column coordinate is odd number, and the row coordinate of the basic point in the second subarray is
Even number and column coordinate are odd number, and the row coordinate of the basic point in third subarray is odd number and column coordinate is even number, the 4th submatrix
The row coordinate of basic point in column is even number and column coordinate is even number, wherein the row coordinate of the basic point in each subarray is
The basic point corresponding line number in basic lattice array, the row coordinate of the basic point in each subarray are the basic point on basis
Corresponding columns in lattice array；Preferably, the corresponding basic point value of coordinate of the processing unit based on multiple boundary points, by linear
Weight calculation obtains insertion point value；Preferably, first selector and/or second selector for example can be alternative selector.
Digital processing circuit 300 of the present invention executes interpolation operation and includes the following steps:
Step S10: multiple subarrays are extracted from basic lattice array.The basic lattice array stored in storage unit 301 can
It is extracted with classification and obtains multiple subarrays, the basic point between each subarray can be overlapped or not be overlapped, when each submatrix
When basic point between column is not overlapped, it is preferable that each subarray for example can by by basic lattice array each dimension odd number/
The crossover arrangement assembled classification of even number obtains, and specifically, when basic lattice array is one-dimensional array, the first subarray is by the side of going
To or column direction on odd number basic point constitute, the second subarray is by the even number basic point on line direction or column direction
It constitutes；When basic lattice array is two-dimensional array, the row coordinate of the basic point in the first subarray is odd number and column coordinate is odd
It counts, the row coordinate of the basic point in the second subarray is even number and column coordinate is odd number, the row of the basic point in third subarray
Coordinate is odd number and column coordinate is even number, and the row coordinate of the basic point in the 4th subarray is even number and column coordinate is even number,
In, the row coordinate of the basic point in each subarray is the basic point corresponding line number in basic lattice array, each subarray
In basic point row coordinate be the basic point corresponding columns in basic lattice array.Wherein, the subarray is just to table
Show the corresponding optional basic point of each boundary point, basic lattice array is divided into multiple subarrays, just to easily be inserted
Each boundary point of access point, which, which can be merely representative of, classifies the basic point of basic lattice array, can also indicate base
Plinth lattice array is divided into multiple subarrays.Following embodiment neutron array can be merely representative of the basic point of basic lattice array point
Class, multiple subarray are still stored in a storage unit with a complete basic lattice array, and not by basic lattice array
Multiple subarrays are divided into be respectively stored in different storage mediums.
Step S20: at least one reference point coordinate of neighbouring insertion point is chosen in each subarray.First selector
302 in each subarray for choosing multiple reference points of neighbouring insertion point co-ordinate, the reference point chosen in each subarray
Quantity be not more than 2n.Preferably, more by combining to obtain basic lattice array in the crossover arrangement of each dimension odd/even
When a subarray, the quantity of subarray is 2n, one for example can be at least chosen in each subarray according to insertion point co-ordinate
Closest to the reference point of insertion point.
Step S30: target interval is multiple where determining insertion point in basic lattice array according to each reference point coordinate
Boundary point coordinate.Mesh where second selector 303 is used to determine insertion point in basic lattice array according to each reference point coordinate
Multiple boundary point coordinates in section are marked, the boundary point of insertion point is used to limit position of the insertion point in basic lattice array, wherein
The quantity of boundary point is 2n.It is corresponded to when each subarray can for example be combined according to the crossover arrangement of each dimension odd/even
When classification obtains, the reference point quantity of selection can at least be equal to the quantity of boundary point.
Step S40: the corresponding insertion point value in insertion point is determined based on the corresponding basic point value of coordinate of multiple boundary points.Place
The coordinate for multiple boundary points that reason unit 304 is obtained based on multiple second selectors 303, reads the corresponding basis of each boundary point
Point value determines the corresponding insertion point value in insertion point, it is preferable that insertion point value can for example be calculated by linear weight.
To sum up, digital processing circuit of the invention includes multiple first selectors for choosing multiple reference points, and
For choosing multiple second selectors of multiple boundary points.The input of first selector is that the basic point in each subarray is sat
Mark.Second selector on the basis of first selector for limiting the position of insertion point.
And the present invention chooses the reference point of insertion point by first selector, is selected from reference point by second selector
The boundary point for taking insertion point realizes the position that insertion point is limited in basic lattice array in such a way that two class selectors are cascade, into
And it determines insertion point value, reduce the use of selector and reduces the connection of circuit, while reducing realization multi-dimensional interpolation
The power consumption of the hardware circuit of method improves the stability of circuit entirety.
Digital processing circuit proposed by the present invention will be described below by specific embodiment.Following embodiment neutron array is pressed
It is obtained according to the corresponding classification of value on the crosspoint of each dimension odd/even, and by first selector respectively in each submatrix
The reference point of a closest insertion point is chosen in column, obtained reference point limits insertion point in basic point by second selector
Position in array, further, first selector and second selector are alternative selector.Following embodiment is retouched
It states based on above-mentioned qualifications, however by the description in figure it is found that implementation of the invention is without being limited thereto.
Fig. 4 shows the schematic illustration that digital processing circuit according to a first embodiment of the present invention carries out interpolation operation.
As shown in figure 4, showing the schematic illustration that digital processing circuit realizes one-line interpolation operation.Wherein basic point
Array 100 includes 17 basic point P1-P17.Basic lattice array 100 is divided into according to the crosspoint correspondence of one-dimensional odd/even
For the first subarray 110 and the second subarray 120, the first subarray 110 is made of the odd number basic point on line direction, the
Two subarrays 120 are made of the even number basic point on line direction.It is chosen from the first subarray 110 by first selector
One reference point P13 of neighbouring insertion point 101 chooses a reference point of neighbouring insertion point 101 from the second subarray 120
P14 chooses a reference point in first foundation array 110 from 9 basic points, therefore only needs 8 first selectors, and second
A reference point is chosen in base array 120 from 8 basic points, therefore only needs 7 first selectors.Pass through the second selection
Device chooses left margin point and right margin point respectively from reference point P13, P14, it is therefore desirable to two second selectors.It needs to illustrate
, in the present invention first selector and second selector just to be better understood by the present invention, wherein first selector and
Second selector for example can be the alternative selector of same model or different model.
To sum up, in the above-described first embodiment, 17 selectors are needed, and insertion point is chosen according to a step in the prior art
Boundary point when, it is above-mentioned basis lattice array need 30 ((17-1-1) x2=30) a alternative selectors, when in basic lattice array
When interpolation number of nodes (points subtract 1 based in one-dimensional basis lattice array) N is sufficiently large, digital processing circuit of the invention can subtract
Few N/2 selector, wherein N is the natural number greater than 1.
Fig. 5 shows the schematic illustration that digital processing circuit according to a second embodiment of the present invention carries out interpolation operation.
As shown in figure 5, showing the schematic illustration that digital processing circuit realizes two-dimensional linear interpolation operation.Wherein basic point
Array 200 includes 17x17 basic point.By basic lattice array 200 according to horizontal odd/even and the friendship of vertically odd/even number
Crunode correspondence is divided into the first subarray 210, the second subarray 220, third subarray 230 and the 4th subarray 240, the first submatrix
The row coordinate of basic point in column 210 is odd number and column coordinate is odd number, and the row coordinate of the basic point in the second subarray 220 is
Even number and column coordinate are odd number, and the row coordinate of the basic point in third subarray 230 is odd number and column coordinate is even number, the 4th son
The row coordinate of basic point in array 240 is even number and column coordinate is even number.Through first selector from the first subarray 210
A reference point 211 for choosing neighbouring insertion point 201 chooses a correlation of neighbouring insertion point 201 from the second subarray 220
Point 221 is chosen a reference point 231 of neighbouring insertion point 201 from third subarray 230, is chosen from the 4th subarray 240
One reference point 241 of neighbouring insertion point 201.A reference point is chosen in first foundation array 210 from 9x9 basic point,
Therefore 80 first selectors are only needed, choose a reference point from 8x9 basic point in the second base array 220, therefore
71 first selectors are only needed, choose a reference point from 9x8 basic point in third base array 230, therefore only need
71 first selectors are wanted, choose a reference point from 8x8 basic point in the 4th base array 240, therefore only need 63
A first selector.It is selected respectively from reference point 211, reference point 221, reference point 231, reference point 241 by second selector
Take upper left boundary point, lower-left boundary point, upper right boundary point and bottom right boundary point, it is therefore desirable to 3x4 second selector.It needs
Bright, first selector and second selector are in the present invention just to be better understood by the present invention, wherein first selector
It for example can be the alternative selector of same model or different model with second selector.
To sum up, in above-mentioned second embodiment, 297 selectors are needed, and is chosen and is inserted into according to a step in the prior art
When the boundary point of point, above-mentioned basis lattice array needs a alternative selection of 1020 (((17-1) x (17-1) -1) x 4=1020)
Device, it is of the invention when interpolation number of nodes (points subtract 1 based in one-dimensional basis lattice array) N is sufficiently large in basic lattice array
Digital processing circuit can reduce (NxN- (N/2) x (N/2)) a selector, and wherein N is the natural number greater than 1.
When dimension n is greater than 2, according to digital processing circuit provided by the invention, when interpolation number of nodes in basic lattice array
When (points subtract 1 based in one-dimensional basis lattice array) N is sufficiently large, interpolating apparatus of the invention can reduce (Nn–(N/2)n) a
Selector, wherein N is the natural number greater than 1.
Digital processing circuit of the invention, which can solve, obtains the changing value in region by existing basic lattice array, both
The space for storing the memory of basic lattice array is saved, while digital processing circuit provided by the invention execution interpolation operation can
To reduce the quantity of selector, and then the power consumption for reducing hardware circuit improves the stability of hardware circuit.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (9)
1. a kind of digital processing circuit characterized by comprising
Storage unit is extracted from the basic lattice array for storing basic lattice array and obtains multiple subarrays, the basis
Each basic point in lattice array has corresponding basic point coordinate and basic point value；
Multiple first selectors, the seat of at least one reference point for choosing neighbouring insertion point in each subarray
Mark；
Multiple second selectors, for choosing the insertion in the basic lattice array according to the coordinate of each reference point
The coordinate of multiple boundary points of target interval where point；And
Processing unit determines insertion corresponding with the insertion point based on the corresponding basic point value of coordinate of the multiple boundary point
Point value,
Wherein, the basic point number at least one described subarray is less than the basic point number in the basic lattice array.
2. digital processing circuit according to claim 1, which is characterized in that the basic point between multiple subarrays is mutual
It is not overlapped.
3. digital processing circuit according to claim 1, which is characterized in that when the basis lattice array is that n ties up array, institute
The target interval for stating insertion point has 2nA boundary point, the n are positive integer.
4. the digital processing circuit stated according to claim 3, which is characterized in that the quantity of the subarray is equal to for determining
State the quantity of the boundary point of target interval.
5. digital processing circuit according to claim 4, which is characterized in that the multiple first selector is used for each
At least one described reference point coordinate is chosen in the subarray.
6. digital processing circuit according to claim 5, which is characterized in that when the basic lattice array is one-dimensional array
When,
First subarray is made of the odd number basic point on line direction or column direction,
Second subarray is made of the even number basic point on line direction or column direction.
7. digital processing circuit according to claim 5, which is characterized in that when the basic lattice array is two-dimensional array
When,
The row coordinate of basic point in first subarray is odd number and column coordinate is odd number,
The row coordinate of basic point in second subarray is even number and column coordinate is odd number,
The row coordinate of basic point in third subarray is odd number and column coordinate is even number,
The row coordinate of basic point in 4th subarray is even number and column coordinate is even number,
Wherein, the row coordinate of the basic point in each subarray is the basic point corresponding row in the basic lattice array
It counts, the row coordinate of the basic point in each subarray is the basic point corresponding columns in the basic lattice array.
8. digital processing circuit according to claim 1, which is characterized in that the processing unit is based on the multiple boundary
The corresponding basic point value of the coordinate of point, is calculated the insertion point value by linear weight.
9. digital processing circuit according to claim 1, which is characterized in that the first selector and/or described second
Selector is alternative selector.
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| CN201811438482.3A CN109615580B (en) | 2018-11-28 | 2018-11-28 | Digital processing circuit |
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| CN201811438482.3A CN109615580B (en) | 2018-11-28 | 2018-11-28 | Digital processing circuit |
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| CN101500168A (en) * | 2009-02-18 | 2009-08-05 | 北京中星微电子有限公司 | 1/3 interpolation apparatus for image brightness |
| CN101778280A (en) * | 2010-01-14 | 2010-07-14 | 山东大学 | Circuit and method based on AVS motion compensation interpolation |
| US20160062948A1 (en) * | 2014-08-27 | 2016-03-03 | Imagination Technologies Limited | Efficient interpolation |
| JP2016163070A (en) * | 2015-02-26 | 2016-09-05 | キヤノン株式会社 | Data converter and control method and program thereof |
| CN106096263A (en) * | 2016-06-07 | 2016-11-09 | 深圳市国微电子有限公司 | A kind of multidimensional linear polation method and apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6157937A (en) * | 1997-07-17 | 2000-12-05 | Nec Corporation | High speed interpolation circuit with small circuit scale |
| CN101500168A (en) * | 2009-02-18 | 2009-08-05 | 北京中星微电子有限公司 | 1/3 interpolation apparatus for image brightness |
| CN101778280A (en) * | 2010-01-14 | 2010-07-14 | 山东大学 | Circuit and method based on AVS motion compensation interpolation |
| US20160062948A1 (en) * | 2014-08-27 | 2016-03-03 | Imagination Technologies Limited | Efficient interpolation |
| JP2016163070A (en) * | 2015-02-26 | 2016-09-05 | キヤノン株式会社 | Data converter and control method and program thereof |
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