CN109614730A

CN109614730A - SRAM cell design method

Info

Publication number: CN109614730A
Application number: CN201811566658.3A
Authority: CN
Inventors: 张亮; 景旭斌
Original assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Current assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date: 2018-12-19
Filing date: 2018-12-19
Publication date: 2019-04-12
Anticipated expiration: 2038-12-19
Also published as: CN109614730B

Abstract

The invention discloses a kind of SRAM cell design methods, include the following steps: step 1, according to existing core devices model, simulate the core devices of specific active area dimensions W0 and grid size L0；Step 2, centered on benchmark device size W0/L0, form the array of a device, using the array of the device as test structure, collect its electric property, optimal active area dimensions W and grid size L value selected, as final device；Step 3, using the core devices of the W/L size after optimization, construct sram cell, according to finally determining sram cell, establish Basic Exhibition, design test structure carries out model extraction and characterization, forms the model of non-standard sram cell；Step 4, on the basis of the model of non-standard sram cell, carry out the design of memory compiler, and complete to verify.The present invention has off-standard size, at low cost, simple process.

Description

SRAM cell design method

Technical field

The present invention relates to IC chip manufacturing fields, more particularly to a kind of SRAM (Static RAM) unit Design method.

Background technique

SRAM is widely used in various chips as storage organization most common in logic circuit.Since SRAM can be with Perfectly compatible with logic process, read or write speed is fast, low in energy consumption, so application scenarios are very wide, especially as cache, such as The L1 (level cache) of CPU/L2 (L2 cache) etc..But SRAM is disadvantageous in that it generally requires 6-8 transistor, and Flash (flash memory)/DRAM (dynamic random access memory)/OTP (One Time Programmable) this memory device substantially can be by 1-2 transistor adds capacitance resistance etc. to form.So the chip area that SRAM is occupied is significantly larger than other memory constructions.

For each chip technology node, it (mainly includes individual unit face that industry, which can arrange standard set sram cell, Sum unit performance).But the chip manufacturing chamber of commerce is adjusted according to the operational characteristic of itself and optimization design.This standard SRAM The size of unit be it is unified, for Chevron Research Company (CRC) different manufactories carry out flexibly switching provide possibility.And this standard Sram cell is generally applicable in various SRAM memory capacity, such as from several K to hundreds of million.But due to high capacity to be met In the case of, the mismatch and fluctuation of device, SRAM device can generally use special light shield and injection condition, independently of core devices It is adjusted, to obtain optimum performance performance.

But under the application scenarios of some low capacity, such as within tens of bit to 1Mbit, if still using this mark Quasi- SRAM, then needing additional light shield expense.And in order to which a small amount of SRAM needs to pay additional light shield, drawn high product at This.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of SRAM cell design methods, have off-standard size, cost Low, simple process；For this purpose, the present invention also provides a kind of 6T sram cell.

In order to solve the above technical problems, SRAM cell design method of the invention, includes the following steps: step 1, according to existing There is a core devices model, carry out simulation calculation, with the single tube performance of standard SRAM, unit performance is target, and simulating specific has The core devices of source region size W0 and grid size L0, the core devices size are defined as benchmark device size W0/L0；

Step 2, centered on benchmark device size W0/L0, make fixed grid size L, the size of active area dimensions W respectively Variation；And fixed active area dimensions W, the size variation of grid size L forms the array of a device, by the array of the device As test structure, its electric property is collected；According to the electric property of the array of the device, therefrom select optimal active Area size W and grid size L value, as final device；

Step 3, using the core devices of the W/L size after optimization, construct sram cell, it is mono- according to finally determining SRAM Member, establishes Basic Exhibition, and design test structure carries out model extraction and characterization, forms the model of non-standard sram cell；

Step 4, on the basis of the model of non-standard sram cell, carry out the design of memory compiler, and complete to verify.

Any actual chips will necessarily include core devices and input and output device.Under Normal practice, sram cell Need additional light shield and injection process, it is at high cost, process flow is complicated.And way of the invention is the work using core devices Process to form non-standard SRAM device to synchronize, and the non-standard sram cell device is without additional dedicated light shield and additional Injection technology can reduce product cost, process complexity and processing step, energy conservation and environmental protection, and provide the final yield of product.

The following table 1 is the table of comparisons of the present invention with standard SRAM.

Table 1

Detailed description of the invention

Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

Fig. 1 is the SRAM cell design method flow schematic diagram.

Specific embodiment

For this specific application scenarios demand of low capacity, the SRAM cell design method is provided a kind of nonstandard The SRAM cell design method of object staff cun, the non-standard sram cell using this method production has simple process, without dedicated Light shield, it is at low cost the features such as, and readwrite performance still can the other kinds of memory construction such as far super DRAM/OTP.

The sram cell includes core devices and input and output device, the SRAM cell design method, using core The technique of device to form off-gauge SRAM device to synchronize.As shown in connection with fig. 1, the specific implementation process is as follows:

According to existing core devices model, simulation calculation is carried out, with the single tube performance of standard SRAM, unit performance is mesh Mark, simulates the core devices of specific active area dimensions W0 and grid size L0.The core devices size is defined as benchmark device Size W0/L0.

Centered on benchmark device size W0/L0, make fixed grid size L, the size variation of active area dimensions W respectively； And fixed active area dimensions W, the size variation of grid size L form the array of a device.Using the array of the device as survey Structure is tried, its electric property is collected.According to the array electric property of device, optimal active area dimensions W and grid are therefrom selected Pole size L value, as final core devices.

Using the core devices of the W/L size after optimization, sram cell is constructed.By taking 6T sram cell as an example, it is usually required mainly for Three devices constitute a sram cell, and according to technological ability, can carry out in performance and size to the sram cell of composition Adjustment and balance.According to finally determining sram cell, establish Basic Exhibition, design test structure, carry out model extraction and Characterization.

On the basis of the model of the non-standard sram cell of low cost, the design of memory compiler is carried out, and completes to verify. After being finally completed, designer can call these non-standard SRAM designs of low cost under design environment.

Using the non-standard SRAM of low cost described in the invention, at least 2 dedicated light shields of SRAM device can be reduced, and Corresponding specific injection technology is saved, simple flow reduces product cost.

The present invention uses simulation calculation, can obtain single tube performance identical or approximate with existing standard SRAM.

The present invention includes to use various sizes of device array method, can obtain the device susceptibility under different sizes, It can screen and obtain optimum size combination, and dimensionally-optimised, acquisition best-of-breed element performance can be carried out according to susceptibility.

Present invention may apply to all process nodes and various types of SRAM.Under the premise of low cost, core is improved The caching speed of piece, and then chip overall performance is improved, various general or even specific demand can be met with customization.

Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these It should be regarded as protection scope of the present invention.

Claims

1. a kind of ram cell design method, which comprises the steps of:

Step 1, according to existing core devices model, carry out simulation calculation, with the single tube performance of standard SRAM, unit performance is mesh Mark, simulates the core devices of specific active area dimensions W0 and grid size L0, which is defined as benchmark device Size W0/L0；

Step 2, centered on benchmark device size W0/L0, make fixed grid size L respectively, the size of active area dimensions W becomes Change；And fixed active area dimensions W, the size variation of grid size L form the array of a device, and the array of the device is made To test structure, its electric property is collected；According to the electric property of the array of the device, optimal active area is therefrom selected Size W and grid size L value, as final device；

Step 3, using the core devices of the W/L size after optimization, construct sram cell, according to finally determining sram cell, Basic Exhibition is established, design test structure carries out model extraction and characterization, forms the model of non-standard sram cell；

2. design method as described in claim 1, it is characterised in that: according to actual process and device performance, to composition Sram cell carries out performance and adjustment and balance in size.

3. design method as described in claim 1, it is characterised in that: according to the combination array of building device, obtain Device susceptibility under different sizes, screening obtain optimum size combination, dimensionally-optimised according to device susceptibility progress, obtain Obtain best-of-breed element performance.

4. design method as described in claim 1, it is characterised in that: be suitable for all process nodes and various types of SRAM。