CN109599342A - A kind of production method of FinFET side wall - Google Patents
A kind of production method of FinFET side wall Download PDFInfo
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- CN109599342A CN109599342A CN201811560774.4A CN201811560774A CN109599342A CN 109599342 A CN109599342 A CN 109599342A CN 201811560774 A CN201811560774 A CN 201811560774A CN 109599342 A CN109599342 A CN 109599342A
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- side wall
- finfet
- production method
- grid
- dielectric layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 34
- 125000006850 spacer group Chemical group 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 2
- 230000005669 field effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- KOOADCGQJDGAGA-UHFFFAOYSA-N [amino(dimethyl)silyl]methane Chemical compound C[Si](C)(C)N KOOADCGQJDGAGA-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of production methods of FinFET side wall, comprising the following steps: step S01: providing semi-conductive substrate, forms the fin and grid of FinFET on the semiconductor substrate；Step S02: the fin and grid are completely covered dielectric layer deposited on the semiconductor substrate；Step S03: deep trouth is formed in the dielectric layer of the grid two sides；Step S04: spacer material is deposited in the deep trouth；Step S05: spacer material extra except the deep trouth is removed；Step S06: removal dielectric layer material forms side wall in the grid two sides.Technique of the invention can be compatible with conventional silicon substrate super large-scale integration manufacturing technology, has simple, convenient, period short feature, hence it is evident that reduce process costs.
Description
Technical field
The present invention relates to the manufactures of technical field integrated circuit technology, more particularly, to a kind of production of FinFET side wall
Method.
Background technique
With the continuous development of semiconductor technology, traditional planar device has been difficult to the need for meeting people to high performance device
It asks.
Fin formula field effect transistor (Fin Field-Effect Transistor, FinFET) is a kind of solid type device,
Including the fin vertically formed on substrate and the stacking gate intersected with fin.This design can greatly improve circuit control and subtract
Few electric leakage mouth, while the lock that can also substantially shorten transistor is long.
Referring to FIG. 1, Fig. 1 is a kind of schematic perspective view of existing fin formula field effect transistor.As shown in Figure 1,
Fin formula field effect transistor structure includes: the semiconductor substrate 10 positioned at bottom, is formed in the semiconductor substrate 10 convex
The fin 14 risen, fin 14 are obtained generally by etching to semiconductor substrate 10；Dielectric layer 11 is covered on the semiconductor
A part of the side wall of 10 surface and fin 14；Gate structure 12 across in the fin 14 top and side wall, grid
Structure 12 includes gate dielectric layer (not shown) and the gate electrode (not shown) on gate dielectric layer.More about fin
The introduction of formula field effect transistor please refers to the United States Patent (USP) of Publication No. " US7868380B2 ".
The production of existing fin formula field effect transistor side wall in one layer of spacer material of fin and gate deposition, is then adopted first
Method with the ion etching of low energy plus bias carries out side wall etching to existing fin formula field effect transistor, is retaining grid
The side wall of pole simultaneously, needs to remove the spacer material of the side fin (Fin).However, being directed to the etching that this depth-to-width ratio is more than 10, need
500% or more over etching is carried out, such process will cause the silicon loss (loss is greater than 5nm) on the surface Fin, but also meeting
Bring some other problems.
So being badly in need of the production method for finding a kind of new FinFET side wall, to eliminate the shortcomings of the prior art.
Summary of the invention
It is an object of the invention to overcome drawbacks described above of the existing technology, a kind of production side of FinFET side wall is provided
Method.
To achieve the above object, technical scheme is as follows:
A kind of production method of FinFET side wall, comprising the following steps:
Step S01: providing semi-conductive substrate, forms the fin and grid of FinFET on the semiconductor substrate；
Step S02: the fin and grid are completely covered dielectric layer deposited on the semiconductor substrate；
Step S03: deep trouth is formed in the dielectric layer of the grid two sides；
Step S04: spacer material is deposited in the deep trouth；
Step S05: spacer material extra except the deep trouth is removed；
Step S06: removal dielectric layer material forms side wall in the grid two sides.
Further, in step S02, the dielectric layer is at least double-layer structure, include from top to bottom mask layer and
Planarization layer.
Further, the mask layer is silicon oxynitride, and the planarization layer is carbon-free dielectric layer.
Further, the planarization layer is SiONH.
Further, the planarization layer is deposited using FCVD technique then to be solidified by high annealing.
Further, use trimethylsilyl ammonia and ammonia as reaction source, the high annealing in the FCVD technique
Temperature be 950~1100 DEG C.
Further, in step S04, the spacer material is silicon nitride.
Further, the spacer material is deposited using plasma enhanced atomic layer deposition method.
Further, in step S05, spacer material extra except the deep trouth is removed using hot phosphoric acid.
Further, in step S06, using dry etching, and O is used2As etching gas, the dielectric layer material is removed
Material.
It can be seen from the above technical proposal that the present invention deposits a kind of tool stream by the process first with FCVD
The novel medium material of dynamic property, such as SiONH；This material is not carbon containing, and after high annealing, intensity with higher can
The body structure surface and groove with irregular complex profile are filled, can fully ensure that dielectric material to fin and grid in this way
The filling at position.Then side wall region is defined by chemical wet etching, forms deep trouth in the dielectric layer, then increase by plasma
The method of strong atomic layer deposition (PEALD) deposits spacer material, and spacer material is filled into deep trouth.Finally dielectric material is gone
It removes, the side wall of FinFET can be ultimately formed.Meanwhile technique of the invention can be manufactured with conventional silicon substrate super large-scale integration
Technical compatibility has simple, convenient, period short feature, to significantly reduce process costs.
Detailed description of the invention
Fig. 1 is a kind of schematic perspective view of existing fin formula field effect transistor.
Fig. 2 is a kind of production method flow diagram of FinFET side wall of the present invention.
Fig. 3~Fig. 8 is the processing step schematic diagram that method according to fig. 2 forms a kind of FinFET side wall.
Specific embodiment
With reference to the accompanying drawing, specific embodiments of the present invention will be described in further detail.
It should be noted that in following specific embodiments, when describing embodiments of the invention in detail, in order to clear
Ground indicates structure of the invention in order to illustrate, spy does not draw to the structure in attached drawing according to general proportion, and has carried out part
Amplification, deformation and simplified processing, therefore, should be avoided in this, as limitation of the invention to understand.
In specific embodiment of the invention below, referring to Fig. 2, Fig. 2 is a kind of system of FinFET side wall of the present invention
Make method flow schematic diagram；Meanwhile Fig. 3~Fig. 8 is please referred to, Fig. 3~Fig. 8 is that method according to fig. 2 forms a kind of side FinFET
The processing step schematic diagram of wall.As shown in Fig. 2, a kind of production method of FinFET side wall of the invention, it may include following steps:
Step S01: providing semi-conductive substrate, forms the fin and grid of FinFET on the semiconductor substrate.
Semiconductor substrate 100 can be monocrystalline silicon, polysilicon or amorphous silicon；Semiconductor substrate 100 be also possible to silicon, germanium,
GaAs or silicon Germanium compound；Semiconductor substrate 100 can also have the silicon substrate (SOI substrate) on epitaxial layer or insulator；
Semiconductor substrate 100 can also be other semiconductor materials, and this is no longer going to repeat them.
Please refer to Fig. 3.Specifically, forming the fin 200 and grid of FinFET on a semiconductor substrate 100 in the present embodiment
When pole 300, fin 200 can be the monocrystalline silicon for being doped with N-type or p type impurity, grid 300 can be doping polysilicon or
Metal gate.
Step S02: fin and grid are completely covered dielectric layer deposited on a semiconductor substrate.
Please refer to Fig. 4.Specifically, in the present embodiment, when deposit forms dielectric layer 400 on a semiconductor substrate 100, medium
Layer 400 at least can be double-layer structure；It can successively include from top to bottom mask layer 401 and flat when using double-layer structure
Change layer 402.Wherein, mask layer 401 can be silicon oxynitride；Planarization layer 402 can select carbon-free dielectric layer material shape
At the suitable materials such as especially carbon-free novel medium material, such as SiONH.
Carbon-free planarization layer 402 is selected, filling mobility can be significantly improved.Planarization layer 402 after deposit is again
It, can intensity with higher after high annealing solidifies.In this way, can fully ensure that form the medium material of planarization layer 402
Expect the filling to 300 position of fin 200 and grid with complex outline.
As a preferred embodiment, FCVD (flame CVD) technique can be used and deposit the planarization layer,
Then, solidified by high annealing.In FCVD technique, it can be used trimethylsilyl ammonia and ammonia as reaction source, it is high
The temperature of temperature annealing can be 950~1100 DEG C.
Step S03: deep trouth is formed in the dielectric layer of grid two sides.
Please refer to Fig. 5.The general lithographic etch process method of industry can be used, first pass through photoetching development, carry out deep trouth
Definition；Then, by being performed etching to dielectric layer, to form deep trouth 500 in the dielectric layer 400 that deep trouth defines position.It is deep
The filling of the spacer material for after of slot 500, forms side wall further to make in 300 two sides of grid.Thus, deep trouth 500
Need to be formed directly into 300 two sides of grid so that the lateral wall of grid 300 as deep trouth 500 inner sidewall and with 500 phase of deep trouth
It is logical.The deep trouth 500 that the wherein side of grid 300 is schematically illustrated in figure, is not construed as limitation of the invention.
Step S04: spacer material is deposited in deep trouth.
Please refer to Fig. 6.Specifically, can be formed sediment by the method for plasma enhanced atomic layer deposition (PEALD) in the present embodiment
Product spacer material 600 '.Spacer material 600 ' is preferably silicon nitride, also, spacer material 600 ' needs at least to fill out deep trouth 500
It is full.
Step S05: extra spacer material except removal deep trouth.
Please refer to Fig. 7.Wet etching can be used, remove the spacer material 600 ' except deep trouth 500.For example, heat can be used
Phosphoric acid removes the spacer material 600 ' except deep trouth 500, i.e., removal, which is used to form except the deep trouth 500 of side wall, is located at dielectric layer
Spacer material 600 ' on 400 surfaces.After etching, remaining spacer material 600 ' still fills up deep trouth 500, is used for subsequent production side
Wall is used.
Step S06: removal dielectric layer material forms side wall in grid two sides.
Please refer to Fig. 8.Dry etching can be used in the etching of this step；Also, it when removing dielectric layer material 400, can be used
Use O2Dry etch process as etching gas.After etching, it will be formed in 300 two sides of grid and meet semiconductor technology standard
Required side wall 600.
In addition, after completing the procedure, other techniques to form cmos device can be continued to execute, these processing steps can
To be formed using method familiar to those skilled in the art, details are not described herein.
In conclusion depositing a kind of novel medium material for having high fluidity the invention firstly uses the process of FCVD
Material is used as planarization layer, and this material is not carbon containing, and after high annealing, irregular complex is can be filled in intensity with higher
The flute surfaces of profile can fully ensure that the filling of fin and grid in this way.Then side wall region is determined by chemical wet etching
Justice is good, then deposits spacer material by the method for plasma enhanced atomic layer deposition (PEALD), and spacer material is filled into deep trouth
In.Finally material removal medium, the side wall of FinFET is ultimately formed.Meanwhile technique of the invention can be super with conventional silicon substrate
Large scale integrated circuit manufacturing technology is compatible, has simple, and convenient, period short feature reduces process costs.
Above is merely a preferred embodiment of the present invention, the scope of patent protection that embodiment is not intended to limit the invention,
Therefore all to change with equivalent structure made by specification and accompanying drawing content of the invention, it similarly should be included in of the invention
In protection scope.
Claims (10)
1. a kind of production method of FinFET side wall, which comprises the following steps:
Step S01: providing semi-conductive substrate, forms the fin and grid of FinFET on the semiconductor substrate；
Step S02: the fin and grid are completely covered dielectric layer deposited on the semiconductor substrate；
Step S03: deep trouth is formed in the dielectric layer of the grid two sides；
Step S04: spacer material is deposited in the deep trouth；
Step S05: spacer material extra except the deep trouth is removed；
Step S06: removal dielectric layer material forms side wall in the grid two sides.
2. the production method of FinFET side wall according to claim 1, which is characterized in that in step S02, the dielectric layer
At least double-layer structure includes mask layer and planarization layer from top to bottom.
3. the production method of FinFET side wall according to claim 2, which is characterized in that the mask layer is nitrogen oxidation
Silicon, the planarization layer are carbon-free dielectric layer.
4. the production method of FinFET side wall according to claim 2, which is characterized in that the planarization layer is SiONH.
5. the production method of FinFET side wall according to claim 4, which is characterized in that using described in the deposit of FCVD technique
Then planarization layer is solidified by high annealing.
6. the production method of FinFET side wall according to claim 5, which is characterized in that use three in the FCVD technique
As reaction source, the temperature of the high annealing is 950~1100 DEG C for silicyl ammonia and ammonia.
7. the production method of FinFET side wall according to claim 1, which is characterized in that in step S04, the side wall material
Material is silicon nitride.
8. the production method of FinFET side wall according to claim 1, which is characterized in that use plasma enhanced atomic layer
Deposition process deposits the spacer material.
9. the production method of FinFET side wall according to claim 1, which is characterized in that in step S05, using hot phosphoric acid
Remove spacer material extra except the deep trouth.
10. the production method of FinFET side wall according to claim 1, which is characterized in that in step S06, using dry method
Etching, and use O2As etching gas, the dielectric layer material is removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811560774.4A CN109599342B (en) | 2018-12-20 | 2018-12-20 | Manufacturing method of FinFET side wall |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811560774.4A CN109599342B (en) | 2018-12-20 | 2018-12-20 | Manufacturing method of FinFET side wall |
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| Publication Number | Publication Date |
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| CN109599342A true CN109599342A (en) | 2019-04-09 |
| CN109599342B CN109599342B (en) | 2022-07-05 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515215A (en) * | 2012-06-28 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing fin field effect tube |
| CN105185711A (en) * | 2014-06-19 | 2015-12-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method and electronic device |
| CN105765728A (en) * | 2013-12-24 | 2016-07-13 | 英特尔公司 | Techniques for trench isolation using flowable dielectric materials |
-
2018
- 2018-12-20 CN CN201811560774.4A patent/CN109599342B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515215A (en) * | 2012-06-28 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing fin field effect tube |
| CN105765728A (en) * | 2013-12-24 | 2016-07-13 | 英特尔公司 | Techniques for trench isolation using flowable dielectric materials |
| CN105185711A (en) * | 2014-06-19 | 2015-12-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method and electronic device |
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